CN104360326B - Digital storage and forwarding type interference system - Google Patents

Abstract

The invention provides a digital store and forward interference system, which belongs to the field of electronic communication. The invention can conduct detection, deception and interference to the radiation source, wherein the deception in distance, speed and height can be completed during deception. The present invention includes 7 external SMA interfaces, the main lobe is judged through the radar wave envelope provided externally, and the programmable gate array device can automatically align the sampling data bits of the intermediate frequency radar wave input from the outside and process the data to control the digital frequency synthesizer With external power amplifier, the detection, deception and interference of radiation sources can be realized.

Description

A digital store and forward jamming system

technical field

The invention belongs to the field of electronic communication, in particular to a digital store and forward interference system.

Background technique

Signal delay technology is widely used in the field of communication, such as communication switching equipment, radar deception equipment, etc., and often uses this technology to achieve goals.

In communication instruments, many devices need to use delay technology; such as oscilloscopes, in many applications for observing complex signal waveforms, it is often necessary to display a small part of a waveform and let it occupy the entire screen. When a waveform is selected, it is powerless to use the standard time base through the normal trigger method, so a dual time base structure is generally used, which requires the introduction of delay technology to delay the second time base. The general method to achieve signal delay in civilian use is to use a delay line, and the delay is obtained by propagating the signal on the delay line; the disadvantage of the above method is that the delay line is bulky and the delay is uncontrollable, which is not accurate enough for precision instruments.

In the field of radar, such as search and warning radar, the radar can detect and monitor targets as early as possible in the largest possible range, ensuring that the opponent's target has sufficient time to prepare for the enemy before approaching the defense zone. The delay technique can be used to spoof the search and warning radar. Using this technology, on the one hand, it can deceive the enemy's radar to achieve strategic effects; on the other hand, it can deceive its own radar, which is suitable for use in exercises and training where it is impossible to use real aircraft as the target, to achieve exercise teaching Effect.

Due to the above situations, domestic demand for delay technology, especially digital store-and-forward technology, is getting higher and higher. Store-and-forward technology has become an important means of radar distance deception, track deception, and altitude deception. There are some domestic studies and patents on the design of the store-and-forward system, such as Zhou Xuli (Research on the distance deception and track deception of search and warning radar [D]. North University of China, 2008: 27.) proposed the radar distance and track deception The scheme, that is, distance deception is realized by delay modulation and amplification of the received radar illumination signal; Tian Xiaowei (a memory with real-time store-and-forward function, Chinese utility model patent, 201220069420.1[P]. 2012-09-05. ) proposed a memory with real-time store-and-forward function, which mainly includes memory, data interface module, data storage module, state control module and real-time output module. The traditional store-and-forward system mentioned in the above literature and the radar deception effect are based on distance deception and speed deception. The system function is relatively simple, and the deception function is relatively simple. Due to the use of external memory, the minimum delay of the system is relatively large. The deception detection method Basically, simulation is performed by modeling. In practical applications, the input and output links of the store-and-forward system often have problems such as timing asynchrony and data bit misalignment, resulting in uncorrectable errors in output data. The effect of verifying deception is often different from the actual one, thus causing flaws in the system design.

Contents of the invention

The invention provides a digital storage and forwarding jamming system, which can integrate signal detection, deception, and jamming, and realize the deception of distance, speed, and height of the radar when the anti-jamming mode is turned on; the invention is simple to implement and works Stable, wide input bandwidth.

The present invention specifically adopts the following technical solutions:

A digital store-and-forward jamming system, the structure of which is shown in Figure 2 and Figure 3, including a digital-to-analog conversion output port 1, a Doppler frequency multiplication reference output port 2, a frequency synthesis input port 3, and a reference frequency input port 4 , external radar wave envelope input port 5, saturated power intermediate frequency radar wave input port 6, low power intermediate frequency radar wave input port 7, connector 8, first analog-to-digital converter 16, FPGA module 17, digital frequency synthesizer 18, Digital-to-analog converter 19, clock chip 20, memory 21, single-chip microcomputer 22, second analog-to-digital converter 23 and DLVA analog-to-digital converter 25;

The saturated power intermediate-frequency radar wave input port 6 is connected with the first analog-to-digital converter 16, and the low-power intermediate-frequency radar wave input port 7 is connected with the second analog-to-digital converter 23, and the first analog-to-digital converter 16 and The second analog-to-digital converter 23 is connected with the FPGA module 17 respectively;

Described external radar wave envelope input port 5 is connected with DLVA analog-to-digital converter 25, and the output end of DLVA analog-to-digital converter 25 is connected with FPGA module 17 by CMOS level conversion device;

Described single-chip microcomputer 22 is connected with FPGA module 17, clock chip 20, the second analog-to-digital converter 23 respectively, and described single-chip microcomputer 22 is connected with described connector 8 by RS422 interface;

Described FPGA module 17 is connected with digital frequency synthesizer 18 by SPI interface, is used to control digital frequency synthesizer 18 to produce Doppler frequency multiplication reference in real time; The general output interface of described FPGA module 17 is connected with connector 8 to output external Power control signal; described digital-to-analog converter 19 and FPGA module 17 are communicated by LVDS signal, can be further connected with FPGA module 17 by locked delay loop (DLL) to ensure FPGA module 17 and digital-analog at digital-to-analog converter 19 output terminals The data clock beats of the converter 19 are aligned;

The frequency synthesis input port 3 is connected with the clock chip 20, the reference frequency input port 4 is connected with the digital frequency synthesizer 18, and the output port of the digital frequency synthesizer 18 is connected with the Doppler frequency multiplication reference output port 2, The output end of the digital-to-analog converter 19 is connected with the digital-to-analog conversion output port 1;

The clock chip 20 provides clock beats to the first analog-to-digital converter 16, the digital-to-analog converter 19, the second analog-to-digital converter 23 and the DLVA analog-to-digital converter 25 respectively; the whole system power supply is provided by the motherboard through the connector 8 ; The memory 21 is connected with the FPGA module 17 .

The second digital-to-analog converter 23 samples the radar wave input to the low-frequency intermediate-frequency radar wave input port 7, and the sampled signal is input to the FPGA module 17 by a low-voltage differential signal mode (LVDS) to form a radar deception wave;

The first analog-to-digital converter 16 samples the radar wave of the saturated power intermediate frequency radar wave input port 6, and the sampled signal is input to the FPGA module 17 by LVDS and is stored in the memory 21 as the detection information of the radar wave, so as to achieve The purpose of investigation; further, the stored information is imported into the host computer through the reserved network port for analysis, and the characteristics of the radiation source are obtained;

The DLVA analog-to-digital converter 25 samples the signal of the external radar wave envelope input port 5, and the sampled signal is input to the FPGA module 17 as the basis for judging the main lobe of the radar wave through a CMOS level conversion device, so that only Key waveforms are stored to compress the storage capacity, without the need to increase external memory as in the prior art; based on the signal input by the DLVA analog-to-digital converter 25, the FPGA module 17 adjusts the radar wave pulse amplitude in different ranges to achieve target height deception Purpose;

When the whole system starts to work, the single-chip microcomputer 22 configures the second analog-to-digital converter 23 to enter the test mode. At this time, the four channels of the second analog-to-digital converter 23 send specific test patterns, and the internal data conversion unit 14 of the FPGA module 17 receives The sampling point that the second analog-to-digital converter 23 transmits, if the sampling point is different from the above-mentioned test pattern, then the FPAG module 17 is by adjusting the row data shift control pin of the serial-to-parallel converter in its internal data conversion unit 14 to slide the parallel data up and down, and at the same time detect whether the data after sliding is aligned with the test pattern; once the alignment is detected, the FPGA module 17 will shift the fixed row of data to the control pin, and at the same time generate a notification signal to trigger the single-chip microcomputer to configure the second analog-to-digital converter 23 Enter normal working mode;

The structure of FPGA module 17 is as shown in Figure 4:

1) In the fraud mode, after its internal data conversion unit 14 receives the sampling data of the second analog-to-digital converter 23, the collected data is passed to the multiplexing selector 9 according to the beat frequency, and the multiplexing selector The device 9 transmits the data to the entry FIFO unit 10 according to the beat frequency. Once the entry FIFO unit 10 receives the DLVA signal transmitted by the threshold determination unit 26, it starts to release the data from the multiplexing selector 9 and transmits it according to the clock beat. Give main storage FIFO unit 11, change the empty state of main storage FIFO unit 11 output signals simultaneously; Export FIFO unit 12 detects that the state of empty signal changes from 1 to 0 and then starts its internal timer to start counting, once timing reaches and FPGA After the delay parameter configured by the single-chip microcomputer 22 connected to the module 17, the export FIFO unit 12 starts to read the data in the main storage FIFO unit 11 according to the clock beat and passes the data to the data conversion unit 15 for parallel-to-serial conversion, and finally the data is transmitted to multiple The multiplexing selector 13 outputs to the digital-to-analog converter 19 and outputs a spoofing signal; on the basis of realizing the distance spoofing, the spoofing unit 27 controls the output frequency of the external digital frequency synthesizer 18 in real time through the SPI interface 28 to achieve superposition on the carrier The purpose of the Doppler frequency is to realize the speed deception function; after the gain control unit 24 receives the control signal of the deception unit 27, it analyzes the data input via the DLVA analog-to-digital converter 25, estimates the power of the input signal at this time and generates a power control The signal is connected to the connector 8 connected to the FPGA module 17, and the signal is used to control the magnification of the pulse signals of different ranges output by the external T/R assembly to the digital-to-analog converter 19, so as to achieve a high degree of deception;

2) In the detection mode, the multiplexer 9 releases the data of the data conversion unit connected to the first analog-to-digital converter 16, and stores the converted data into the memory 21, while shielding and second analog-to-digital conversion The data of the data conversion unit 14 connected to the device 23.

The beneficial effects of the present invention are:

1) The digital store-and-forward jamming system provided by the present invention solves the problems of incoherent clocks and low signal-to-noise ratio of waveforms in investigation and storage in previous designs by setting multiple external interfaces;

2) Solve the problem of misalignment of data bits in the traditional design, improve the output effect of the device, and only store the key waveforms to compress the storage capacity, so that it is not necessary to increase the external memory as in the previous design, and solve the problem of using an external memory in the traditional design. The deficiency of the minimum delay is increased, and the delay is more accurate; at the same time, the present invention enables multi-beam radar deception to be highly deceptive;

3) The present invention integrates detection, deception and interference, and can store a maximum pulse waveform of 200us, with a waveform delay accuracy of 0.41us; the ground control station can control the equipment to enter the power-on, standby, detection, deception, and interference modes at any time, enabling the radar to When the anti-jamming mode is turned on, the distance, speed, and altitude can be deceived, and a stable flight path can be formed.

Description of drawings

Figure 1 is a block diagram of a general store-and-forward structure;

Fig. 2 is a schematic diagram of the external interface of the present invention;

Fig. 3 is a schematic diagram of the hardware structure of the present invention;

Fig. 4 is FPGA internal module structure design among the present invention;

Fig. 5 is the store-delay-forward effect of the digital store-and-forward interference system provided in the specific embodiment;

Fig. 6 is an effect diagram of the input wave and the forwarding wave of the digital store and forward interference system provided by the specific embodiment;

Among them, 1: digital-to-analog conversion output port, 2: Doppler frequency multiplication reference output port, 3: frequency synthesis input port, 4: reference frequency input port, 5: external radar wave envelope input port, 6: saturation power intermediate frequency Radar wave input port, 7: low power intermediate frequency radar wave input port, 8: connector, 9: internal multiplexer, 10: entry FIFO unit, 11: main storage FIFO unit, 12 exit FIFO unit, 13: multiple Multiplexer, 14: data conversion unit, 15: data conversion unit, 16: first analog-to-digital converter, 17: FPGA module, 18: digital frequency synthesizer, 19: digital-to-analog converter, 20: clock chip, 21: memory, 22: microcontroller, 23: second analog-to-digital converter, 24: gain control unit inside FPGA, 25: DLVA analog-to-digital converter, 26: threshold determination unit inside FPGA, 27: deception control inside FPGA Unit, 28: SPI communication interface inside FPGA, 29, 30: isolation FIFO unit.

detailed description

The utility model will be described in detail below in conjunction with the accompanying drawings and specific embodiments.

The main structure of the digital store-and-forward jamming system provided by this embodiment is shown in Figure 2 and Figure 3. After the high-frequency signal is received by the T/R component, two channels of 100M-500M intermediate frequency signals with low power and saturated power are output through down-conversion. , while detecting the envelope of the high-frequency signal to generate an envelope signal; the low-power signal is input to the second analog-to-digital converter 23 through the low-power intermediate-frequency radar wave input port 7, and then input to the FPGA module 17 for storage and processing. Spoofing signal; saturated power signal is input to the first analog-to-digital converter 16 through the saturated power intermediate frequency radar wave input port 6 for storage; the generated envelope signal is input to the DLVA analog-to-digital converter through the external radar wave envelope input port 5 In 25, it is judged whether the pulse arrives;

The digital-to-analog conversion output port 1, as the output port of the digital-to-analog converter 19, is the output port of the processed intermediate frequency radar wave. The frequency of the output intermediate frequency signal is 100Mhz～500Mhz, the power is -15dbm～0dbm, and the main-to-clutter ratio is greater than 25dbc; The 100Mhz Doppler frequency multiplication reference output port 2 is used as the output end of the digital frequency synthesizer 18, and its output range is 99.9Mhz～100.1Mhz, and the power is 0dbm; the external 1.25G frequency synthesis input port 3 is used as the input end of the clock chip 20, Provide beat frequency for the first analog-to-digital converter 16, digital-to-analog converter 19, second analog-to-digital converter 23 and DLVA analog-to-digital converter 25 in the system; the external 100Mhz reference frequency input port 4 is used as the digital frequency synthesizer 18 Reference frequency input port, input power is -2dbm; External radar wave envelope input port 5 is used as the input port of DLVA analog-to-digital converter 25, provides a basis for judging the main lobe of radar wave; Saturation power intermediate frequency radar wave input port 6 is used as the first The input terminal of the analog-to-digital converter 16 receives a signal with a frequency of 100Mhz-500Mhz and a power of 0dbm. The first analog-to-digital converter 16 samples the signal and stores it in the memory 21 via the FPGA module 17 as a radar wave for detection. Storage; the low-power intermediate-frequency radar wave input port 7 is used as the input end of the second analog-to-digital converter 23, and the input frequency is 100Mhz～500Mhz, and the power is a signal of -40dbm～0dbm, and the second analog-to-digital converter 23 samples the input signal , processed by the FPGA module 17 and generate a spoof signal.

When the system starts to work, the single-chip microcomputer 22 configures the second analog-to-digital converter 23 to enter the test mode, and in the test mode, four channels (QD, ID, Q, I, each road is 12bit) of the second analog-to-digital converter 23 will be Output a fixed test pattern. The specific format of the test pattern output in one clock beat is: the QD channel at T ₀ is FF7h, the ID channel is FEFh, the Q channel is 008h, and the I channel is 010h; T ₁ repeats the T ₀ time pattern; _At T2, the QD channel pattern is exchanged with the Q channel pattern, and the ID channel is exchanged with the I channel pattern. Until T5, each channel repeats the _T0 time pattern, and the above cycle is repeated _;

The second analog-to-digital converter 23 is connected with the internal data conversion unit 14 of the FPGA module 17, and the data conversion unit 14 mainly has two effects: 1) each bit of each channel is regarded as serial data, and serial-parallel is carried out Convert to reduce the internal processing rate in this way; 2) judge whether the input data is a test pattern, if it is not a test pattern, then shift the parallel data part of the serial-to-parallel conversion back and forth, continue to judge whether it is a test pattern, and judge by shifting, Stop shifting until the final test pattern. At this time, configure the second analog-to-digital converter 23 in the working mode, and the down-converted waveform is input from the low-power intermediate-frequency radar wave input port 7 to the second analog-to-digital converter 23 for sampling.

The internal structure of the FPGA module 17 that is used to detect and generate fraudulent signals in the present embodiment is as shown in Figure 4:

1) In the fraud mode, the data conversion unit 14 transmits data to the multiplexer 9, and the multiplexer 9 releases the data of the data conversion unit 14 connected to the second analog-to-digital converter 23, and shields the data with the second analog-to-digital converter 23. The data of the data conversion unit that an analog-to-digital converter 16 is connected;

After the DLVA analog-to-digital converter 25 samples the radar wave envelope signal, the sampled data is output to the threshold judging unit 26 in the FPGA module 17 to judge whether the pulse arrives; if the input data exceeds the preset threshold, then it is considered that the pulse arrives. The timing threshold determination unit 26 will output the DLVA signal to the entry FIFO unit 10;

When the entry FIFO unit 10 does not receive the DLVA signal from the threshold determination unit 26, it will shield all input signals; when the entry FIFO unit 10 receives the DLVA signal, it will release the signal of the multiplexer 9 to the main storage FIFO unit 11, while the main storage FIFO unit 11 changes the state of the empty signal released to the outlet FIFO unit 12, indicating that it starts to store data;

After the exit FIFO unit 12 detects that the empty signal state that the main storage FIFO unit 11 releases changes, it starts its internal timer and starts counting; when the timer reaches the threshold configured by the cheating unit 27, it starts to read the main storage FIFO unit 11 and transmit the data to the data conversion unit 15 for parallel-to-serial conversion; after the exit FIFO unit 12 detects that the empty signal state recovers, stop reading the data of the main storage FIFO unit 11; the cheating unit 27 controls the gain control unit 24 and the exit FIFO unit The control signal of 12 is generated by the SPI interface 28 transmission after receiving the flight control instruction by the single-chip microcomputer 22 outside the FPGA module 17;

After the isolation FIFO unit 29 receives the data from the data conversion unit 15, the data is released to the multiplexer 13 according to the clock provided by the multiplexer 13, and the multiplexer 13 transmits the input data to the external data The analog converter 19 outputs a spoofing signal via the digital-to-analog conversion output port 1, and the spoofing signal can reach the function of distance spoofing through full forwarding or cycle measurement forwarding mode; Control the output frequency of the external digital frequency synthesizer 18 to achieve the purpose of superimposing the Doppler frequency on the carrier, and realize the speed deception function; after the gain control unit 24 receives the control signal of the deception unit 27, it analyzes the frequency via the DLVA analog-to-digital converter 25 The input data estimates the power of the input signal at this time and generates a power control signal to the connector 8, which is used to control the amplification factor of the output signal of the digital-to-analog converter 19 by the external R/T component to achieve a high degree of deception;

Described full forwarding mode is specifically as follows: DLVA analog-to-digital converter 25 communicates with FPGA module 17 by CMOS level conversion device, the data after DLVA analog-to-digital converter 25 samples and the threshold that threshold determination unit 26 sets in FPGA module 17 For comparison, once the sampled data is higher than the threshold, the delayed forwarding starts, and once the sampled data is lower than the threshold, the system stops storing. From the perspective of input and output signals, the system operates as forwarding main lobe and side lobe; using this The method can successfully form a track on the radar and achieve distance and speed deception;

Described measurement cycle forwarding mode is specifically as follows: when the data sampled by DLVA analog-to-digital converter 25 is higher than the set threshold, then the delay forwarding begins, and the main lobe width is set according to the detected radar wave characteristics, then the system forwarding time Fixed; from the point of view of the input and output signals, the system operates to only retransmit the main lobe; using this method, it is possible to successfully form a track on the radar and achieve high deception;

2) In the investigation mode, the data sampled by the first analog-to-digital converter 16 is transmitted to the memory 21 via the multiplexer 9 for storage.

The real delay forwarding effect of this embodiment is shown in Figure 5. During the test, the 300Mhz signal of 48us pulse modulation is input at the low-power intermediate frequency radar wave input port, and the envelope signal after detection is input at the external radar wave envelope input port. The signal of the analog conversion output port is shown in the figure. The upper signal in the figure is the input envelope signal, and the lower output is the original signal delayed by 15us (because the delayed signal does not pass through the detector, the displayed result is the modulated 300Mhz signal) . The comparison between the input wave and the forwarding wave of the present invention is shown in Figure 6, and the waveform delay forwarding is controlled by the host computer in real time; the upper signal in the figure is the signal forwarded by the present invention, and the lower part is the input waveform signal.

Claims (7)

1. A digital store-and-forward jamming system, comprising a digital-to-analog conversion output port (1), a low-power intermediate-frequency radar wave input port (7), a connector (8), a first analog-to-digital converter (16), and an FPGA Module (17), digital frequency synthesizer (18), digital-to-analog converter (19), clock chip (20), memory (21), single-chip microcomputer (22) and the second analog-to-digital converter (23), it is characterized in that , also includes Doppler frequency multiplication reference output port (2), frequency synthesis input port (3), reference frequency input port (4), external radar wave envelope input port (5), saturated power intermediate frequency radar wave input port ( 6) and DLVA analog-to-digital converter (25); The saturated power intermediate-frequency radar wave input port (6) is connected with the first analog-to-digital converter (16), and the low-power intermediate-frequency radar wave input port (7) is connected with the second analog-to-digital converter (23). The first analog-to-digital converter (16) and the second analog-to-digital converter (23) are connected with the FPGA module (17) respectively; The external radar wave envelope input port (5) is connected with the DLVA analog-to-digital converter (25), and the output end of the DLVA analog-to-digital converter (25) is connected with the FPGA module (17) by a CMOS level conversion device; Described single-chip microcomputer (22) is connected with FPGA module (17), clock chip (20), the second analog-to-digital converter (23) respectively, and described single-chip microcomputer (22) is connected with described connector (8) by RS422 interface; Described FPGA module (17) is connected with digital frequency synthesizer (18) by SPI interface, is used to control digital frequency synthesizer (18) to produce Doppler frequency multiplication reference in real time; The general output interface of described FPGA module (17) Connect with connector (8) and be used for outputting external power control signal; Described digital-to-analog converter (19) communicates with FPGA module (17) by LVDS signal, and described frequency synthesis input port (3) and clock chip (20) Connect, the reference frequency input port (4) is connected with the digital frequency synthesizer (18), the output port of the digital frequency synthesizer (18) is connected with the Doppler frequency multiplication reference output port (2), and the digital frequency synthesizer The output terminal of the analog converter (19) is connected with the digital-to-analog conversion output port (1); Described clock chip (20) provides clock beat to first analog-to-digital converter (16), digital-to-analog converter (19), second analog-to-digital converter (23) and DLVA analog-to-digital converter (25) respectively; The system power supply is provided by the motherboard through the connector (8); the memory (21) is connected with the FPGA module (17). 2. digital storage and forwarding type jamming system according to claim 1, is characterized in that, described digital-to-analog converter (19) output end is connected with FPGA module (17) to ensure FPGA module by locking delay loop (DLL) (17) is aligned with the data clock beat of the digital-to-analog converter (19). 3. digital storage and forwarding type interference system according to claim 1, is characterized in that, described FPGA module (17) comprises the first data conversion unit (14), the second data conversion unit (15) and the 3rd data Conversion unit, first multiplexer (9) and second multiplexer (13), entry FIFO unit (10), threshold judgment unit (26), main storage FIFO unit (11), exit FIFO unit (12), spoofing unit (27), SPI interface (28) and isolation FIFO unit (29), the specific process of described FPGA module (17) working in reconnaissance mode and spoofing mode respectively is as follows: A. Investigation mode: the first multiplexer (9) releases the data of the third data conversion unit connected to the first analog-to-digital converter (16), and stores the converted data into the memory (21), Simultaneously shield the data of the first data conversion unit (14) that is connected with the external second analog-to-digital converter (23); B. cheating mode: the first data conversion unit (14) transmits the sampling data of the second external analog-to-digital converter (23) to the first multiplexer (9), and the first multiplexer (9) ) release the data of the first data conversion unit (14) connected to the second analog-to-digital converter (23), and shield the data of the third data conversion unit connected to the first analog-to-digital converter (16); After the described external DLVA analog-to-digital converter (25) samples the radar wave envelope signal, the sampled data is output to the threshold determination unit (26) in the FPGA module (17) to judge whether the pulse arrives; if the input data exceeds Preset threshold, then consider pulse arrival, threshold determination unit (26) will output DLVA signal to entrance FIFO unit (10); After the entry FIFO unit (10) receives the DLVA signal, the signal of the first multiplexer (9) is released to the main storage FIFO unit (11), and now the main storage FIFO unit (11) changes its direction to the exit FIFO unit (12) ) state of the released empty signal, indicating that data is to be stored; After the exit FIFO unit (12) detects that the empty signal state of the main storage FIFO unit (11) has changed, it starts its internal timer and starts counting; when the timer reaches the threshold configured by the cheating unit (27), the exit FIFO Unit (12) starts to read the data of main storage FIFO unit (11) and transmits to the second data conversion unit (15) and carries out parallel-serial conversion; The external single-chip microcomputer (22) generates through SPI interface (28) transmission after receiving the flight control instruction; After the isolation FIFO unit (29) receives the data of the second data conversion unit (15), the data is released to the second multiplexer (13) according to the clock provided by the second multiplexer (13), The second multiplexer (13) transmits the input data to the external digital-to-analog converter (19) and outputs a spoofing signal through the digital-to-analog conversion output port (1). To achieve the function of distance deception. 4. digital storage and forwarding type jamming system according to claim 3, is characterized in that, described fraud unit (27) controls the output frequency of external digital frequency synthesizer (18) in real time by SPI interface (28), reaches in The purpose of superimposing the Doppler frequency on the carrier is to cooperate with the system delay forwarding to realize the speed deception function. 5. digital storage and forwarding type jamming system according to claim 3, is characterized in that, described FPGA module (17) also comprises gain control unit (24), and described gain control unit (24) receives fraudulent unit ( 27) after the control signal, analyze the data input via the DLVA analog-to-digital converter (25), estimate the power size of the input signal at this moment and generate the power control signal to the connector (8) connected with the FPGA module (17), use It is used to control the amplification factor of the pulse signals in different ranges output by the external T/R component to the digital-to-analog converter (19), so as to achieve the purpose of highly deceiving. 6. digital storage and forwarding type jamming system according to claim 5, is characterized in that, described cheating unit (27) is received flight control instruction by external single-chip microcomputer (22) to the control signal of gain control unit (24) Then generate by SPI interface (28) transmission. 7. The digital store-and-forward jamming system according to claim 3, characterized in that, the second analog-to-digital converter (23) and the first data conversion unit (14) also have a test before entering the normal operating mode Mode, specifically as follows: the single-chip microcomputer (22) configures the second analog-to-digital converter (23) to enter the test mode, and now four channels of the second analog-to-digital converter (23) send specific test patterns; while the FPGA module (17) The internal first data conversion unit (14) of the internal first data conversion unit (14) receives the sampling point transmitted by the second analog-to-digital converter (23), if the sampling point is different from the above-mentioned test pattern, the FPAG module (17) adjusts its internal first data The parallel data shift control pin of the serial-to-parallel converter in the conversion unit (14) slides the parallel data, and detects whether the data after sliding is aligned with the test pattern; once the alignment is detected, the FPGA module (17) shifts the fixed parallel data bit control pin, and simultaneously generate a notification signal to trigger the microcontroller to configure the second analog-to-digital converter (23) to enter the normal working mode.