CN104360326B - Digital storage and forwarding type interference system - Google Patents
Digital storage and forwarding type interference system Download PDFInfo
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- CN104360326B CN104360326B CN201410679828.4A CN201410679828A CN104360326B CN 104360326 B CN104360326 B CN 104360326B CN 201410679828 A CN201410679828 A CN 201410679828A CN 104360326 B CN104360326 B CN 104360326B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
- G01S7/38—Jamming means, e.g. producing false echoes
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- Radar, Positioning & Navigation (AREA)
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- Radar Systems Or Details Thereof (AREA)
Abstract
The invention provides a digital storage and forwarding type interference system, and belongs to the field of electronic communication. The system can investigate, deceive and interfere in a radiation source, and deception on distance, speed and height can be achieved. The system comprises seven external SMA interfaces, main lobe judgment is carried out through a radar wave envelope provided by the outside, a programmable gate array device can be automatically flush with medium-frequency radar wave sampled data bits input from the outside and process data, a digital frequency synthesizer and an external power amplifier are controlled, and investigation, deception and interference of the radiation source are achieved.
Description
Technical field
The invention belongs to electronic communication field, and in particular to a kind of stored digital and repeating jamming system.
Background technology
Signal delay technology is widely used in the field of communications, such as communication exchange equipment, radar deception equipment etc., usually
Target is realized using the technology.
In communication instrument, many equipment need to use delay technology；Such as oscillograph, in many observation sophisticated signal ripples
In the application scenario of shape, generally require to show the sub-fraction of a waveform, and allow it to occupy whole screen, it is complete in observational study
During a certain selected waveform of portion's TV signal, the use of base during standard is helpless by the method for triggered as normal, so typically
The structure of dual time base is adopted all, this is accomplished by introducing delay technology to postpone base when second.Signal delay is realized on civilian
Conventional method is to use delay line, is postponing above-the-line promotion being postponed by signal；The shortcoming of said method is delay line
Bulky, delay is uncontrollable, and for precision instrument, such delay is not accurate enough.
In field of radar, surveillance radar is such as searched for, the radar can be found in scope as big as possible as early as possible
And monitoring target, it is ensured that other side's target had before defence area is closed on the sufficient time carry out meet enemy prepare.And delay technology can be with
For cheating to searching for surveillance radar.Using the technology, on the one hand enemy radar can be cheated, reach strategic effect
Really；On the other hand oneself radar can be cheated, is adapted to be used as target using true aircraft in manoeuvre, training etc.
In the case of use, reach manoeuvre teaching efficiency.
Between the above situation, the domestic demand to delay technology, especially stored digital and retransmission technique is increasingly
Height, storage have become the important means cheated to distance by radar deception, track spoofing, height with retransmission technique.To storage forwarding
There are part research and patent in the design country of system, and (range gate deception and track spoofing to searching for surveillance radar grinds such as Zhou Xuli
Study carefully [D]. Northcentral University, 2008:27.) it is by receiving to propose to distance by radar and track spoofing scheme, i.e. range gate deception
Radar illumination signal carry out time delay modulation and amplify realize；Tian Xiaowei (a kind of memorizer with real-time storage forwarding capability,
Chinese utility model patent, 201220069420.1 [P] .2012-09-05.) one kind is proposed with real-time storage forwarding capability
Memorizer, mainly comprising memorizer, data interface module, data memory module, status control module and real-time output module.
Traditional store-and-forward system and radar deception effect mentioned by above-mentioned document is built upon range gate deception and velocity gate deception
On the basis of, systemic-function is relatively simple, and deception function is fairly simple, due to using external memory storage, system lowest latency to compare
Greatly, it is essentially all to be emulated by modeling to cheat the method for inspection, and in actual applications, the input of store-and-forward system is defeated
Outgoing link often occurs the problems such as sequential is asynchronous, data bit is not lined up, and causes the not repairable mistake of output data, single
Verified by emulating deception effect often with actually disagree, so as to cause the defect of system design.
The content of the invention
The invention provides a kind of stored digital and repeating jamming system, the system can collect signal investigation, deception, dry
Disturb in one, realize that radar enters the deception of row distance, speed, height in the case where anti-tampering pattern is opened；The present invention realizes simple, work
Stablize, input tape is wide.
The present invention is specifically adopted the following technical scheme that：
A kind of stored digital and repeating jamming system, its structure as shown in Figures 2 and 3, including digital-to-analogue conversion delivery outlet
1st, Doppler's frequency multiplication benchmark delivery outlet 2, the comprehensive input port 3 of frequency, reference frequency input port 4, outside radar wave envelope input port 5, full
With power intermediate frequency radar wave input port 6, low-power if radar ripple input port 7, connector 8, the first analog-digital converter 16, FPGA
Module 17, digital frequency synthesizer 18, digital to analog converter 19, clock chip 20, memorizer 21, single-chip microcomputer 22, the second modulus turn
Parallel operation 23 and DLVA analog-digital converters 25；
The saturation power if radar ripple input port 6 is connected with the first analog-digital converter 16, the low-power intermediate frequency thunder
It is connected up to ripple input port 7 with the second analog-digital converter 23, first analog-digital converter 16 and the second analog-digital converter 23 are distinguished
It is connected with FPGA module 17；
The outside radar wave envelope input port 5 is connected with DLVA analog-digital converters 25, DLVA analog-digital converters 25 it is defeated
Go out end to be connected with FPGA module 17 by CMOS level conversion device；
The single-chip microcomputer 22 is connected with FPGA module 17, clock chip 20, the second analog-digital converter 23 respectively, the monolithic
Machine 22 is connected with the connector 8 by RS422 interfaces；
The FPGA module 17 is connected with digital frequency synthesizer 18 by SPI interface, for controlling Digital Frequency Synthesize
Device 18 produces Doppler's frequency multiplication benchmark in real time；The general output interface of the FPGA module 17 is connected outer to export with connector 8
Portion's power control signal；The digital to analog converter 19, further can be turned in digital-to-analogue by LVDS signal communications with FPGA module 17
19 outfan of parallel operation is connected with FPGA module 17 by locking ring retard (DLL) to guarantee FPGA module 17 with digital to analog converter 19
Data clock beat aligns；
The comprehensive input port 3 of the frequency is connected with clock chip 20, the reference frequency input port 4 and digital frequency synthesizer 18
Connection, the outfan of the digital frequency synthesizer 18 are connected with Doppler's frequency multiplication benchmark delivery outlet 2, the digital to analog converter 19
Outfan be connected with digital-to-analogue conversion delivery outlet 1；
The clock chip 20 respectively to the first analog-digital converter 16, digital to analog converter 19, the second analog-digital converter 23 and
DLVA analog-digital converters 25 provide timeticks；Whole system power supply is provided by connector 8 by motherboard；Memorizer 21 and FPGA
Module 17 connects.
The radar wave of second digital to analog converter, 23 pairs of input tremendously low frequency rate if radar ripple input ports 7 is sampled,
Signal after sampling is input into FPGA module 17 by Low Voltage Differential Signal pattern (LVDS) and forms radar deception ripple；
First analog-digital converter 16 is sampled to the radar wave of saturation power if radar ripple input port 6, sampling
Signal afterwards is input into FPGA module 17 by LVDS and as the investigation information Store to radar wave in memorizer 21, is reached
Investigation purpose；Further, stored information is imported in host computer via reserved network interface and is analyzed, obtain radiation source special
Levy；
The signal of 25 pairs of outsides of DLVA analog-digital converters radar wave packet network input port 5 is sampled, the letter after sampling
Number it is input into FPGA module 17 as radar wave main lobe foundation is judged via CMOS level conversion devices, thus can be only to crucial ripple
Shape is stored, and compresses amount of storage, without as needing to increase external memory storage in prior art；It is defeated with DLVA analog-digital converters 25
The signal for entering is foundation, and FPGA module 17 adjusts different journey area radar wave pulse amplitudes, realizes object height deception purpose；
When whole system is started working, single-chip microcomputer 22 configures the second analog-digital converter 23 and enters test pattern, and now second
Four passages of analog-digital converter 23 send specific test pattern, while the internal data converting unit 14 of FPGA module 17 connects
The sampled point of the transmission of the second analog-digital converter 23 is received, if the sampled point is different from above-mentioned test pattern, FPAG modules 17 are led to
The row data shift control pin for overregulating the deserializer in its internal Date Conversion Unit 14 is parallel to slide up and down
Data, while detecting whether the data after sliding are alignd with test pattern；Once detecting alignment, FPGA module 17 will fix row
Data shift control pin, while producing the second analog-digital converter of notification signal triggering single-chip microcomputer configuration 23 enters normal work mould
Formula；
The structure of FPGA module 17 is as shown in Figure 4：
1) in cheating mode, its internal Date Conversion Unit 14 receives the sampled data of the second analog-digital converter 23
Afterwards, institute's gathered data is passed to into multiplexing selector 9 according to beat frequency, multiplexing selector 9 is according to beat frequency
Entrance cell fifo 10 is passed data to, entrance cell fifo 10 is once received to be believed by the DLVA that thresholding identifying unit 26 is transmitted
Number, begin to let pass the data that transmit of multiplexing selector 9 and pass to primary storage cell fifo 11 according to timeticks, together
When change the empty states of 11 output signal of primary storage cell fifo；Outlet cell fifo 12 detects the state of empty signals
Its dynamic internal timer is opened after being changed into 0 from 1 and starts timing, once timing reaches the single-chip microcomputer 22 being connected with FPGA module 17 matched somebody with somebody
After the delay parameter put, export cell fifo 12 and start the data in primary storage cell fifo 11 to be read according to timeticks and incited somebody to action
Data transfer carries out parallel-serial conversion to Date Conversion Unit 15, and final data is transferred to multiplexing selector 13 and exports to digital-to-analogue
Transducer 19 simultaneously exports curve；On the basis of range gate deception is realized, deception unit 27 passes through 28 real-time control of SPI interface
The output frequency of external digital frequency synthesizer 18, reaches the purpose that Doppler frequency is superimposed on carrier wave, realizes velocity gate deception
Function；After gain control unit 24 receives the control signal of deception unit 27, analyze what is be input into via DLVA analog-digital converters 25
Data, are estimated the now watt level of input signal and produce power control signal to the connector 8 being connected with FPGA module 17,
The signal is used for the amplification of the pulse signal in the different journey areas for controlling the outside output of T/R components logarithm weighted-voltage D/A converter 19, reaches
To the purpose of height deception；
2) in investigative mode, the Date Conversion Unit that the clearance of multiplexer 9 is connected with the first analog-digital converter 16
Data, and by the data storage after conversion to memorizer 21, while the data turn that shielding is connected with the second analog-digital converter 23
Change the data of unit 14.
The invention has the beneficial effects as follows：
1) stored digital that the present invention is provided passes through to arrange multiple external interfaces with repeating jamming system, to solve in the past
Clock not coherent, the investigation low problem of stored waveform signal to noise ratio in design；
2) in solving the problems, such as traditional design, data bit is not lined up, and improves equipment output effect, and only to key waveforms
Stored, compressed amount of storage, so as to not necessarily like needing to increase external memory storage in designing in the past, using outer in solution traditional design
Portion's memorizer increases the deficiency in minimum delay so that postpone more accurate；Meanwhile, the invention enables multiple-beam radar deception
Height deception can be carried out；
3) present invention integrates investigation, cheats, disturbs, the impulse waveform of maximum storage 200us, and waveform delay precision is
0.41us；Ground control station can enter start, standby, investigation, deception, jamming pattern by control device at any time, open can radar
The deception for entering row distance, speed, height under anti-tampering pattern is opened, and forms stable flight path.
Description of the drawings
Fig. 1 is general storage forwarding structured flowchart；
Fig. 2 is the external interface schematic diagram of the present invention；
Fig. 3 is hardware architecture diagram of the present invention；
Fig. 4 is FPGA internal module structure designs in the present invention；
Stored digital and the storage delay forwarding effect of retransmitted jamming system that Fig. 5 is provided for specific embodiment；
Stored digital and the incoming wave of retransmitted jamming system and forwarding ripple design sketch that Fig. 6 is provided for specific embodiment；
Wherein, 1：Digital-to-analogue conversion delivery outlet, 2：Doppler's frequency multiplication benchmark delivery outlet, 3：Frequently comprehensive input port, 4：Reference frequency
Input port, 5：Outside radar wave envelope input port, 6：Saturation power if radar ripple input port, 7：Low-power if radar ripple is defeated
Entrance, 8：Connector, 9：Internal multiplexer, 10：Entrance cell fifo, 11：Primary storage cell fifo, 12 outlet FIFO are mono-
Unit, 13：Multiplexer, 14：Date Conversion Unit, 15：Date Conversion Unit, 16：First analog-digital converter, 17：FPGA moulds
Block, 18：Digital frequency synthesizer, 19：Digital to analog converter, 20：Clock chip, 21：Memorizer, 22：Single-chip microcomputer, 23：Second mould
Number converter, 24：Gain control unit inside FPGA, 25：DLVA analog-digital converters, 26：Thresholding inside FPGA judges single
Unit, 27：Deception control unit inside FPGA, 28：SPI communication interface inside FPGA, 29,30：Isolation cell fifo.
Specific embodiment
With reference to the accompanying drawings and detailed description this utility model is described in detail.
The stored digital that present embodiment is provided with repeating jamming system primary structure as shown in Figures 2 and 3, believe by high frequency
Number via T/R components receive after by down coversion output low-power and saturation power two-way 100M～500M intermediate-freuqncy signal, together
When detect high-frequency signal envelope, produce envelope signal；Low-power signal is input to via low-power if radar ripple input port 7
In second analog-digital converter 23, then it is input into FPGA module 17 for storing and processing generation curve；Saturation power signal
It is input into into the first analog-digital converter 16 via saturation power if radar ripple input port 6 and is stored；Produced envelope letter
Number it is input into into DLVA analog-digital converters 25 via outside radar wave envelope input port 5 and differentiates to whether pulse arrives；
Outfan of the digital-to-analogue conversion delivery outlet 1 as digital to analog converter 19, is the if radar ripple delivery outlet after processing, its
The frequency of output intermediate-freuqncy signal is 100Mhz～500Mhz, and power is -15dbm～0dbm, and the miscellaneous ratio of master is more than 25dbc；100Mhz
Outfan of the Doppler's frequency multiplication benchmark delivery outlet 2 as digital frequency synthesizer 18, its output area be 99.9Mhz～
100.1Mhz, power are 0dbm；Input of the comprehensive input port 3 of outside 1.25G frequency as clock chip 20, is first in system
Analog-digital converter 16, digital to analog converter 19, the second analog-digital converter 23 and DLVA analog-digital converters 25 provide beat frequency；It is outside
Reference frequency input of the 100Mhz reference frequencies input port 4 as digital frequency synthesizer 18, input power are -2dbm；Outward
Input of the portion radar wave envelope input port 5 as DLVA analog-digital converters 25, to judge that radar wave main lobe provides foundation；Saturation
Input of the power intermediate frequency radar wave input port 6 as the first analog-digital converter 16, incoming frequency are 100Mhz～500Mhz, work(
Signal of the rate for 0dbm, the first analog-digital converter 16 pairs signal is sampled, and stores to memorizer via FPGA module 17
Radar wave in 21 as investigation is stored；Input of the low-power if radar ripple input port 7 as the second analog-digital converter 23,
Incoming frequency is 100Mhz～500Mhz, the signal that power is -40dbm～0dbm, and the second analog-digital converter 23 is to input signal
Sampled, processed by FPGA module 17 and produced curve.
During system starts, single-chip microcomputer 22 configures the second analog-digital converter 23 and enters test pattern, in test pattern,
Four passages (QD, ID, Q, I, every is 12bit all the way) of the second analog-digital converter 23 can export fixed test pattern, one
The concrete form of test pattern of individual timeticks output is：T0Moment QD passage is FF7h, and ID passages are FEFh, and Q passages are
008h, I passage is 010h；T1Moment repeats T0Moment pattern；T2Moment QD passage pattern is exchanged with Q passage patterns, ID passages with
I passages pattern is exchanged, until T5Moment, each passage repeated T0Moment pattern, repeats to circulate above；
Second analog-digital converter 23 is connected with the Date Conversion Unit 14 inside FPGA module 17, and Date Conversion Unit 14 is led
There are two effects：1) regard each bit position of each passage as serial data, carrying out serioparallel exchange reduces interior with this
Portion's processing speed；2) judge whether the data being input into are test pattern, if not being test pattern, then to serioparallel exchange part
Parallel data carry out before and after displacement, continue to determine whether as test pattern, judged by shifting, until being finally test pattern,
Stop displacement, it is mode of operation now to configure the second analog-digital converter 23, and down coversion waveform is from the input of low-power if radar ripple
Mouth 7 is input to the second analog-digital converter 23 and is sampled.
The internal structure of the FPGA module 17 in present embodiment for investigating and producing curve is as shown in Figure 4：
1) in cheating mode, Date Conversion Unit 14 transfers data to multiplexer 9, and multiplexer 9 is let pass
The data of the Date Conversion Unit 14 being connected with the second analog-digital converter 23, and the number that shielding is connected with the first analog-digital converter 16
According to the data of converting unit；
After DLVA analog-digital converters 25 are sampled to radar wave envelope signal, sampled data is exported to FPGA module 17
In thresholding identifying unit 26 judging whether pulse arrives；If input data exceedes pre-determined threshold, then it is assumed that pulse arrives, this
When thresholding identifying unit 26 output DLVA signals are fed into mouthful cell fifo 10；
Entrance cell fifo 10 can shield all of input when not receiving from the DLVA signals of thresholding identifying unit 26
Signal；When entrance cell fifo 10 receives DLVA signals, the signal of its multiplexer 9 of letting pass is mono- to primary storage FIFO
Unit 11, while primary storage cell fifo 11 changes the state of the empty signals to the outlet release of cell fifo 12, shows to start to deposit
Storage data；
After outlet cell fifo 12 detects the empty signal conditions change of the release of primary storage cell fifo 11, start which
Internal timer starts timing；When timer reaches the thresholding that deception unit 27 configures which, start to read primary storage
The data of cell fifo 11 are simultaneously transmitted to Date Conversion Unit 15 and carry out parallel-serial conversion；When outlet cell fifo 12 is detected
After empty signal conditions are recovered, stop reading the data of primary storage cell fifo 11；Deception unit 27 is to gain control unit 24
With the control signal of outlet cell fifo 12, received by the single-chip microcomputer 22 outside FPGA module 17 and connect by SPI after flying control instruction
28 transmission of mouth is produced；
After isolation cell fifo 29 receives the data of Date Conversion Unit 15, the data are provided according to multiplexer 13
Clock let pass to multiplexer 13, multiplexer 13 by the data transfer being input into outside digital to analog converter 19 and via
Digital-to-analogue conversion delivery outlet 1 exports curve, and the curve can reach distance and be taken advantage of by full forwarding or all forward modes of survey
The function of deceiving；On the basis of range gate deception is realized, deception unit 27 is closed by 28 real-time control external digital frequency of SPI interface
Grow up to be a useful person 18 output frequency, reach on carrier wave be superimposed Doppler frequency purpose, realize velocity gate deception function；Gain control list
After unit 24 receives the control signal of deception unit 27, the data being input into via DLVA analog-digital converters 25 are analyzed, estimated now defeated
Entering the watt level of signal and power control signal being produced to connector 8, the signal is used to control outside R/T components logarithmic mode turn
The amplification of 19 output signal of parallel operation, reaches the purpose of height deception；
Described full forward mode is specific as follows：DLVA analog-digital converters 25 are by CMOS level conversion device and FPGA moulds
Block 17 communicates, the thresholding in the data and FPGA module 17 after the sampling of DLVA analog-digital converters 25 set by thresholding identifying unit 26
It is compared, postpones forwarding if the data after sampling are higher than thresholding and proceed by, the data after sampling is less than thresholding
Then system stops storage, and in input with output signal, system operatio is forwarding main lobe and secondary lobe；Using such method
Can successfully on radar formed flight path and reach distance and velocity gate deception；
Described survey week forward mode is specific as follows：Data after DLVA analog-digital converters 25 are sampled are higher than set
Thresholding, then postpone forwarding and start, according to the radar wave featured configuration main lobe width investigated, then the system forwards time fix；From
From the point of view of in input and output signal, system operatio is only to forward a main lobe；Can the successfully formation on radar using such method
Flight path simultaneously reaches height deception；
2) in investigative mode, the first analog-digital converter 16 sample after data via multiplexing selector 9 transmit to
Memorizer 21 is stored.
The real of present embodiment postpones forwarding effect as shown in figure 5, defeated in low-power if radar ripple input port when testing
Enter the pulse modulated 300Mhz signals of 48us, the envelope signal after outside radar wave packet network input port is input into detection tests number
As shown in FIG., in figure, signal above is the envelope signal of input to mould conversion delivery outlet signal, and lower section is output as postponing
The primary signal (as postpones signal is not over cymoscope, showing that result is the 300Mhz signals after modulation) of 15us.Input
Ripple is with present invention forwarding ripple contrast as shown in fig. 6, being forwarded by host computer real-time control waveform delay；In figure, upper square signal is this
The signal of invention forwarding, lower section are the waveshape signal of input.
Claims (7)
1. the input of a kind of stored digital and repeating jamming system, including digital-to-analogue conversion delivery outlet (1), low-power if radar ripple
Mouth (7), connector (8), the first analog-digital converter (16), FPGA module (17), digital frequency synthesizer (18), digital to analog converter
(19), clock chip (20), memorizer (21), single-chip microcomputer (22) and the second analog-digital converter (23), it is characterised in that also include
Doppler's frequency multiplication benchmark delivery outlet (2), the comprehensive input port (3) of frequency, reference frequency input port (4), outside radar wave envelope input port
(5), saturation power if radar ripple input port (6) and DLVA analog-digital converters (25)；
The saturation power if radar ripple input port (6) is connected with the first analog-digital converter (16), the low-power intermediate frequency thunder
It is connected up to ripple input port (7) with the second analog-digital converter (23), first analog-digital converter (16) and the second analog-digital converter
(23) it is connected with FPGA module (17) respectively；
Outside radar wave envelope input port (5) is connected with DLVA analog-digital converters (25), DLVA analog-digital converters (25)
Outfan is connected with FPGA module (17) by CMOS level conversion device；
The single-chip microcomputer (22) is connected with FPGA module (17), clock chip (20), the second analog-digital converter (23) respectively, described
Single-chip microcomputer (22) is connected with the connector (8) by RS422 interfaces；
The FPGA module (17) is connected with digital frequency synthesizer (18) by SPI interface, for controlling Digital Frequency Synthesize
Device (18) produces Doppler's frequency multiplication benchmark in real time；The general output interface of the FPGA module (17) is connected use with connector (8)
In output external power control signal；The digital to analog converter (19) and FPGA module (17) are by LVDS signal communications, described
Frequently comprehensive input port (3) is connected with clock chip (20), and the reference frequency input port (4) is with digital frequency synthesizer (18) even
Connect, the outfan of the digital frequency synthesizer (18) is connected with Doppler's frequency multiplication benchmark delivery outlet (2), the digital to analog converter
(19) outfan is connected with digital-to-analogue conversion delivery outlet (1)；
The clock chip (20) is respectively to the first analog-digital converter (16), digital to analog converter (19), the second analog-digital converter
(23) and DLVA analog-digital converters (25) provide timeticks；Whole system power supply is provided by connector (8) by motherboard；Storage
Device (21) is connected with FPGA module (17).
2. stored digital according to claim 1 and repeating jamming system, it is characterised in that the digital to analog converter
(19) outfan is connected to guarantee FPGA module (17) and digital to analog converter with FPGA module (17) by locking ring retard (DLL)
(19) data clock beat alignment.
3. stored digital according to claim 1 and repeating jamming system, it is characterised in that the FPGA module (17)
Including the first Date Conversion Unit (14), the second Date Conversion Unit (15) and the 3rd Date Conversion Unit, the first multiplexing
Device (9) and the second multiplexer (13), entrance cell fifo (10), thresholding identifying unit (26), primary storage cell fifo
(11) cell fifo (12), deception unit (27), SPI interface (28) and isolation cell fifo (29), the FPGA moulds, are exported
Block (17) works in investigative mode respectively and the detailed process of cheating mode is as follows：
A. investigative mode：The 3rd data conversion list that first multiplexer (9) clearance is connected with the first analog-digital converter (16)
The data of unit, and by the data storage after conversion to memorizer (21), while shielding and outside second analog-digital converter (23)
The data of connected the first Date Conversion Unit (14)；
B. cheating mode：The sampled data of outside the second analog-digital converter (23) is transferred to by the first Date Conversion Unit (14)
First multiplexer (9), the first data conversion that the first multiplexer (9) clearance is connected with the second analog-digital converter (23)
The data of unit (14), and shield the data of the 3rd Date Conversion Unit being connected with the first analog-digital converter (16)；
After described outside DLVA analog-digital converters (25) are sampled to radar wave envelope signal, by sampled data export to
Thresholding identifying unit (26) in FPGA module (17) is judging whether pulse arrives；If input data exceedes pre-determined threshold,
Think that pulse arrives, thresholding identifying unit (26) feeds a mouthful cell fifo (10) by DLVA signals are exported；
Entrance cell fifo (10) let pass after receiving DLVA signals the first multiplexer (9) signal it is mono- to primary storage FIFO
First (11), now primary storage cell fifo (11) change the state of its empty signal discharged to outlet cell fifo (12), table
Bright beginning data storage；
After outlet cell fifo (12) detects the empty signal conditions change that primary storage cell fifo (11) discharges, start which
Internal timer starts timing；When timer reaches the thresholding that deception unit (27) is configured to which, cell fifo is exported
(12) start to read the data of primary storage cell fifo (11) and transmit to the second Date Conversion Unit (15) to carry out parallel-serial conversion；
Deception unit (27) is received by outside single-chip microcomputer (22) to the control signal for exporting cell fifo (12) and is flown after control instruction
Produced by SPI interface (28) transmission；
After isolation cell fifo (29) receives the data of the second Date Conversion Unit (15), by the data according to the second multiplexing
The clock that device (13) is provided is let pass and gives the second multiplexer (13), the second multiplexer (13) by be input into data transfer extremely
Outside digital to analog converter (19) simultaneously exports curve via digital-to-analogue conversion delivery outlet (1), the curve by full forwarding or
Person surveys the function that all forward modes can reach range gate deception.
4. stored digital according to claim 3 and repeating jamming system, it is characterised in that the deception unit (27)
By the output frequency of SPI interface (28) real-time control external digital frequency synthesizer (18), reach be superimposed on carrier wave it is how general
The purpose of frequency is strangled, coupled system postpones forwarding and realizes velocity gate deception function.
5. stored digital according to claim 3 and repeating jamming system, it is characterised in that the FPGA module (17)
After also including that gain control unit (24), the gain control unit (24) receive the control signal of deception unit (27), analysis
Via the data that DLVA analog-digital converters (25) are input into, estimate the now watt level of input signal and produce power control signal
To the connector (8) being connected with FPGA module (17), for controlling the difference that outside T/R components logarithm weighted-voltage D/A converter (19) exports
The amplification of the pulse signal in journey area, reaches the purpose of height deception.
6. stored digital according to claim 5 and repeating jamming system, it is characterised in that the deception unit (27)
The control signal of gain control unit (24) is received after winged control instruction by SPI interface (28) biography by outside single-chip microcomputer (22)
Defeated generation.
7. stored digital according to claim 3 and repeating jamming system, it is characterised in that second analog digital conversion
Device (23) and the first Date Conversion Unit (14) also have test pattern before into normal mode of operation, specific as follows：Single-chip microcomputer
(22) configure the second analog-digital converter (23) and enter test pattern, now four passages of the second analog-digital converter (23) send spy
Fixed test pattern；The first Date Conversion Unit of the inside (14) of FPGA module (17) receives the second analog-digital converter (23) simultaneously
The sampled point of transmission, if the sampled point is different from above-mentioned test pattern, FPAG modules (17) by adjust its internal the
The parallel data shift control pin slip parallel data of the deserializer in one Date Conversion Unit (14), slides while detecting
Whether the data after dynamic are alignd with test pattern；Once detecting alignment, FPGA module (17) will fixed parallel data displacement control
Pin processed, enters normal mode of operation while producing notification signal triggering single-chip microcomputer and configuring the second analog-digital converter (23).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
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| CN108008362A (en) * | 2016-10-30 | 2018-05-08 | 中国船舶重工集团公司第七二三研究所 | A kind of if radar target echo and interference generation module |
| CN106680786B (en) * | 2017-03-20 | 2019-02-05 | 湖南鼎方量子科技有限公司 | A kind of radar jammer real time target information modulator approach |
| CN110927683B (en) * | 2019-10-17 | 2022-02-22 | 南京国立电子科技有限公司 | Interference signal generating device and method thereof |
| CN112946585B (en) * | 2019-12-11 | 2024-03-01 | 东莞天速通信技术有限公司 | Jammer and jammer method based on space power synthesis |
| CN115037408A (en) * | 2022-04-19 | 2022-09-09 | 上海航天电子通讯设备研究所 | Anti-unmanned aerial vehicle electronic reconnaissance and interference attack integrated system and method |
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| CN201497809U (en) * | 2009-09-03 | 2010-06-02 | 中国电子科技集团公司第十四研究所 | Combined interference discriminator |
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