CN104360326A - Digital storage and forwarding type interference system - Google Patents
Digital storage and forwarding type interference system Download PDFInfo
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- CN104360326A CN104360326A CN201410679828.4A CN201410679828A CN104360326A CN 104360326 A CN104360326 A CN 104360326A CN 201410679828 A CN201410679828 A CN 201410679828A CN 104360326 A CN104360326 A CN 104360326A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
- G01S7/38—Jamming means, e.g. producing false echoes
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Abstract
The invention provides a digital storage and forwarding type interference system, and belongs to the field of electronic communication. The system can investigate, deceive and interfere in a radiation source, and deception on distance, speed and height can be achieved. The system comprises seven external SMA interfaces, main lobe judgment is carried out through a radar wave envelope provided by the outside, a programmable gate array device can be automatically flush with medium-frequency radar wave sampled data bits input from the outside and process data, a digital frequency synthesizer and an external power amplifier are controlled, and investigation, deception and interference of the radiation source are achieved.
Description
Technical field
The invention belongs to electronic communication field, be specifically related to a kind of stored digital and repeating jamming system.
Background technology
Signal delay technology is widely used in the field of communications, as communication exchange equipment, radar deception equipment etc., usually utilizes this technology to carry out realize target.
In communication instrument, much equipment needs to use delay technology; Such as oscillograph, observe in the application scenario of sophisticated signal waveform a lot, often need the sub-fraction of a display waveform, and allow it occupy whole screen, when a certain selected waveform of the whole TV signal of observational study, during use standard, base is helpless by the method for triggered as normal, so generally all adopt the structure of dual time base, this just needs to introduce base when delay technology postpones second.The conventional method realizing signal delay on civilian uses lag line, postponed at delay above-the-line promotion by signal; The shortcoming of said method is that lag line is bulky, postpones uncontrollable, accurate not for delay such exact instrument.
In field of radar, as search surveillance radar, this radar in scope large as far as possible, can find and monitors target as early as possible, ensures that the other side's target had the sufficient time to carry out and meets enemy's preparation before closing on defence area.And delay technology can be used for cheating search surveillance radar.Use this technology, can cheat enemy radar on the one hand, reach strategic effect; Can cheat oneself radar on the other hand, be adapted at using when manoeuvre, training etc. can not use true aircraft to be used as target, reach manoeuvre teaching efficiency.
Between these situations above, domestic to delay technology, especially the demand of stored digital and retransmission technique is more and more higher, and store & forward technology has become the important means to distance by radar deception, track spoofing, highly deception.Part research and patent is had to the design of store-and-forward system is domestic, as Zhou Xuli (to the search range gate deception of surveillance radar and track spoofing research [D]. Northcentral University, 2008:27.) propose distance by radar and track spoofing scheme, namely range gate deception is by carrying out time delay modulation to the radar illumination signal received and amplify realizing; Tian Xiaowei (a kind of storer with real-time storage forwarding capability, Chinese utility model patent, 201220069420.1 [P] .2012-09-05.) propose a kind of storer with real-time storage forwarding capability, mainly comprise storer, data interface module, data memory module, status control module and real-time output module.Traditional store-and-forward system mentioned by above-mentioned document and radar deception effect are based upon on range gate deception and velocity gate deception basis, systemic-function is more single, deception function is fairly simple, owing to using external memory storage, system lowest latency is larger, the deception method of inspection is all emulated by modeling substantially, in actual applications, the input and output link of store-and-forward system often occurs that sequential is asynchronous, the problems such as data bit does not line up, cause and export the not repairable mistake of data, single pass emulation verifies that deception effect often disagrees with actual, thus cause the defect of system.
Summary of the invention
The invention provides a kind of stored digital and repeating jamming system, this system can integrate signal and investigate, cheats, disturbs, and realizes radar and is opening the deception carrying out distance, speed, height under anti-tampering pattern; The present invention realizes simply, and working stability, input tape is wide.
The present invention specifically adopts following technical scheme:
A kind of stored digital and repeating jamming system, its structure as shown in Figures 2 and 3, comprises digital-to-analog conversion delivery outlet 1, Doppler's frequency multiplication benchmark delivery outlet 2, frequently combines input port 3, reference frequency input port 4, outside radar wave envelope input port 5, saturation power if radar ripple input port 6, low-power if radar ripple input port 7, connector 8, first analog to digital converter 16, FPGA module 17, digital frequency synthesizer 18, digital to analog converter 19, clock chip 20, storer 21, single-chip microcomputer 22, second analog to digital converter 23 and DLVA analog to digital converter 25;
Described saturation power if radar ripple input port 6 is connected with the first analog to digital converter 16, described low-power if radar ripple input port 7 is connected with the second analog to digital converter 23, and described first analog to digital converter 16 is connected with FPGA module 17 respectively with the second analog to digital converter 23;
The output terminal that described outside radar wave envelope input port 5 is connected with DLVA analog to digital converter 25, DLVA analog to digital converter 25 is connected with FPGA module 17 by CMOS level conversion device;
Described single-chip microcomputer 22 is connected with FPGA module 17, clock chip 20, second analog to digital converter 23 respectively, and described single-chip microcomputer 22 is connected with described connector 8 by RS422 interface;
Described FPGA module 17 is connected with digital frequency synthesizer 18 by SPI interface, produces Doppler's frequency multiplication benchmark in real time for control figure frequency synthesizer 18; The general output interface of described FPGA module 17 is connected to export external power control signal with connector 8; Described digital to analog converter 19 is communicated by LVDS signal with FPGA module 17, can be connected to guarantee that FPGA module 17 is alignd with the data clock beat of digital to analog converter 19 with FPGA module 17 by lock ring retard (DLL) at digital to analog converter 19 output terminal further;
Described frequency is combined input port 3 and is connected with clock chip 20, described reference frequency input port 4 is connected with digital frequency synthesizer 18, the output terminal of described digital frequency synthesizer 18 is connected with Doppler's frequency multiplication benchmark delivery outlet 2, and the output terminal of described digital to analog converter 19 is connected with digital-to-analog conversion delivery outlet 1;
Described clock chip 20 provides timeticks respectively to the first analog to digital converter 16, digital to analog converter 19, second analog to digital converter 23 and DLVA analog to digital converter 25; Whole system power supply is provided by connector 8 by motherboard; Storer 21 is connected with FPGA module 17.
Described second digital to analog converter 23 is sampled to the radar wave inputing to low frequency if radar ripple input port 7, and the signal after sampling inputs to FPGA module 17 by Low Voltage Differential Signal pattern (LVDS) and forms radar deception ripple;
The radar wave of described first analog to digital converter, 16 pairs of saturation power if radar ripple input ports 6 is sampled, and the signal after sampling inputs to FPGA module 17 by LVDS and is stored in storer 21 as to the investigation information of radar wave, reaches investigation object; Further, stored information is imported in host computer via reserved network interface and analyzes, obtain radiation source feature;
The signal of described DLVA analog to digital converter 25 to outside radar wave packet network input port 5 is sampled, signal after sampling inputs to FPGA module 17 as judging radar wave main lobe foundation via CMOS level conversion device, can only store key waveforms thus, compression memory space, and need not as needing to increase external memory storage in prior art; The signal inputted with DLVA analog to digital converter 25 is for foundation, and FPGA module 17 adjusts different journey districts radar wave pulse height, realize target height deception object;
When whole system is started working, single-chip microcomputer 22 configures the second analog to digital converter 23 and enters test pattern, now four passages of the second analog to digital converter 23 send specific test pattern, the internal data converting unit 14 of FPGA module 17 receives the sampled point that the second analog to digital converter 23 transmits simultaneously, if described sampled point is different from above-mentioned test pattern, whether then FPAG module 17 slides up and down parallel data by regulating the row data shift control pin of the deserializer in the Date Conversion Unit 14 of its inside, detect the data after sliding simultaneously and align with test pattern; Once alignment be detected, FPGA module 17 is by fixed line number according to shift control pin, and generation notification signal triggering single-chip microcomputer configures the second analog to digital converter 23 and enters normal mode of operation simultaneously;
The structure of FPGA module 17 is as shown in Figure 4:
1) in cheating mode, after the Date Conversion Unit 14 of its inside receives the sampled data of the second analog to digital converter 23, institute's image data is passed to multiplexed selector switch 9 according to beat frequency, data are passed to entrance cell fifo 10 according to beat frequency by multiplexed selector switch 9, entrance cell fifo 10 is once receive the DLVA signal transmitted by thresholding identifying unit 26, the data that the multiplexed selector switch 9 that just starts to let pass transmits also pass to primary storage cell fifo 11 according to timeticks, change the empty state that primary storage cell fifo 11 outputs signal simultaneously; Outlet cell fifo 12 detects that opening its dynamic internal timer after the state of empty signal becomes 0 from 1 starts timing, once after timing reaches the delay parameter that the single-chip microcomputer 22 that is connected with FPGA module 17 configures, outlet cell fifo 12 starts to read the data in primary storage cell fifo 11 according to timeticks and data are passed to Date Conversion Unit 15 to carry out parallel-serial conversion, and final data is transferred to multiplexed selector switch 13 and exports to digital to analog converter 19 and export curve; On the basis realizing range gate deception, deception unit 27 controls the output frequency of external digital frequency synthesizer 18 in real time by SPI interface 28, reach the object superposing Doppler frequency on carrier wave, realize velocity gate deception function; After gain control unit 24 receives the control signal of deception unit 27, analyze the data inputted via DLVA analog to digital converter 25, estimate the watt level of now input signal and produce power control signal to the connector 8 be connected with FPGA module 17, this signal, for controlling the enlargement factor of the pulse signal in the different journey districts of outside T/R assembly logarithmic mode converter 19 output, reaches the object of highly deception;
2) in investigative mode, multiplexer 9 is let pass the data of the Date Conversion Unit be connected with the first analog to digital converter 16, and the data after conversion are stored in storer 21, shield the data of the Date Conversion Unit 14 be connected with the second analog to digital converter 23 simultaneously.
The invention has the beneficial effects as follows:
1) stored digital provided by the invention and repeating jamming system are by arranging multiple external interface, to solve in design in the past the clock problems such as coherent, investigation stored waveform signal to noise ratio (S/N ratio) be not low;
2) problem that in traditional design, data bit does not line up is solved, improve equipment output effect, and only key waveforms is stored, compression memory space, thus need not need to increase external memory storage as in design in the past, solving in traditional design utilizes external memory storage to increase the deficiency in minimum delay, makes delay more accurate; Meanwhile, the invention enables multiple-beam radar to cheat and can carry out height deception;
3) the present invention integrates investigation, cheats, disturbs, the pulse waveform of maximum storage 200us, and waveform delay precision is 0.41us; Ground control station can enter start, standby, investigation, deception, jamming pattern by opertaing device at any time, radar can be made to open the deception carrying out distance, speed, height under anti-tampering pattern, and flight path is stablized in formation.
Accompanying drawing explanation
Fig. 1 is general storage forwarding structured flowchart;
Fig. 2 is external interface schematic diagram of the present invention;
Fig. 3 is hardware configuration schematic diagram of the present invention;
Fig. 4 is FPGA internal module structural design in the present invention;
The storage delay of the stored digital that Fig. 5 provides for embodiment and retransmitted jamming system forwards effect;
The incoming wave of the stored digital that Fig. 6 provides for embodiment and retransmitted jamming system with forward ripple design sketch;
Wherein, 1: digital-to-analog conversion delivery outlet, 2: Doppler's frequency multiplication benchmark delivery outlet, 3: frequently combine input port, 4: reference frequency input port, 5: outside radar wave envelope input port, 6: saturation power if radar ripple input port, 7: low-power if radar ripple input port, 8: connector, 9: internal multiplexer, 10: entrance cell fifo, 11: primary storage cell fifo, 12 outlet cell fifos, 13: multiplexer, 14: Date Conversion Unit, 15: Date Conversion Unit, 16: the first analog to digital converters, 17:FPGA module, 18: digital frequency synthesizer, 19: digital to analog converter, 20: clock chip, 21: storer, 22: single-chip microcomputer, 23: the second analog to digital converters, the gain control unit of 24:FPGA inside, 25:DLVA analog to digital converter, the thresholding identifying unit of 26:FPGA inside, the deception control module of 27:FPGA inside, the SPI communication interface of 28:FPGA inside, 29, 30: isolation cell fifo.
Embodiment
Below in conjunction with the drawings and specific embodiments, the utility model is described in detail.
The stored digital that present embodiment provides and repeating jamming system primary structure are as shown in Figures 2 and 3, exported the intermediate-freuqncy signal of low-power and saturation power two-way 100M ~ 500M by down coversion after high-frequency signal receives via T/R assembly, detect the envelope of high-frequency signal simultaneously, produce envelope signal; Low-power signal is input in the second analog to digital converter 23 via low-power if radar ripple input port 7, then inputs to FPGA module 17 for storing and process generation curve; Saturation power signal inputs in the first analog to digital converter 16 via saturation power if radar ripple input port 6 and stores; Whether the envelope signal produced inputs to paired pulses in DLVA analog to digital converter 25 via outside radar wave envelope input port 5 and arrives and differentiate;
Digital-to-analog conversion delivery outlet 1, as the output terminal of digital to analog converter 19, is the if radar ripple delivery outlet after process, and its frequency exporting intermediate-freuqncy signal is 100Mhz ~ 500Mhz, and power is-15dbm ~ 0dbm, main assorted than being greater than 25dbc; 100Mhz Doppler frequency multiplication benchmark delivery outlet 2 is as the output terminal of digital frequency synthesizer 18, and its output area is 99.9Mhz ~ 100.1Mhz, and power is 0dbm; Outside 1.25G combines the input end of input port 3 as clock chip 20 frequently, for intrasystem first analog to digital converter 16, digital to analog converter 19, second analog to digital converter 23 and DLVA analog to digital converter 25 provide beat frequency; Outside 100Mhz reference frequency input port 4 is as the reference frequency input end of digital frequency synthesizer 18, and power input is-2dbm; Outside radar wave envelope input port 5 as the input end of DLVA analog to digital converter 25, for judging that radar wave main lobe provides foundation; Saturation power if radar ripple input port 6 is as the input end of the first analog to digital converter 16, incoming frequency is 100Mhz ~ 500Mhz, power is the signal of 0dbm, first analog to digital converter 16 is sampled to this signal, and is stored to the radar wave storage as investigation in storer 21 via FPGA module 17; Low-power if radar ripple input port 7 is as the input end of the second analog to digital converter 23, the signal that incoming frequency is 100Mhz ~ 500Mhz, power is-40dbm ~ 0dbm, second analog to digital converter 23 pairs input signal is sampled, and is undertaken processing and producing curve by FPGA module 17.
During system starts, single-chip microcomputer 22 configures the second analog to digital converter 23 and enters test pattern, in test pattern, four passages (QD, ID, Q, I of second analog to digital converter 23, each road is 12bit) fixing test pattern can be exported, the concrete form of test pattern exported at a timeticks is: T
0moment QD passage is FF7h, ID passage be FEFh, Q passage be 008h, I passage is 010h; T
1moment repeats T
0moment pattern; T
2moment QD passage pattern and Q passage pattern exchange, and ID passage and I passage pattern exchange, until T
5each passage of moment repeats T
0moment pattern, repeats with cocycle;
Second analog to digital converter 23 is connected with the Date Conversion Unit 14 of FPGA module 17 inside, Date Conversion Unit 14 mainly contains two effects: 1) regard each bit position of each passage as serial data, carry out serioparallel exchange and reduce inter-process speed with this; 2) judge input data whether be test pattern, if be not test pattern, so front and back displacement is carried out to serioparallel exchange part parallel data, continue to determine whether test pattern, judged by displacement, until be finally test pattern, stop displacement, now configuring the second analog to digital converter 23 is mode of operation, and down coversion waveform is input to the second analog to digital converter 23 from low-power if radar ripple input port 7 and samples.
For investigating and produce the inner structure of the FPGA module 17 of curve as shown in Figure 4 in present embodiment:
1) in cheating mode, Date Conversion Unit 14 transfers data to multiplexer 9, multiplexer 9 is let pass the data of the Date Conversion Unit 14 be connected with the second analog to digital converter 23, and shields the data of the Date Conversion Unit be connected with the first analog to digital converter 16;
After DLVA analog to digital converter 25 pairs of radar wave envelope signals are sampled, sampled data is exported to thresholding identifying unit 26 in FPGA module 17 to judge whether pulse arrives; If input data exceed pre-determined threshold, then think that pulse arrives, now thresholding identifying unit 26 will export DLVA signal to entrance cell fifo 10;
Entrance cell fifo 10, when not receiving the DLVA signal from thresholding identifying unit 26, can shield all signals of input; When entrance cell fifo 10 receives DLVA signal, the signal of its multiplexer 9 of letting pass is to primary storage cell fifo 11, and primary storage cell fifo 11 changes the state of the empty signal discharged to outlet cell fifo 12 simultaneously, shows to start to store data;
After outlet cell fifo 12 detects the empty signal condition change that primary storage cell fifo 11 discharges, the timer starting its inside starts timing; When timer reaches the thresholding that deception unit 27 configures it, start to read the data of primary storage cell fifo 11 and transfer to Date Conversion Unit 15 and carry out parallel-serial conversion; After outlet cell fifo 12 detects that empty signal condition is recovered, stop the data reading primary storage cell fifo 11; The control signal of deception unit 27 pairs of gain control units 24 and outlet cell fifo 12, by the single-chip microcomputer 22 of FPGA module 17 outside receive fly control instruction after transmit generation by SPI interface 28;
After isolation cell fifo 29 receives the data of Date Conversion Unit 15, these data are let pass to multiplexer 13 according to the clock that multiplexer 13 provides, the data of input are transferred to external number weighted-voltage D/A converter 19 and export curve via digital-to-analog conversion delivery outlet 1 by multiplexer 13, and this curve is by entirely forwarding or surveying the function that all forward modes can reach range gate deception; On the basis realizing range gate deception, deception unit 27 controls the output frequency of external digital frequency synthesizer 18 in real time by SPI interface 28, reach the object superposing Doppler frequency on carrier wave, realize velocity gate deception function; After gain control unit 24 receives the control signal of deception unit 27, analyze the data inputted via DLVA analog to digital converter 25, estimate the watt level of now input signal and produce power control signal to connector 8, this signal, for controlling the enlargement factor of outside R/T assembly logarithmic mode converter 19 output signal, reaches the object of highly deception;
Described full forward mode is specific as follows: DLVA analog to digital converter 25 is communicated with FPGA module 17 by CMOS level conversion device, DLVA analog to digital converter 25 sample after data and FPGA module 17 in thresholding set by thresholding identifying unit 26 compare, once the data after sampling are higher than thresholding, postpone forwarding and start to carry out, once the data after sampling are lower than thresholding, system stops storing, from constrained input signal, Dynamic System is for forwarding main lobe and secondary lobe; Utilize such method successfully can form flight path on radar and reach distance and velocity gate deception;
Described survey week forward mode is specific as follows: the data after DLVA analog to digital converter 23 is sampled are higher than set thresholding, then postpone to forward to start, according to investigating the radar wave featured configuration main lobe width arrived, then the system forwards time is fixed; From constrained input signal, Dynamic System is for only to forward main lobe; Utilize such method successfully can form flight path on radar and reach and highly cheat;
2) in investigative mode, the data after the first analog to digital converter 16 sampling transfer to storer 21 via multiplexed selector switch 9 and store.
The reality of present embodiment postpones to forward effect as shown in Figure 5, at the pulse modulated 300Mhz signal of low-power if radar ripple input port input 48us during test, envelope signal after the input detection of outside radar wave packet network input port, test digital-to-analog conversion delivery outlet signal as shown in FIG., the signal being positioned at top in figure is the envelope signal of input, below exports the original signal (because inhibit signal is not by wave detector, display result is the 300Mhz signal after modulation) for postponing 15us.Incoming wave and the present invention forward ripple and contrast as shown in Figure 6, postpone to forward by the real-time control waveform of host computer; In figure, upper square signal is the signal that the present invention forwards, and below is the waveform signal of input.
Claims (7)
1. a stored digital and repeating jamming system, comprise digital-to-analog conversion delivery outlet (1), low-power if radar ripple input port (7), connector (8), first analog to digital converter (16), FPGA module (17), digital frequency synthesizer (18), digital to analog converter (19), clock chip (20), storer (21), single-chip microcomputer (22) and the second analog to digital converter (23), it is characterized in that, also comprise Doppler's frequency multiplication benchmark delivery outlet (2), frequently input port (3) is combined, reference frequency input port (4), outside radar wave envelope input port (5), saturation power if radar ripple input port (6) and DLVA analog to digital converter (25),
Described saturation power if radar ripple input port (6) is connected with the first analog to digital converter (16), described low-power if radar ripple input port (7) is connected with the second analog to digital converter (23), and described first analog to digital converter (16) is connected with PFGA module (17) respectively with the second analog to digital converter (23);
Described outside radar wave envelope input port (5) is connected with DLVA analog to digital converter (25), and the output terminal of DLVA analog to digital converter (25) is connected with FPGA module (17) by CMOS level conversion device;
Described single-chip microcomputer (22) is connected with FPGA module (17), clock chip (20), the second analog to digital converter (23) respectively, and described single-chip microcomputer (22) is connected with described connector (8) by RS422 interface;
Described FPGA module (17) is connected with digital frequency synthesizer (18) by SPI interface, produces Doppler's frequency multiplication benchmark in real time for control figure frequency synthesizer (18); The general output interface of described FPGA module (17) is connected for exporting external power control signal with connector (8); Described digital to analog converter (19) is communicated by LVDS signal with FPGA module (17), described frequency is combined input port (3) and is connected with clock chip (20), described reference frequency input port (4) is connected with digital frequency synthesizer (18), the output terminal of described digital frequency synthesizer (18) is connected with Doppler's frequency multiplication benchmark delivery outlet (2), and the output terminal of described digital to analog converter (19) is connected with digital-to-analog conversion delivery outlet (1);
Described clock chip (20) provides timeticks respectively to the first analog to digital converter (16), digital to analog converter (19), the second analog to digital converter (23) and DLVA analog to digital converter (25); Whole system power supply is provided by connector (8) by motherboard; Storer (21) is connected with FPGA module (17).
2. stored digital according to claim 1 and repeating jamming system, it is characterized in that, described digital to analog converter 19 output terminal is connected with FPGA module 17 to guarantee that FPGA module 17 is alignd with the data clock beat of digital to analog converter 19 by lock ring retard (DLL).
3. stored digital according to claim 1 and repeating jamming system, it is characterized in that, described FPGA module (17) comprises Date Conversion Unit (14,15), multiplexed selector switch (9,13), entrance cell fifo (10), thresholding identifying unit (26), primary storage cell fifo (11), outlet cell fifo (12), deception unit (27), SPI interface (28) and isolation cell fifo (29), and the detailed process that described FPGA module (17) works in investigative mode and cheating mode is respectively as follows:
A. investigative mode: multiplexer (9) is let pass the data of the Date Conversion Unit be connected with the first analog to digital converter (16), and the data after conversion are stored in storer (21), shield the data of the Date Conversion Unit (14) be connected with outside second analog to digital converter (23) simultaneously;
B. cheating mode: the sampled data of second analog to digital converter (23) of outside is transferred to multiplexer (9) by Date Conversion Unit (14), multiplexer (9) is let pass the data of the Date Conversion Unit (14) be connected with the second analog to digital converter (23), and shields the data of the Date Conversion Unit be connected with the first analog to digital converter (16);
After described outside DLVA analog to digital converter (25) is sampled to radar wave envelope signal, sampled data is exported to thresholding identifying unit (26) in FPGA module (17) to judge whether pulse arrives; If input data exceed pre-determined threshold, then think that pulse arrives, thresholding identifying unit (26) will export DLVA signal to entrance cell fifo (10);
Let pass the signal of multiplexer (9) to primary storage cell fifo (11) after entrance cell fifo (10) receives DLVA signal, now primary storage cell fifo (11) changes the state of the empty signal that it discharges to outlet cell fifo (12), shows to start to store data;
After outlet cell fifo (12) detects the empty signal condition change that primary storage cell fifo (11) discharges, the timer starting its inside starts timing; When timer reaches the thresholding that deception unit (27) configure it, export cell fifo (12) and start to read the data of primary storage cell fifo (11) and transfer to Date Conversion Unit (15) and carry out parallel-serial conversion; Described deception unit (27) to outlet cell fifo (12) control signal by the single-chip microcomputer (22) of outside receive fly control instruction after by SPI interface (28) transmit produce;
After isolation cell fifo (29) receives the data of Date Conversion Unit (15), these data are let pass to multiplexer (13) according to the clock that multiplexer (13) provides, the data of input are transferred to external number weighted-voltage D/A converter (19) and export curve via digital-to-analog conversion delivery outlet (1) by multiplexer (13), and this curve is by entirely forwarding or surveying the function that all forward modes can reach range gate deception.
4. stored digital according to claim 3 and repeating jamming system, it is characterized in that, described deception unit (27) controls the output frequency of external digital frequency synthesizer (18) in real time by SPI interface (28), reach the object superposing Doppler frequency on carrier wave, coupled system postpones forwarding and realizes velocity gate deception function.
5. stored digital according to claim 3 and repeating jamming system, it is characterized in that, described FPGA module (17) also comprises gain control unit (24), after described gain control unit (24) receives the control signal of deception unit (27), analyze the data inputted via DLVA analog to digital converter (25), estimate the watt level of now input signal and produce power control signal to the connector (8) be connected with FPGA module (17), for controlling the enlargement factor of the pulse signal in the different journey districts that outside T/R assembly logarithmic mode converter (19) exports, reach the object of highly deception.
6. stored digital according to claim 5 and repeating jamming system, it is characterized in that, described deception unit (27) to the control signal of gain control unit (24) by the single-chip microcomputer (22) of outside receive fly control instruction after by SPI interface (28) transmit produce.
7. stored digital according to claim 3 and repeating jamming system, it is characterized in that, described second analog to digital converter (23) and Date Conversion Unit (14) also have test pattern before entering normal mode of operation, specific as follows: single-chip microcomputer (22) configures the second analog to digital converter (23) and enters test pattern, now four passages of the second analog to digital converter (23) send specific test pattern; The internal data converting unit (14) of FPGA module (17) receives the sampled point that the second analog to digital converter (23) transmits simultaneously, if described sampled point is different from above-mentioned test pattern, whether then FPAG module (17) is by regulating the parallel data shift control pin slip parallel data of the deserializer in the Date Conversion Unit (14) of its inside, detect the data after sliding simultaneously and align with test pattern; Once alignment be detected, FPGA module (17) will fix parallel data shift control pin, and generation notification signal triggering single-chip microcomputer configures the second analog to digital converter (23) and enters normal mode of operation simultaneously.
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| CN106680786A (en) * | 2017-03-20 | 2017-05-17 | 湖南鼎方电子科技有限公司 | Real time target information modulation method for radar jammer |
| CN108008362A (en) * | 2016-10-30 | 2018-05-08 | 中国船舶重工集团公司第七二三研究所 | A kind of if radar target echo and interference generation module |
| CN110927683A (en) * | 2019-10-17 | 2020-03-27 | 南京国立电子科技有限公司 | Interference signal generating device and method thereof |
| CN112946585A (en) * | 2019-12-11 | 2021-06-11 | 东莞天速通信技术有限公司 | Jammer based on space power synthesis and jamming method |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105676198A (en) * | 2016-03-31 | 2016-06-15 | 电子科技大学 | Echo pulse delay generating device for pulse type radar test |
| CN108008362A (en) * | 2016-10-30 | 2018-05-08 | 中国船舶重工集团公司第七二三研究所 | A kind of if radar target echo and interference generation module |
| CN106680786A (en) * | 2017-03-20 | 2017-05-17 | 湖南鼎方电子科技有限公司 | Real time target information modulation method for radar jammer |
| CN106680786B (en) * | 2017-03-20 | 2019-02-05 | 湖南鼎方量子科技有限公司 | A kind of radar jammer real time target information modulator approach |
| CN110927683A (en) * | 2019-10-17 | 2020-03-27 | 南京国立电子科技有限公司 | Interference signal generating device and method thereof |
| CN112946585A (en) * | 2019-12-11 | 2021-06-11 | 东莞天速通信技术有限公司 | Jammer based on space power synthesis and jamming method |
| CN112946585B (en) * | 2019-12-11 | 2024-03-01 | 东莞天速通信技术有限公司 | Jammer and jammer method based on space power synthesis |
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