CN110927683B - Interference signal generating device and method thereof - Google Patents
Interference signal generating device and method thereof Download PDFInfo
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- CN110927683B CN110927683B CN201910986239.3A CN201910986239A CN110927683B CN 110927683 B CN110927683 B CN 110927683B CN 201910986239 A CN201910986239 A CN 201910986239A CN 110927683 B CN110927683 B CN 110927683B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
- G01S7/38—Jamming means, e.g. producing false echoes
Abstract
An interference signal generating apparatus and method thereof, including a signal generating device for generating and finally outputting a processed signal; the interference signal generating device further comprises a processing device, and the processing device is connected with the signal generating equipment; the processing means controls the signal generating device to increase the generation speed of the interference signal. The signal generation device comprises a first FPGA, an ADC, a memory and a first DAC; and the signal output end of the ADC, the input end of the first DAC and the memory are connected with the first FPGA. The combination with other structures or methods effectively avoids the defects in the prior art that the speed of generating the interference signals is not fast enough, the output order of the interference signals cannot be arranged according to the priority when multiple interference signals exist, and the interference signals which are preferentially processed cannot be processed earlier.
Description
Technical Field
The present invention relates to the technical field of interference signals and also relates to the technical field of signal generation, and in particular, to an interference signal generation apparatus and method.
Background
An interference signal (interference signal) is a signal that impairs reception of a desired signal.
With the rapid development of communication technology, the application field of communication products is wider and wider, the requirements on the communication products are also improved, and the anti-interference performance of the communication products is taken as an effective means for checking the functions and performance of the products, and becomes a main standard for measuring the practical value of the communication products. In the communication field, a radar receiving device needs to have practical value against various intentional and unintentional interferences, and a function test of a radar management and control product, an electromagnetic characteristic test of various radar-related electronic products, and the like all need an interference signal generating device to simulate electromagnetic information under a specific environment, so that the quality of the interference signal generating device also seriously affects the quality of communication products such as radars.
In the electronic communication technology, the interference signal generating device is one of the basic components, and the generation of the waveform and the control of the frequency are the most basic requirements, and are also the basis of the communication technology, so that it is important to design the generation and the control of the waveform. The conventional interference signal generating device generally utilizes a 555 circuit or a singlechip to generate a waveform of an interference signal to form the interference signal in a certain frequency range, the method is not fast enough to generate the interference signal, and the output order of the interference signal cannot be arranged according to the priority when multiple paths of interference signals exist, so that the interference signal which is preferentially processed cannot be processed earlier.
Disclosure of Invention
In order to solve the above problems, the present invention provides an interference signal generating apparatus and method thereof, which effectively avoid the defects in the prior art that the speed of generating interference signals is not fast enough, the output order of interference signals cannot be arranged according to priority when there are multiple paths of interference signals, and the interference signals which should be processed preferentially cannot be processed earlier.
In order to overcome the defects in the prior art, the invention provides a solution for an interference signal generating device and a method thereof, which comprises the following steps:
an interference signal generating apparatus includes a signal generating device for generating and finally outputting a processed signal;
the interference signal generating device further comprises a processing device, and the processing device is connected with the signal generating equipment;
the processing means controls the signal generating device to increase the generation speed of the interference signal.
The signal generation device comprises a first FPGA, an ADC, a memory and a first DAC;
the signal output end of the ADC, the input end of the first DAC and the memory are connected with the first FPGA;
the signal input end of the ADC is used for receiving an initial signal;
and the output end of the first DAC is used for outputting the processed signal.
The initial signal is an intermediate frequency baseband signal of a sampled radar; the processed signal is an intermediate frequency baseband signal of the processed radar.
The first FPGA comprises a serial-to-parallel converter, and the serial-to-parallel converter is connected with a signal output end of the ADC;
the memory is a double-port RAM, and two I/O control ports of the double-port RAM are connected with the first FPGA;
the first FPGA further comprises a parallel-to-serial converter, and the parallel-to-serial converter is connected with the input end of the first DAC.
The processing device comprises a second FPGA, a second DAC and a DSP processor;
the second DAC and the DSP processor are both connected with the second FPGA;
the DSP processor can assist in processing tasks of the second FPGA that control generation of interference signals;
the second DAC is used for generating an interference signal of a noise baseband;
the second FPGA is also connected with the first FPGA;
the interference signal generating device further comprises an external clock, and the external clock is connected with the clock input end of the ADC, the second FPGA and the DSP processor.
The first FPGA is also used for receiving an external wave gate signal;
the first FPGA is connected with an external control unit through a first I/O interface;
the second FPGA is connected with an external control unit through a second I/O interface;
the first FPGA is connected with the second FPGA through a third I/O interface;
the second FPGA is connected with the FLASH memory;
and the DSP processor is connected with an external terminal through an Ethernet interface.
The method of the interference signal generation device comprises the following steps:
the processing means controls the signal generating device to increase the generation speed of the interference signal.
The method for controlling the signal generating equipment to increase the generating speed of the interference signal by the processing device comprises the following steps:
step 1: the second FPGA controls the first FPGA to enable the ADC to sample an intermediate-frequency baseband signal of the radar serving as an initial signal;
step 2: the ADC converts the intermediate frequency baseband signal of each sampled radar into discrete quantized values represented by binary data;
and step 3: the serial data formed by the discrete quantized values is decelerated into parallel data matched with the writing time of the memory through a serial-parallel converter, and the parallel data are written into the storage address of the memory by the second FPGA according to the sequence set and arranged by the second FPGA or the first FPGA to be used as storage data, so that the storage control of the second FPGA is realized;
the second FPGA generates a storage address and a control signal required for storing low-speed parallel data according to an external command during storage control, and transmits the storage address and the control signal to the first FPGA to write the parallel data into a memory;
and 4, step 4: when the reproduction is needed, reading out the storage data from the storage address of the memory, converting the storage data into a high-speed digital signal, and recovering to obtain a processed signal;
and 5: in addition, during the period of obtaining the processed signal, the second FPGA synchronously generates an interference signal of the noise baseband through the second DAC, the interference signal of the synchronously generated noise baseband and the processed signal are mixed to form an interference signal, and the interference signal is emitted out according to the area set by the gate signal received by the first FPGA for interference.
The interference signal generating device also comprises a priority judging module which runs on the second FPGA, and when the storage data which needs to be read out have conflict, the storage data with high priority can be determined to be read preferentially according to the preset priority.
The specific processes of the steps 1 to 3 are as follows: the signal generating device records the frequency, the phase and the amplitude of an intermediate frequency baseband signal of the radar in advance, the intermediate frequency baseband signal of the radar is quantized into serial data through an ADC (analog-to-digital converter), the serial data is subjected to speed reduction processing through a serial-to-parallel conversion circuit to obtain parallel data, the parallel data is sent to a dual-port RAM to be stored, then the second FPGA controls the first FPGA to generate a corresponding read signal and a read address after corresponding delay, so that the first FPGA reads out the stored data stored in the read address in the dual-port RAM according to the read signal, the stored data read out after delay is converted into a high-speed digital signal through a parallel-to-serial conversion circuit, and the high-speed digital signal is sent to the first DAC according to the frequency, the phase and the amplitude of the intermediate frequency baseband signal of the radar recorded in advance to be recovered into a processed signal.
The invention has the beneficial effects that:
according to the invention, the signal generation device is controlled by the processing device to increase the generation speed of the interference signal, so that the generation speed of the interference signal is increased, and the problem that the speed of generating the interference signal is not high enough in the prior art is effectively avoided. The second FPGA can control the first FPGA to determine which interfering signal pulse is output first according to predetermined criteria and priorities. Thus, when there are multiple interference signals, the output order of the interference signals can be arranged according to the priority, so that the interference signals which are preferentially processed can be processed earlier. The second FPGA and the first FPGA are both ultra-large-scale FPGAs, so that the processing speed can be improved. In addition, part of tasks for priority judgment can be issued to the DSP processor for execution, and the speed and the efficiency for priority judgment are improved. The method effectively avoids the defects that the speed of generating the interference signals is not fast enough, the output order of the interference signals cannot be arranged according to the priority when multiple paths of interference signals exist, and the interference signals which are preferentially processed cannot be processed earlier in the prior art.
Drawings
Fig. 1 is a block diagram of an interference signal generating apparatus according to the present invention.
Fig. 2 is a flowchart of a method of the interference signal generating apparatus of the present invention.
Detailed Description
The invention will be further described with reference to the following figures and examples.
Example 1:
as shown in fig. 1, the interference signal generating apparatus includes a signal generating device for generating and finally outputting a processed signal; the interference signal generating device also comprises a processing device which is connected with the signal generating equipment; the processing means controls the signal generating device to increase the speed of generation of the interference signal. Therefore, the signal generating device is controlled by the processing device to increase the generating speed of the interference signal, the generating speed of the interference signal is increased, and the problem that the speed of generating the interference signal is not high enough in the prior art is effectively solved. The signal generation device comprises a first FPGA, an ADC, a memory and a first DAC; the signal output end of the ADC, the input end of the first DAC and the memory are connected with the first FPGA; the signal input end of the ADC is used for receiving an initial signal; the output end of the first DAC is used for outputting the processed signal. In this way, the first FPGA, the ADC, the memory and the first DAC can perform the function of generating the interference signal. The initial signal is an intermediate frequency baseband signal of a sampled radar; the processed signal is an intermediate frequency baseband signal of the processed radar. The anti-interference performance of the radar receiver can be detected by the generated processed signal. The first FPGA comprises a serial-parallel converter, and the serial-parallel converter is connected with the signal output end of the ADC; thus, the high-speed serial data can be converted into low-speed parallel data matched with the writing time of the memory through the serial-parallel converter and written into the memory according to the sequence arranged by the first FPGA.
The memory is a double-port RAM serving as a large-capacity memory, and two I/O control ports of the double-port RAM are connected with the first FPGA; thus, the first FPGA can control the two I/O control ports of the dual-port RAM to read from and write to the dual-port RAM as a mass storage.
The first FPGA further comprises a parallel-serial converter, and the parallel-serial converter is connected with the input end of the first DAC; thus, the data read from the memory can be converted into a high-speed digital signal by the parallel-to-serial converter. The processing device comprises a second FPGA, a second DAC and a DSP processor; the first DAC and the second DAC are high-speed DACs and are mainly used for generating interference signals of a noise baseband with the center frequency of 450MHz +/-300 MHz. The second DAC and the DSP processor are both connected with the second FPGA; the DSP processor can assist in processing the task of controlling the second FPGA to generate the interference signal; this allows the second FPGA to process tasks that control the generation of interference signals at an increased rate. The second DAC is used as a DDS device with a frequency modulation and phase modulation function to generate an interference signal of a noise baseband; the generated interference signal of the noise baseband and the processed signal are mixed together and synchronously transmitted to form the interference signal. The second FPGA is also connected with the first FPGA; in this way, the second FPGA can control the first FPGA to determine which interfering signal pulse is output first according to predetermined criteria and priorities. Thus, when there are multiple interference signals, the output order of the interference signals can be arranged according to the priority, so that the interference signals which are preferentially processed can be processed earlier. The second FPGA and the first FPGA are both ultra-large-scale FPGAs, so that the processing speed can be improved. The interference signal generating device further comprises an external clock, and the external clock is connected with the clock input end of the ADC, the second FPGA and the DSP processor. This provides a clock signal to the clock input of the ADC, the second FPGA and the DSP processor. The external clock is capable of generating a clock signal having a clock frequency of 2 GHZ. The external clock can be a crystal oscillator. The first FPGA is also used for receiving an external wave gate signal; the wave gate signal can set the region where the interference signal acts, and the generation of the corresponding interference signal by combining the wave gate signal is more targeted; the first FPGA is connected with an external control unit through a first I/O interface; the first I/O interface can be a dual-channel 8-bit LVDS interface, and the structure can quickly and efficiently obtain control commands and data from an external control unit, so that the flexible reception of the external control commands and data is facilitated; the second FPGA is connected with the external control unit through a second I/O interface; the second I/O interface can be a dual-channel 10-bit LVDS interface or a dual-channel 48-bit LVDS interface, and the structure can quickly and efficiently obtain control commands and data from an external control unit, so that the flexible receiving of external control commands and data is facilitated; the external control unit can be a controller such as a single chip microcomputer. The first FPGA is connected with the second FPGA through a third I/O interface; the third I/O interface can be a dual-channel 20-bit LVDS interface or a dual-channel 10-bit LVDS interface, and the structure can quickly and efficiently achieve the purpose that the second FPGA controls the first FPGA; the second FPGA is connected with the FLASH memory; this allows the FLASH memory to store information that controls the generation of the interference signal. The DSP processor is connected with an external terminal through an Ethernet interface. This enables communication with an external network. The external terminal can be a PC or a notebook computer.
Example 2:
as shown in fig. 1-2, the interference signal generating apparatus includes a signal generating device, which is configured to generate and finally output a processed signal; the interference signal generating device also comprises a processing device which is connected with the signal generating equipment; the processing means controls the signal generating device to increase the speed of generation of the interference signal. Therefore, the signal generating device is controlled by the processing device to increase the generating speed of the interference signal, the generating speed of the interference signal is increased, and the problem that the speed of generating the interference signal is not high enough in the prior art is effectively solved. The signal generation device comprises a first FPGA, an ADC, a memory and a first DAC; the signal output end of the ADC, the input end of the first DAC and the memory are connected with the first FPGA; the signal input end of the ADC is used for receiving an initial signal; the output end of the first DAC is used for outputting the processed signal. In this way, the first FPGA, the ADC, the memory and the first DAC can perform the function of generating the interference signal. The initial signal is an intermediate frequency baseband signal of a sampled radar; the processed signal is an intermediate frequency baseband signal of the processed radar. The anti-interference performance of the radar receiver can be detected by the generated processed signal. The first FPGA comprises a serial-parallel converter, and the serial-parallel converter is connected with the signal output end of the ADC; thus, the high-speed serial data can be converted into low-speed parallel data matched with the writing time of the memory through the serial-parallel converter and written into the memory according to the sequence arranged by the first FPGA.
The memory is a double-port RAM serving as a large-capacity memory, and two I/O control ports of the double-port RAM are connected with the first FPGA; thus, the first FPGA can control the two I/O control ports of the dual-port RAM to read from and write to the dual-port RAM as a mass storage.
The first FPGA further comprises a parallel-serial converter, and the parallel-serial converter is connected with the input end of the first DAC; thus, the data read from the memory can be converted into a high-speed digital signal by the parallel-to-serial converter. The processing device comprises a second FPGA, a second DAC and a DSP processor; the first DAC and the second DAC are high-speed DACs and are mainly used for generating interference signals of a noise baseband with the center frequency of 450MHz +/-300 MHz. The second DAC and the DSP processor are both connected with the second FPGA; the DSP processor can assist in processing the task of controlling the second FPGA to generate the interference signal; this allows the second FPGA to process tasks that control the generation of interference signals at an increased rate. The second DAC is used as a DDS device with a frequency modulation and phase modulation function to generate an interference signal of a noise baseband; the generated interference signal of the noise baseband and the processed signal are mixed together and synchronously transmitted to form the interference signal. The second FPGA is also connected with the first FPGA; in this way, the second FPGA can control the first FPGA to determine which interfering signal pulse is output first according to predetermined criteria and priorities. Thus, when there are multiple interference signals, the output order of the interference signals can be arranged according to the priority, so that the interference signals which are preferentially processed can be processed earlier. The second FPGA and the first FPGA are both ultra-large-scale FPGAs, so that the processing speed can be improved. The interference signal generating device further comprises an external clock, and the external clock is connected with the clock input end of the ADC, the second FPGA and the DSP processor. This provides a clock signal to the clock input of the ADC, the second FPGA and the DSP processor. The external clock is capable of generating a clock signal having a clock frequency of 2 GHZ. The external clock can be a crystal oscillator. The first FPGA is also used for receiving an external wave gate signal; the wave gate signal can set the region where the interference signal acts, and the generation of the corresponding interference signal by combining the wave gate signal is more targeted; the first FPGA is connected with an external control unit through a first I/O interface; the first I/O interface can be a dual-channel 8-bit LVDS interface, and the structure can quickly and efficiently obtain control commands and data from an external control unit, so that the flexible reception of the external control commands and data is facilitated; the second FPGA is connected with the external control unit through a second I/O interface; the second I/O interface can be a dual-channel 10-bit LVDS interface or a dual-channel 48-bit LVDS interface, and the structure can quickly and efficiently obtain control commands and data from an external control unit, so that the flexible receiving of external control commands and data is facilitated; the external control unit can be a controller such as a single chip microcomputer. The first FPGA is connected with the second FPGA through a third I/O interface; the third I/O interface can be a dual-channel 20-bit LVDS interface or a dual-channel 10-bit LVDS interface, and the structure can quickly and efficiently achieve the purpose that the second FPGA controls the first FPGA; the second FPGA is connected with the FLASH memory; this allows the FLASH memory to store information that controls the generation of the interference signal. The DSP processor is connected with an external terminal through an Ethernet interface. This enables communication with an external network. The external terminal can be a PC or a notebook computer.
A method of an interfering signal generating device, comprising:
the processing means controls the signal generating device to increase the speed of generation of the interference signal.
A method of a processing apparatus for controlling a signal generating device to increase the speed of generation of an interfering signal, the steps of:
step 1: in order to store and reproduce the intermediate frequency baseband signal of the radar, the interference signal generating device further forms an interference signal, the second FPGA controls the first FPGA to enable the ADC to sample the intermediate frequency baseband signal of the radar serving as an initial signal at a higher sampling rate according to a sampling theorem and under the control of a clock signal of an external clock;
step 2: the ADC converts the intermediate frequency baseband signal of each sampled radar into discrete quantized values represented by binary data;
and step 3: the high-speed serial data formed by discrete quantized values is decelerated into low-speed parallel data matched with the writing time of the memory through a serial-parallel converter, and the low-speed parallel data are written into the storage address of the memory by the second FPGA according to the sequence set and arranged by the second FPGA or the first FPGA to be used as storage data, so that the storage control of the second FPGA is realized;
the second FPGA generates a storage address and a control signal required for storing the low-speed parallel data according to an external command when performing storage control, and transmits the storage address and the control signal to the first FPGA to write the low-speed parallel data into the memory; the external command is a command directly transmitted through the external control unit or forwarded through the first FPGA.
And 4, step 4: when the reproduction is needed, reading out the storage data from the storage address of the memory, converting the storage data into a high-speed digital signal, and recovering to obtain a processed signal; the processed signal is used as the reproduced original signal.
And 5: in addition, when the interference signal generating device performs deception interference, the second FPGA is used as a DDS device with a frequency modulation and phase modulation function through the second DAC to synchronously generate an interference signal of a noise baseband during the period of obtaining the processed signal, the interference signal of the noise baseband is synchronously generated and mixed with the processed signal to form an interference signal, and the interference signal is emitted out according to the area set by the gate signal received by the first FPGA for interference.
The interference signal generating device also comprises a priority judging module which runs on the second FPGA, when the storage data which needs to be read out have conflict, the conflict means that a plurality of storage data are selected to be read, and the storage data with high priority can be determined to be read preferentially according to the preset priority. Specifically, when the stored data to be read conflict, the first FPGA sends a message of a priority determination request including an identifier of the stored data to be read to the second FPGA, the second FPGA compares and sorts the identifier of the stored data to be read according to the priority of a predetermined identifier in a sequence from high to low, and then returns the sequence of the identifier to the first FPGA, so that the first FPGA can read the stored data corresponding to the identifier in the sequence according to the sequence of the identifier, a mapping table can be temporarily stored in the second FPGA, the mapping table stores the mapping relationship between the identifier of the stored data and the priority in advance, and a part of tasks of priority determination can be issued to the DSP processor for execution, thereby improving the speed and efficiency of priority determination.
The specific process from step 1 to step 3 is as follows: the frequency, the phase and the amplitude of an intermediate frequency baseband signal of the radar are recorded by signal generation equipment serving as a DRFM (digital radio frequency modulation), so that a processed signal under an original signal can be obtained, the frequency, the phase and the amplitude of the intermediate frequency baseband signal of the radar are recorded by the signal generation equipment in advance, the intermediate frequency baseband signal of the radar is quantized into high-speed serial data through an ADC (analog-to-digital converter), the high-speed serial data is subjected to speed reduction processing through a serial-to-parallel conversion circuit to obtain low-speed parallel data, the low-speed parallel data are sent to a dual-port RAM (random access memory) to be stored, then a second FPGA controls a first FPGA to generate a corresponding read signal and a read address after corresponding delay, and the read address can be that the first FPGA stores the stored data in the memory address and then transmits the memory address to the second FPGA as the read signal; therefore, the first FPGA reads out the stored data stored in the read address in the dual-port RAM according to the read signal, the stored data read out after time delay is converted into a high-speed digital signal through the parallel-serial conversion circuit, the high-speed digital signal is sent to the first DAC according to the frequency, the phase and the amplitude of the intermediate frequency baseband signal of the radar recorded in advance and is recovered into a processed signal, and the processed signal is used as an original signal after reproduction.
In order to achieve the purpose of monitoring the stored data in the memory on site, the second FPGA is also connected with a wireless communication module through a Rapid IO interface, a wireless PDA is equipped for a field worker, the wireless communication module is wirelessly connected with the wireless PDA, so that the first FPGA can be controlled by the second FPGA to take the stored data out of the memory, then the stored data is transmitted into the second FPGA and is transmitted into the wireless PDA of the field worker by the second FPGA through the wireless communication module to be displayed, and the purpose of monitoring the stored data is achieved.
However, in an era that enterprise personnel share data more and more importantly, when a field worker wants to transmit a stored data to the handheld terminals of all sharers in the sharing list of all wireless PDAs, the field worker needs to select the corresponding stored data through the wireless PDA, and then transmits the stored data to the handheld terminals of all sharers in the local sharing list through the wireless PDA, so that the operation process is extremely complicated; and when some handheld terminals are not beside the sharer, are in a condition of being exhausted and actually incapable of being used; the field worker can not transmit the stored data to the handheld terminals of the sharers in the sharing list under the condition that the field worker can not operate, great inconvenience is brought to the field worker, and the effect of the field worker on operating the wireless PDA is poor; the sharing table comprises the IP addresses of the handheld terminals of all sharers. The handheld terminal can also be a wireless PDA.
Through improvement, in order to achieve the purpose of monitoring the stored data in the memory on site, the second FPGA is also connected with a wireless communication module through a Rapid IO interface, a wireless PDA is equipped for a field worker, the wireless communication module is wirelessly connected with the wireless PDA, so that the first FPGA can be controlled by the second FPGA to take the stored data out of the memory, then the stored data is transmitted into the second FPGA and is transmitted into the wireless PDA of the field worker by the second FPGA through the wireless communication module to be displayed, and the purpose of monitoring the stored data is achieved.
In an era when enterprise personnel sharing data is increasingly important, field workers often need to transmit a stored data to the handheld terminals of all sharers in a sharing list of all wireless PDAs, and the IP addresses of the handheld terminals of all sharers are included in the sharing list. The handheld terminal can also be a wireless PDA.
The method for transferring a stored data to the hand-held terminals of each sharer in the sharing list of the whole wireless PDA comprises the following steps:
a-1, the wireless PDA transmits the sharing table of the wireless PDA and the IP address of the backup server where the sharing table of the wireless PDA is located to a processing terminal by means of the uniform selection broadcast command recorded by a field worker. The processing terminal can be a PC.
The uniform selection broadcast command in A-1 is a command for representing a field worker to select all the handheld terminals of sharers in the sharing list of the wireless PDA to transmit stored data to be transmitted;
a-2, the processing terminal obtains all sharing tables in the backup server according to the IP address of the backup server, deduces the number K of the corresponding handheld terminals of the sharer in the sharing table of the wireless PDA, and also derives the number L of the corresponding handheld terminals of all the sharers in all the sharing tables;
here, since the shared tables of all wireless PDAs of the same site worker are stored in the same storage area of the backup server, the all shared tables obtained by the processing terminal in a-2 include the shared tables of all wireless PDAs of the site worker.
A-3, comparing K and L, when L is higher than K, executing grouping to the hand-held terminals of all sharers, dividing the group into a plurality of groups of sharing table I, and sequentially transmitting each sharing table I to the wireless PDA;
a-3, the process of grouping the handheld terminals of the total sharers into the first sharing table of a plurality of groups comprises the following steps: executing grouping by using the number of the handheld terminals of the sharers corresponding to each sharing table I as K, and dividing the grouping into L/K group sharing tables I; if L is 1500 and K is 25, then the grouping is performed with the number of handheld terminals of each sharer corresponding to one sharing table being 25, and the sharing table is divided into 60 groups, that is, 1500 ÷ 25 ═ 60 groups of sharing tables one; when L ÷ K cannot be divided evenly, the number of handheld terminals of the sharer in the unremoved part serves as the number of handheld terminals of the sharer in the sharing table one of the last group, as if L is 570, K is 20, L ÷ K ═ 28, the unremoved part of which is 1, the sharing table of the first 28 groups is divided into 29 groups, where the number of handheld terminals of the sharer corresponding to the sharing table of the first 28 groups is 20, and the number of handheld terminals of the sharer corresponding to the sharing table of the 29 th group is 1.
In step S30, when transferring each sharing table one to the wireless PDA, the processing terminal also concurrently displays the sharing table one transferred at the time of the display and the sequence of the sharing table one in the group; the field worker can know the condition and the process of the stored data transmission in real time.
Here, when L is not over K, then the processing terminal responds to the corresponding wireless PDA with a grouping failure message and terminates the process; the wireless PDA receives the grouping failure message, and then transmits the stored data to be transmitted to the handheld terminal of each sharer corresponding to the sharing table of the wireless PDA by means of the existing mode.
A-4, after receiving each sharing table one, the wireless PDA transfers the stored data to be transferred to the handheld terminal of each sharer in the sharing table one of the corresponding group;
in A-4, after receiving a sharing table I, the wireless PDA firstly adds the identification of all sharer hand-held terminals or the title of the sharer hand-held terminal of the sharing table I of the corresponding group into a receiver entry area of the storage data to be transmitted, and then transmits the storage data to be transmitted which is selected in advance to the identification of the sharer hand-held terminal in the receiver entry area or the identification of the corresponding sharer hand-held terminal corresponding to the title of the sharer hand-held terminal of the sharer by means of a transmission command entered by a field worker. The name of the handheld terminal of the sharer can be a unique number of the handheld terminal of the sharer or a unique user name of the handheld terminal of the sharer; the identity of the sharer's handheld terminal can be the mac address of the wireless PDA or the account number of the MSN running on it.
The method that the wireless PDA stores the sharing table of the wireless PDA to the backup server is also included before the A-1; the wireless PDA stores the sharing table of the wireless PDA to the backup server as follows:
b-1, said wireless PDA transmitting a sharing table storing request message with wireless PDA message, sharing table of said wireless PDA to the backup server;
b-2, the backup server judges whether the backup server is a storage area with the sharing table of the wireless PDA corresponding to the wireless PDA message or not by means of the sharing table storage request message; if so, B-3 is executed; if not, B-4 is executed;
b-3, storing the sharing table of the wireless PDA into the storage area of the sharing table of the wireless PDA;
b-4, configuring the storage area of the sharing table of the wireless PDA for the wireless PDA in the backup server, and storing the sharing table of the wireless PDA into the storage area of the sharing table of the wireless PDA.
Here, the wireless PDA message can be a name of the wireless PDA, a MAC address of the wireless PDA; the same field worker is a field worker with the same wireless PDA; as if the corresponding wireless PDAs of the plurality of wireless PDAs were consistently referred to as all easters, then it was determined that the plurality of wireless PDAs belonged to the same worker at the site.
Here, the selective broadcast command has an identification of the wireless PDA. The processing terminal performs grouping on the handheld terminals of the total sharer, and the following processing is further included after the processing terminal is divided into the sharing table I of a plurality of groups: the processing terminal backups the storage data of the group, adds the identifier of the wireless PDA to the storage data of the group, and stores the storage data of the group of the added identifier of the wireless PDA to the storage area of the sharing table of the wireless PDA corresponding to the wireless PDA in the backup server.
Here, the following treatment method is also included after a-1: the processing terminal judges whether the storage data of the grouping added with the wireless PDA identification exists in the backup server or not; if yes, the processing terminal obtains the stored data of the groups and sequentially transmits a sharing table one of each group in the stored data of the groups to the wireless PDA; if not, the processing terminal executes A-2 and A-3. The clustered storage data can be reused, so that the storage data transmission processing mode is greatly reduced, and the loss of software and hardware of the whole system is reduced.
Thus, by storing the shared tables of all wireless PDAs of the same worker on site in the same storage area of the backup server; the wireless PDA transmits the sharing table of the wireless PDA and the IP address of the backup server where the sharing table of the wireless PDA is located to a processing terminal by means of an equal selection broadcast command input by a field worker; the processing terminal obtains all sharing tables in the backup server, deduces the number K of the handheld terminals of the sharer corresponding to the sharing table of the wireless PDA, and also derives the number L of the handheld terminals of the sharer corresponding to all the sharing tables; comparing K and L, when L is higher than K, grouping the hand-held terminals of all sharers, dividing the hand-held terminals into a plurality of group sharing tables I, and sequentially transmitting each group sharing table I to the wireless PDA; the method is characterized in that after the wireless PDA receives the sharing table I of each group, the stored data to be transmitted is transmitted to the handheld terminals of each sharer in the sharing table I of the corresponding group, the site worker can transmit the stored data to the handheld terminals of each sharer in the sharing tables of all the wireless PDAs of the site worker only by activating the uniformly-selected broadcast command through any operable wireless PDA, and the condition that other wireless PDAs are not in operable condition is not considered.
Aiming at the method for delivering a stored data to the handheld terminals of all sharers in the sharing list of the whole wireless PDA, a set of system architecture is provided, and the system architecture comprises the following steps: the system comprises a backup server, a plurality of wireless PDAs of workers on the same site and a processing terminal. The backup server is used for storing the sharing list of the wireless PDA of all the wireless PDAs of the same field worker in the same storage area of the backup server. Each wireless PDA is used for transmitting the sharing table of the wireless PDA and the IP address of the backup server where the sharing table of the wireless PDA is located to a processing terminal by means of the uniform selection broadcast command input by a field worker; and receiving the sharing table I of each group transmitted by the intelligent terminal, and transmitting the stored data to be transmitted to the handheld terminal of each sharer in the sharing table I of the corresponding group after receiving each group of sharing table I. The processing terminal is used for obtaining all sharing tables in the backup server by means of the sharing table of the wireless PDA and the storage area address of the sharing table of the wireless PDA in the backup server, which are transmitted by the wireless PDA, deducing the number K of the handheld terminals of the sharer corresponding to the sharing table of the wireless PDA, and the number L of the handheld terminals of the total sharer corresponding to all the sharing tables; comparing K with L, when L is higher than K, executing grouping to all sharing persons' hand-held terminals, dividing into several groups of sharing table one, and transmitting each group of sharing table one to the wireless PDA in sequence.
The uniform selection broadcast command represents a command that a field worker selects all the handheld terminals of the sharers in the sharing list of the wireless PDA to transmit the stored data to be transmitted;
here, since the shared tables of all the wireless PDAs of the same site worker are stored in the same storage area of the backup server, the all-shared table obtained by the processing terminal here includes the shared tables of the wireless PDAs of all the wireless PDAs of the site worker.
Here, when L is not over K, then the processing terminal responds to the corresponding wireless PDA with a grouping failure message and terminates the process; the wireless PDA receives the grouping failure message, and then transmits the stored data to be transmitted to the handheld terminal of each sharer corresponding to the sharing table of the wireless PDA by means of the existing mode.
After receiving a sharing table, the wireless PDA firstly adds the identification of all sharer hand-held terminals or the title of the sharer hand-held terminal of a corresponding group of sharing tables to a recipient entry area of the stored data to be transferred, and then transfers the stored data to be transferred selected in advance to the identification of the sharer hand-held terminal in the recipient entry area or the identification of the corresponding sharer hand-held terminal by the title of the sharer hand-held terminal by means of a transfer command entered by a field worker. The name of the handheld terminal of the sharer can be a unique number of the handheld terminal of the sharer or a unique user name of the handheld terminal of the sharer; the identity of the sharer's handheld terminal can be the mac address of the wireless PDA or the account number of the MSN running on it.
In the architecture, the wireless PDA is further configured to communicate a shared table save request message with a wireless PDA message, a shared table of the wireless PDA, to a backup server; the backup server is further used for judging whether the backup server is a storage area with the sharing table of the wireless PDA corresponding to the wireless PDA message or not by the backup server through the sharing table storage request message; if yes, storing the sharing table of the wireless PDA into the storage area of the sharing table of the wireless PDA; if not, the storage area of the sharing table of the wireless PDA is configured for the wireless PDA at the backup server, and the sharing table of the wireless PDA is stored in the storage area of the sharing table of the wireless PDA. The wireless PDA message can be the name of the wireless PDA and the MAC address of the wireless PDA; the same field worker is a field worker with the same wireless PDA; as if the corresponding wireless PDAs of the plurality of wireless PDAs were consistently referred to as all easters, then it was determined that the plurality of wireless PDAs belonged to the same worker at the site.
Here, the selective broadcast command has an identification of the wireless PDA. The processing terminal performs grouping on the handheld terminals of the total sharer, and the following processing is further included after the processing terminal is divided into the sharing table I of a plurality of groups: the processing terminal backups the storage data of the group, adds the identifier of the wireless PDA to the storage data of the group, and stores the storage data of the group of the added identifier of the wireless PDA to the storage area of the sharing table of the wireless PDA corresponding to the wireless PDA in the backup server.
Here, the processing terminal is further configured to determine whether there is stored data of a group to which the wireless PDA identifier is added in the backup server after receiving the IP address of the backup server in which the sharing table of the wireless PDA and the sharing table of the wireless PDA transmitted by the wireless PDA are located; if yes, the processing terminal obtains the stored data of the groups and sequentially transmits a sharing table one of each group in the stored data of the groups to the wireless PDA; if not, the processing terminal executes A-2 and A-3. The clustered storage data can be reused, so that the storage data transmission processing mode is greatly reduced, and the loss of software and hardware of the whole system is reduced.
Here, the processing terminal is further configured to, when transferring the first sharing table of each group to the wireless PDA, concurrently display the transferred first sharing table at the time of the transfer, and further change the order of the first sharing table of the group in the grouping; the field worker can know the condition and progress of the stored data transmission in real time.
Here, the processing terminal is further configured to perform grouping on the handheld terminals of the total sharer, and the process of dividing the handheld terminals of the total sharer into the first sharing table of the plurality of groups includes: executing grouping by using the number of the handheld terminals of the sharers corresponding to each sharing table I as K, and dividing the grouping into L/K group sharing tables I; if L is 1500 and K is 25, then the grouping is performed with the number of handheld terminals of each sharer corresponding to one sharing table being 25, and the sharing table is divided into 60 groups, that is, 1500 ÷ 25 ═ 60 groups of sharing tables one; when L ÷ K cannot be divided evenly, the number of handheld terminals of the sharer in the unremoved part serves as the number of handheld terminals of the sharer in the sharing table one of the last group, as if L is 570, K is 20, L ÷ K ═ 28, the unremoved part of which is 1, the sharing table of the first 28 groups is divided into 29 groups, where the number of handheld terminals of the sharer corresponding to the sharing table of the first 28 groups is 20, and the number of handheld terminals of the sharer corresponding to the sharing table of the 29 th group is 1.
Thus, by storing the shared tables of all wireless PDAs of the same worker on site in the same storage area of the backup server; the wireless PDA transmits the sharing table of the wireless PDA and the IP address of the backup server where the sharing table of the wireless PDA is located to a processing terminal by means of an equal selection broadcast command input by a field worker; the processing terminal obtains all sharing tables in the backup server, deduces the number K of the handheld terminals of the sharer corresponding to the sharing table of the wireless PDA, and also derives the number L of the handheld terminals of the sharer corresponding to all the sharing tables; comparing K and L, when L is higher than K, grouping the hand-held terminals of all sharers, dividing the hand-held terminals into a plurality of group sharing tables I, and sequentially transmitting each group sharing table I to the wireless PDA; the method is characterized in that after the wireless PDA receives the sharing table I of each group, the stored data to be transmitted is transmitted to the handheld terminals of each sharer in the sharing table I of the corresponding group, the site worker can transmit the stored data to the handheld terminals of each sharer in the sharing tables of all the wireless PDAs of the site worker only by activating the uniformly-selected broadcast command through any operable wireless PDA, and the condition that other wireless PDAs are not in operable condition is not considered.
The present invention has been described in an illustrative manner by the embodiments, and it should be understood by those skilled in the art that the present disclosure is not limited to the embodiments described above, but is capable of various changes, modifications and substitutions without departing from the scope of the present invention.
Claims (7)
1. An interference signal generating device is characterized by comprising a signal generating device and a processing device, wherein the signal generating device is used for generating and finally outputting a processed signal; the processing device is connected with the signal generating equipment;
the processing means controls the signal generating device to increase a generation speed of an interference signal;
the signal generation equipment comprises a first FPGA, an ADC, a memory and a first DAC;
the signal output end of the ADC, the input end of the first DAC and the memory are connected with the first FPGA;
the signal input end of the ADC is used for receiving an initial signal;
the output end of the first DAC is used for outputting the processed signal;
the processing device comprises a second FPGA, a second DAC and a DSP processor;
a priority decision module is operated on the second FPGA and used for deciding that the storage data with high priority is read preferentially according to the preset priority when the storage data needing to be read conflict;
the second DAC and the DSP processor are both connected with the second FPGA;
the DSP processor can assist in processing tasks of the second FPGA that control generation of interference signals;
the second DAC is used for generating an interference signal of a noise baseband;
the second FPGA is also connected with the first FPGA;
the interference signal generating device further comprises an external clock, and the external clock is connected with the clock input end of the ADC, the second FPGA and the DSP processor.
2. The jammer generation apparatus of claim 1, wherein the initial signal is an intermediate frequency baseband signal of a sampled radar; the processed signal is an intermediate frequency baseband signal of the processed radar.
3. The jamming signal generating apparatus of claim 1, wherein the first FPGA comprises a serial to parallel converter, the serial to parallel converter being connected to a signal output of the ADC;
the memory is a double-port RAM, and two I/O control ports of the double-port RAM are connected with the first FPGA;
the first FPGA further comprises a parallel-to-serial converter, and the parallel-to-serial converter is connected with the input end of the first DAC.
4. The jamming signal generating apparatus according to claim 1, wherein the first FPGA is further configured to receive an external gate signal;
the first FPGA is connected with an external control unit through a first I/O interface;
the second FPGA is connected with an external control unit through a second I/O interface;
the first FPGA is connected with the second FPGA through a third I/O interface;
the second FPGA is connected with the FLASH memory;
and the DSP processor is connected with an external terminal through an Ethernet interface.
5. An interference signal generating method is characterized in that an interference signal generating device comprises a signal generating device and a processing device, wherein the signal generating device is used for generating and finally outputting a processed signal; the processing device is connected with the signal generating equipment;
the method comprises the following steps: the processing means controls the signal generating device to increase a generation speed of an interference signal;
the signal generation equipment comprises a first FPGA, an ADC, a memory and a first DAC;
the signal output end of the ADC, the input end of the first DAC and the memory are connected with the first FPGA;
the signal input end of the ADC is used for receiving an initial signal;
the output end of the first DAC is used for outputting the processed signal;
the processing device comprises a second FPGA, a second DAC and a DSP processor;
a priority decision module is operated on the second FPGA and used for deciding that the storage data with high priority is read preferentially according to the preset priority when the storage data needing to be read conflict;
the second DAC and the DSP processor are both connected with the second FPGA;
the DSP processor can assist in processing tasks of the second FPGA that control generation of interference signals;
the second DAC is used for generating an interference signal of a noise baseband;
the second FPGA is also connected with the first FPGA;
the interference signal generating device further comprises an external clock, and the external clock is connected with the clock input end of the ADC, the second FPGA and the DSP processor.
6. The interference signal generating method according to claim 5, wherein the method for controlling the signal generating device by the processing apparatus to increase the generation speed of the interference signal comprises the steps of:
step 1: the second FPGA controls the first FPGA to enable the ADC to sample an intermediate-frequency baseband signal of the radar serving as an initial signal;
step 2: the ADC converts the intermediate frequency baseband signal of each sampled radar into discrete quantized values represented by binary data;
and step 3: the serial data formed by the discrete quantized values is decelerated into parallel data matched with the writing time of the memory through a serial-parallel converter, and the parallel data are written into the storage address of the memory by the second FPGA according to the sequence set and arranged by the second FPGA or the first FPGA to be used as storage data, so that the storage control of the second FPGA is realized;
the second FPGA generates a storage address and a control signal required for storing low-speed parallel data according to an external command during storage control, and transmits the storage address and the control signal to the first FPGA to write the parallel data into a memory;
and 4, step 4: when the reproduction is needed, reading out the storage data from the storage address of the memory, converting the storage data into a high-speed digital signal, and recovering to obtain a processed signal;
and 5: in addition, during the period of obtaining the processed signal, the second FPGA synchronously generates an interference signal of the noise baseband through the second DAC, the interference signal of the synchronously generated noise baseband and the processed signal are mixed to form an interference signal, and the interference signal is emitted out according to the area set by the gate signal received by the first FPGA for interference.
7. The method according to claim 6, wherein the specific processes of step 1 to step 3 are as follows: the signal generating device records the frequency, the phase and the amplitude of an intermediate frequency baseband signal of a radar in advance, the intermediate frequency baseband signal of the radar is quantized into serial data through an ADC (analog-to-digital converter), the serial data is subjected to speed reduction processing through a serial-to-parallel conversion circuit to obtain parallel data, the parallel data is sent to a dual-port RAM to be stored, then the second FPGA controls the first FPGA to generate a corresponding read signal and a read address after corresponding delay, so that the first FPGA reads out the stored data stored in the read address in the dual-port RAM according to the read signal, the stored data read out after delay is converted into a high-speed digital signal through a parallel-to-serial conversion circuit, and the high-speed digital signal is sent to the first DAC according to the frequency, the phase and the amplitude of the intermediate frequency baseband signal of the radar recorded in advance to be recovered into the processed signal.
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| CN111800365A (en) * | 2020-07-03 | 2020-10-20 | 湖南华诺星空电子技术有限公司 | Interference signal generation method and device |
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| CN104360326B (en) * | 2014-11-24 | 2017-05-10 | 电子科技大学 | Digital storage and forwarding type interference system |
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