CN110515890B - Data analysis method and system of multiprocessor system-on-chip MPSOC - Google Patents
Data analysis method and system of multiprocessor system-on-chip MPSOC Download PDFInfo
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Abstract
The invention provides a data analysis method of MPSOC, which comprises the following steps: the differential input clock buffer IBUFDS converts the first electric signal and the second electric signal which are input in a differential mode to obtain a single-ended signal; the global clock buffer BUFG carries out synchronous processing on the single-ended signals to obtain delay-free single-ended signals; the phase-locked loop PLL processes the single-ended signal without delay to obtain a first clock signal with 7 times of frequency; the data is collected by a 7-frequency multiplied first clock signal. Thus, by using a normal IO as a clock input, 7 is realized according to homology of PLL clock output and the like: 1, no GC pins are occupied, MMCM is occupied, and a large amount of data integration is not needed. Since each BANK has 2 PLLs, this can achieve more paths of 7: LVDS parsing of 1. Because the analysis is simpler, a large amount of resources are saved, and the resources are vacated for other processing.
Description
Technical Field
The present invention relates to the field of data processing technologies, and in particular, to a data analysis method and system for a multiprocessor system on a chip (Multi Processor System on Chip, mps oc).
Background
The intellectual property core (Intellectual Property core, IP) of the current mpssoc does not support 7:1, whereas most visual information requires 7:1, and the data can be processed after analysis.
Sirolimus (xilinx) gives one solution 7:1, a data analysis method, which comprises the following steps:
the video output consists of a channel CLOCK (CLOCK) and possibly multiple DATA (DATA). The associated clock must be connected to pins that can be used as GC, then the received differential data is transferred with 2 clocks (phase 180) through ibufds_diff_out, delay aligned through IDELAY3, and then 8 through ISERDESE 3: 1, then, through shifting by a 2-way clock, and then, processing to obtain final data, and realizing 7:1 resolving.
However, this method has the following drawbacks:
(1) The associated clock must be connected to the GC pin, which is only assigned to the phase locked loop (PhaseLockedLoop, PLL)/mixed mode clock manager (Mixed Mode Clock Manager, MMCM) for use in the ideelay 3.
(2) Parsing is performed based on the primitives of ISERDESE 3.
(3) The later data arrangement is complicated.
Disclosure of Invention
The embodiment of the invention aims to provide a data analysis method and a system of MPSOC, which are used for solving the problems that an associated clock in MPSOC analysis in the prior art is required to be connected to a GC pin, the analysis is required to be performed based on primitives of ISERDESE3 and the later data arrangement is complicated.
In order to solve the above problems, in a first aspect, the present invention provides a data parsing method of an mpssoc, the method comprising:
the differential input clock buffer IBUFDS converts the first electric signal and the second electric signal which are input in a differential mode to obtain a single-ended signal;
the global clock buffer BUFG carries out synchronous processing on the single-ended signals to obtain delay-free single-ended signals;
the phase-locked loop PLL processes the single-ended signal without delay to obtain a first clock signal with 7 times of frequency;
and collecting data through the 7 times frequency first clock signal.
In one possible implementation manner, after the phase-locked loop PLL processes the single-ended signal without delay to obtain the first clock signal with 7 times of frequency, the method further includes:
the phase-locked loop PLL processes the single-ended signal without delay to obtain a first clock signal with 7 times frequency and a second clock signal at the same time;
and aligning the original data input into IDELAY3 or FIFO by the rising edge of the second clock signal to obtain the data.
In one possible implementation, the first clock signal and the second clock signal are homologous clock signals.
In one possible implementation manner, the acquiring data by the 7 times frequency first clock signal specifically includes:
and acquiring the data through the falling edge of the 7 times frequency first clock signal.
In one possible implementation, the duty cycle of the 7-fold multiplied first clock signal is 4:3.
In one possible implementation, the PLL includes a phase frequency detector PFD, a low pass filter LPF, a voltage controlled oscillator VCO, and a feedback divider;
the output end of the PFD is connected to the input end of the LPF, the input end of the LPF is connected to the input end of the VCO, the output end of the VCO is connected to the input end of the feedback frequency divider, and the output end of the feedback frequency divider is connected to the PFD.
In one possible implementation, the PFD includes a first flip-flop, a second flip-flop, a delay element, an and gate, an inverter NMOS transistor, and a PMOS transistor;
the clock end of the first trigger is respectively connected to the clock end of the second trigger and the first end of the delay element, the output end of the first trigger is respectively connected to the input end of the phase inverter and the first input end of the AND gate, the output end of the second trigger is respectively connected to the second input end of the AND gate and the grid electrode of the NMOS tube, the drain electrode of the NMOS tube is connected to the drain electrode of the PMOS tube, the grid electrode of the NMOS tube is connected to the output end of the phase inverter, and the output end of the AND gate is connected to the second end of the delay element.
In a second aspect, the present invention provides a data parsing system of a mpssoc, the system comprising:
the device comprises a differential input clock buffer IBUFDS, a first clock buffer and a second clock buffer, wherein the IBUFDS is used for converting a first electric signal and a second electric signal which are input in a differential mode to obtain a single-ended signal;
the global clock buffer BUFG is used for carrying out synchronous processing on the single-ended signals to obtain delay-free single-ended signals;
a phase-locked loop PLL, configured to process the single-ended signal without delay to obtain a first clock signal with 7 times of frequency; and then collecting data through the 7 times frequency first clock signal.
In a possible implementation manner, the PLL is further configured to process the single-ended signal without delay to obtain a first clock signal with 7 times frequency and obtain a second clock signal at the same time;
and aligning the original data input into IDELAY3 or FIFO by the rising edge of the second clock signal to obtain the data.
In one possible implementation, the first clock signal and the second clock signal are homologous clock signals.
In a third aspect, the present invention provides an apparatus comprising a memory for storing a program and a processor for performing the method of any of the first aspects.
In a fourth aspect, the present invention provides a computer program product comprising instructions which, when run on a computer, cause the computer to perform the method of any of the first aspects.
In a fifth aspect, the present invention provides a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements a method according to any of the first aspects.
By applying the data analysis method and system of the MPSOC provided by the embodiment of the invention, the common IO is adopted as the clock input, and the 7 is realized according to the homology and the like of the PLL clock output: 1, no GC pins are occupied, MMCM is occupied, and a large amount of data integration is not needed. Since each BANK has 2 PLLs, this can achieve more paths of 7: LVDS parsing of 1. Because the analysis is simpler, a large amount of resources are saved, and the resources are vacated for other processing.
Drawings
Fig. 1 is a flow chart of a data parsing method of a mpssoc according to a first embodiment of the invention;
fig. 2 is a schematic diagram of a PLL according to a first embodiment of the invention;
fig. 3 is a schematic structural diagram of a PFD according to a first embodiment of the present invention;
FIG. 4 is a schematic diagram of a first clock signal and a second clock signal with 7 times frequency according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a FIFO structure according to a first embodiment of the present invention;
FIG. 6 is a schematic diagram of a 7:1 acquisition system according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of a data analysis system of a mpssoc according to a second embodiment of the invention.
Fig. 8 is an example of a structure of a data parsing system of a mpssoc according to the second embodiment of the invention;
fig. 9 is a schematic diagram of the data format of fig. 8.
Detailed Description
The present application is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be noted that, for convenience of description, only the portions related to the present invention are shown in the drawings.
It should be noted that, in the case of no conflict, the embodiments and features in the embodiments may be combined with each other. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
Fig. 1 is a flow chart of a data analysis method of mpssoc provided in an embodiment of the present invention, and the method may be applied to a processor of an unmanned vehicle, as shown in fig. 1, and the method includes the following steps:
step 101, a differential input clock buffer (Differential Signaling Input Buffer with Selectable I/O Interface, IBUFDS) performs conversion processing on a first electrical signal and a second electrical signal that are input in a differential manner, so as to obtain a single-ended signal.
Specifically, on an mpssoc chip, IBUFDS is provided, the IBUFDS supports a low-voltage differential signal, and differential processing is performed on the first electrical signal and the second electrical signal to obtain a single-ended signal. Therefore, a common pin can be adopted, the differential signal is converted into a single-ended signal through the IBUFDS, the xilinx outputs the differential signal through the IBUFDS_DIFF_OUT, and the application does not need to pass through a special IBUFDS_DIFF_OUT pin, so that the application range of the application is enlarged.
Step 102, the global clock buffer (Global clock selection buffer, BUFG) performs a synchronous processing on the single-ended signal to obtain a single-ended signal without delay.
Specifically, on a MPSOC chip, there is BUFG.
Step 103, a phase-locked loop (PLL) processes the single-ended signal without delay to obtain a 7-frequency multiplied first clock signal.
Specifically, referring to fig. 2, the PLL on the mpssoc chip includes a phase-frequency detector (PFD), a Low-Pass Filter (LPF), a voltage-controlled oscillator (Voltage controlled oscillator, VCO), and a feedback divider (N Counter). The output of the PFD is connected to the input of the LPF, the input of the LPF is connected to the input of the VCO, the output of the VCO is connected to the input of the feedback divider, and the output of the feedback divider is connected to the PFD.
Wherein the low pass filter filters out high phase noise. The voltage controlled oscillator includes a variable tuning element, such as a varactor diode, whose capacitance varies with the input voltage to form a tunable resonant circuit, thereby producing a range of frequencies. The feedback divider is used to divide the VCO frequency into PFD frequencies, allowing the PLL to generate an output frequency that is a multiple of the PFD frequencies.
The structure of the PFD referring to fig. 3, in fig. 3, the PFD includes a first flip-flop U1, a second flip-flop U2, a delay element D, an and gate U3, an inverter U4, an N-Metal-Oxide-Semiconductor (NMOS) tube, and a P-Metal-Oxide-Semiconductor (PMOS) tube.
The clock end CLR1 of the first trigger U1 is respectively connected to the clock end CLR2 of the second trigger U2 and the first end of the delay element D, the output end Q1 of the first trigger U1 is respectively connected to the input end of the inverter U3 and the first input end of the AND gate U3, the output end Q2 of the second trigger U2 is respectively connected to the second input end of the AND gate U3 and the grid electrode of the NMOS tube N1, the drain electrode of the NMOS tube N1 is connected to the drain electrode of the PMOS tube P1, the grid electrode of the NMOS tube N1 is connected to the output end of the inverter U4, and the output end of the AND gate U3 is connected to the second end of the delay element D.
Specifically, the phase frequency detector compares the Fref input at the +IN terminal with the feedback signal at the-IN terminal, and the first trigger and the second trigger are D-type triggers. One of the flip-flops outputs an enable positive current source and the other flip-flop outputs an enable negative current source. These current sources are so-called charge pumps.
Step 104, collecting data through 7 times frequency first clock signals.
Specifically, one path of clock consistent with the original clock and one path of 7-frequency-multiplied clock are output through the PLL, and the two paths of clocks are homologous clocks, see CLK0 and CLK1 in fig. 4, where the 7-frequency-multiplied first clock signal is CLKO, and the second clock signal is CLK1.
After the corresponding clock is generated, CLK1 of the same frequency is used for ideelay 3 to align the original data with the rising edge of the clock. And then the data is analyzed by using a 7-frequency-multiplied second clock signal, and the data is acquired by using the falling edge of the 7-frequency-multiplied second clock signal in fig. 4.
The use of IDELAY3 does not occupy RAM resources, and FIFO structure is also possible if first-in first-out (First Input First Output, FIFO) alignment is desired, see fig. 5.
The FIFO occupies the resources of the random access memory (Random Access Memory, RAM) of the Field programmable gate array (Field-Programmable Gate Array, FPGA), and the FIFO speed is also one reason for consideration, and the FIFO speed of the current mpssoc can be up to 637M, and the current video data is more than about 350M.
After alignment, the data is related to the clock, see FIG. 6.
This allows the data to be collected on the falling edge of CLK0, and subjected to 7:1, then sorting the parsed data according to the data format, and realizing 7: 1.
It should be noted that, the error between the hardware design data and the clock is within 20 mils, and the delay is approximately 3.5ps according to the transmission of the electrical signal, while the rising and falling time of the video can tolerate 350ps at maximum, and the delay of the hardware is far less than the rising and falling time, so that the alignment can be realized without separate calibration. The ideelay 3 can be omitted, and in particular, whether it is determined according to the hardware design is omitted.
By applying the data analysis method of the MPSOC provided by the embodiment of the invention, the common IO is adopted as the clock input, and the 7 is realized according to the homologous clock signal output by the PLL clock: 1, and no GC pins, mixed-mode clock manager (Mixed-Mode Clock Manager, MMCM), and no large amount of data integration. The Input-Output buffers (IOBs) of the FPGA are divided into several groups (BANKs), each group having 2 PLLs, so that a more multiplexed 7: the Low-voltage differential signal (Low-Voltage Differential Signaling, LVDS) of 1 is analyzed, so that the analysis is simpler, a large amount of resources are saved, and resources are saved for other processing.
Fig. 7 is a schematic structural diagram of a data analysis system of an mpssoc according to a second embodiment of the present invention, where the data analysis system of the mpssoc is applied in a data analysis method of the mpssoc, and as shown in fig. 7, a data analysis system 700 of the mpssoc includes: IBUFDS 701, BUFG 702, PLL 703.
The IBUFDS 701 is configured to perform conversion processing on a first electrical signal and a second electrical signal that are input differentially, so as to obtain a single-ended signal;
BUFG 702 is used for carrying out synchronous processing on a single-ended signal to obtain a single-ended signal without delay;
the PLL 703 is configured to process a single-ended signal without delay to obtain a first clock signal with 7 times of frequency; the data is then collected by 7 times the frequency of the first clock signal.
Further, referring to fig. 8, the pll is further configured to process a single-ended signal without delay to obtain a first clock signal with frequency being 7 times, and obtain a second clock signal at the same time;
the original data input to the ideelay 3 or FIFO is aligned by the rising edge of the second clock signal to obtain data.
Wherein the first clock signal and the second clock signal are homologous clock signals.
Fig. 9 is a schematic diagram of the DATA format of fig. 8, and txout0+/-, txout1+/-, txout2+/-, and txout3+/-infig. 9 correspond to DATA0_diff, DATA1_diff, DATA2_diff, and DATA3_diff in fig. 8 in sequence, where the two units are the most significant bit (Most Significant Bit, MSB) and the least significant bit (Least Significant Bit, LSB), respectively.
The PLL structure is consistent with that described in the first embodiment, and the technical effect of the data parsing system of the mpssoc is consistent with that of the data parsing method of the mpssoc, which is not described herein.
An embodiment of the present invention provides an apparatus, including a memory and a processor, where the memory is configured to store a program, and the memory may be connected to the processor through a bus. The memory may be non-volatile memory, such as a hard disk drive and flash memory, in which software programs and device drivers are stored. The software program can execute various functions of the method provided by the embodiment of the invention; the device driver may be a network and interface driver. The processor is configured to execute a software program, where the software program is executed to implement the method provided in the first embodiment of the present invention.
A fourth embodiment of the present invention provides a computer program product containing instructions, which when executed on a computer, cause the computer to perform the method provided by the first embodiment of the present invention.
The fifth embodiment of the present invention provides a computer readable storage medium, where a computer program is stored, and when the computer program is executed by a processor, the method provided in the first embodiment of the present invention is implemented.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative elements and steps are described above generally in terms of function in order to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied in hardware, in a software module executed by a processor, or in a combination of the two. The software modules may be disposed in Random Access Memory (RAM), memory, read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
The foregoing detailed description of the invention has been presented for purposes of illustration and description, and it should be understood that the invention is not limited to the particular embodiments disclosed, but is intended to cover all modifications, equivalents, alternatives, and improvements within the spirit and principles of the invention.
Claims (8)
1. A data parsing method of an mpssoc, the method comprising:
the differential input clock buffer IBUFDS converts the first electric signal and the second electric signal which are input in a differential mode to obtain a single-ended signal;
the global clock buffer BUFG carries out synchronous processing on the single-ended signals to obtain delay-free single-ended signals;
the phase-locked loop PLL processes the single-ended signal without delay to obtain a first clock signal with 7 times of frequency;
collecting data through the 7 times frequency first clock signal;
the phase-locked loop PLL processes the single-ended signal without delay to obtain a first clock signal with frequency doubling of 7, and then further includes:
the phase-locked loop PLL processes the single-ended signal without delay to obtain a first clock signal with 7 times frequency and a second clock signal at the same time;
and aligning the original data input into IDELAY3 or FIFO by the rising edge of the second clock signal to obtain the data.
2. The method of claim 1, wherein the first clock signal and the second clock signal are homologous clock signals.
3. The method according to claim 1, wherein the acquiring data by the 7-frequency multiplied first clock signal specifically comprises:
and acquiring the data through the falling edge of the 7 times frequency first clock signal.
4. The method of claim 1, wherein the duty cycle of the 7-fold multiplied first clock signal is 4:3.
5. The method of claim 1, wherein the PLL comprises a phase frequency detector PFD, a low pass filter LPF, a voltage controlled oscillator VCO, and a feedback divider;
the output end of the PFD is connected to the input end of the LPF, the input end of the LPF is connected to the input end of the VCO, the output end of the VCO is connected to the input end of the feedback frequency divider, and the output end of the feedback frequency divider is connected to the PFD.
6. The method of claim 5, wherein the PFD comprises a first flip-flop, a second flip-flop, a delay element, an and gate, an inverter, an NMOS transistor, and a PMOS transistor;
the clock end of the first trigger is respectively connected to the clock end of the second trigger and the first end of the delay element, the output end of the first trigger is respectively connected to the input end of the phase inverter and the first input end of the AND gate, the output end of the second trigger is respectively connected to the second input end of the AND gate and the grid electrode of the NMOS tube, the drain electrode of the NMOS tube is connected to the drain electrode of the PMOS tube, the grid electrode of the NMOS tube is connected to the output end of the phase inverter, and the output end of the AND gate is connected to the second end of the delay element.
7. A data parsing system of an mpssoc, the system comprising:
the device comprises a differential input clock buffer IBUFDS, a first clock buffer and a second clock buffer, wherein the IBUFDS is used for converting a first electric signal and a second electric signal which are input in a differential mode to obtain a single-ended signal;
the global clock buffer BUFG is used for carrying out synchronous processing on the single-ended signals to obtain delay-free single-ended signals;
a phase-locked loop PLL, configured to process the single-ended signal without delay to obtain a first clock signal with 7 times of frequency; then collecting data through the 7 times frequency first clock signal;
processing the single-ended signal without delay to obtain a first clock signal with 7 times frequency and a second clock signal at the same time;
and aligning the original data input into IDELAY3 or FIFO by the rising edge of the second clock signal to obtain the data.
8. The system of claim 7, wherein the first clock signal and the second clock signal are homologous clock signals.
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