CN106533647A - IOSERDES-based cameralink interface system - Google Patents
IOSERDES-based cameralink interface system Download PDFInfo
- Publication number
- CN106533647A CN106533647A CN201611088523.1A CN201611088523A CN106533647A CN 106533647 A CN106533647 A CN 106533647A CN 201611088523 A CN201611088523 A CN 201611088523A CN 106533647 A CN106533647 A CN 106533647A
- Authority
- CN
- China
- Prior art keywords
- data
- cameralink
- module
- signal
- image
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
- H04N5/765—Interface circuits between an apparatus for recording and another apparatus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0075—Arrangements for synchronising receiver with transmitter with photonic or optical means
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Physics & Mathematics (AREA)
- Computer Networks & Wireless Communication (AREA)
- Theoretical Computer Science (AREA)
- Optics & Photonics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multimedia (AREA)
- Studio Devices (AREA)
Abstract
The invention discloses an IOSERDES-based cameralink interface system. The system realizes a cameralink interface through an FPGA, and comprises a receiving module and a sending module. The receiving module comprises a differential input buffer, an input clock module, serial-parallel conversion modules and an input data logical mapping module. The sending module comprises an output data logical mapping module, parallel-serial conversion modules, an output clock module and a differential output buffer. Cameralink logical functions and physical interfaces are realized through FPGA; through special resources, accuracy of high-speed serial-parallel conversion and parallel-serial conversion can be ensured; all functions of an existing cameralink protocol chip can be replaced; realization of the cameralink interface can be greatly simplified; cost is reduced; and convenient transplantation and maintenance are achieved.
Description
Technical field
The present invention relates to high speed image coffret field, more particularly to a kind of cameralink based on IOSERDES connects
Port system.
Background technology
With various optical camera load widely using on satellite platform, master of the image signal source as remote sensing information
Acquisition modes are wanted, its transmission means and signal quality are the key factors for affecting systematic function.Cameralink interface protocols are
A kind of open agreement that National Semiconductor laboratory is proposed, the physical connector with specification and connection cables, because of its tool
There are good reliability and jamproof ability, make it the primary selection of optical camera payload interface.
The realization major part of cameralink interfaces is come real using controller plus special agreement transceiving chip at present
Existing, the such as DS90CR287/288 of National Semiconductor, its advantage are that dependable performance is stable, and being widely applied of obtaining is tested
Card；Which has the disadvantage to control single DS90CR287/288 needs to consume 30 FPGA pins, the BASE of cameralink interfaces,
MEDIUM, FULL pattern is respectively necessary for 1,2,3 DS90CR287/288, need to consume 30,60,90 FPGA draw
Foot.Multi-disc DS90CR287/288 is consumed in circuit-board laying-out wiring simultaneously space and resource, and optical camera load is little
One of bottleneck of type, even miniaturized design.
With the fast development of FPGA technology, many FPGA pins possess LVDS level standards, are provided simultaneously with digital resistance
Anti- matching feature so that be implemented as based on the cameralink interfaces of FPGA a kind of possible.The present invention proposes one kind and is based on
The cameralink interface realizing methods of IOSERDES, all of logic function and physical interface are all realized by FPGA, are used
The specific resource of FPGA ensure that the correctness of high speed serial parallel exchange and parallel-serial conversion, can substitute existing cameralink
The repertoire of protocol chip, can be configured to tri- kinds of cameralink mode of operations of BASE, MEDIUM, FULL.Can be very big
Simplified cameralink interfaces realization, be easy to transplant and safeguard.
The content of the invention
It is an object of the invention to provide a kind of cameralink interface systems based on IOSERDES, cameralink logics
Function and physical interface all realized by FPGA, ensure that the correct of high speed serial parallel exchange and parallel-serial conversion using specific resource
Property, the repertoire of existing cameralink protocol chips can be substituted, tri- kinds of BASE, MEDIUM, FULL can be configured to
Cameralink mode of operations.The realization of cameralink interfaces can greatly be simplified, reduces cost is easy to transplant and is tieed up
Shield.
In order to realize object above, the present invention is achieved by the following technical solutions：
A kind of cameralink interface systems based on IOSERDES, which passes through FPGA and realizes cameralink interfaces, its
Feature is, comprising：
Described receiver module is included：
Differential Input is cached, for the cameralink physical signallings of LVDS are converted to single-ended signal；
Input clock module, carries out frequency multiplication, sequential alignment and clock about for the cameralink clock signals to being input into
Beam；
Serioparallel exchange module, the serial signal for cameralink interfaces are input into is simultaneously according to sequential and logical transition
Row data；
Input data logical mappings module, for by the parallel data after serioparallel exchange according to the first frame useful signal,
The output of a line useful signal, the first data valid signal and the first data signal；
Described sending module is included：
Output data logical mappings module, for will be the second frame useful signal, the second row useful signal, the second data effective
Signal and the second data signal are organized into the logical order before parallel-serial conversion；
Parallel serial conversion module, for exporting logical transition into serial signal by parallel signal according to cameralink interfaces；
Output clock module, which passes through OSERDES modules and generates cameralink output clocks；
Difference output is cached, and is LVDS physical signallings for cameralink is exported logical transition.
The pin of the input clock module is configured on FPGA global clocks, using the phaselocked loop inside FPGA or numeral
Timer manager enters horizontal phasing control and frequency multiplication to sampling clock, and carries out time constraints to the clock after adjustment, is used for
Serioparallel exchanges of the ISERDES based on rising edge clock.
Described serioparallel exchange module includes several adjacent ISEDES modules, completes the serioparallel exchange of bit, controls
Logic realization first reaches low level of the bit positioned at transformation result, finally reaches the original that bit is located at a high position for transformation result
Then.
Described receiver module is respectively necessary for 1,2,3 serioparallel exchange moulds under BASE, MEDIUM, FULL pattern
Block, in requisition for 4,8,12 ISERDES modules.
After described input data logical mappings module converts parallel data into the gray value of image pixel, will be discrete
Grayvalue transition is the image pixel with logical order.
Described output data logical mappings module is by frame useful signal, row useful signal, data valid signal and data
After signal logic is converted into the permutation and combination of image data pixel values, image data pixel values is further mapped to bit and is patrolled
Volume.
Described parallel serial conversion module includes several adjacent OSEDES modules, realizes that low level is first exported, defeated after a high position
Go out.
Described sending module is respectively necessary for 1,2,3 parallel-serial conversion moulds under BASE, MEDIUM, FULL pattern
Block, in requisition for 4,8,12 OSERDES modules.
Described output clock module carries out parallel-serial conversion using OSERDES modules, carries out time constraints to transformation result,
Export from FPGA global clocks pin clock is exported as cameralink.
The present invention compared with prior art, with advantages below：
(1) transceiver logic of cameralink is realized inside FPGA completely, while FPGA pins have LVDS standards,
Cameralink agreement transceiving chips need not be additionally used, image capture and display system electronics system can be greatly simplified,
Reduces cost so that the integrated level of system is high, small volume is low in energy consumption.
(2) compared with traditional use cameralink agreement transceiving chips, under full patterns, it is only necessary to consume 30 FPGA
Pin resource, is reduced to original 30%, can further improve FPGA resource utilization rate.
(3) in the case where chip need not be increased and decreased, circuit board need not be changed, logical code need only be adjusted, can be realized
BASE, MEDIUM, FULL Three models of cameralink, circuit board upgrading update convenient.
Description of the drawings
Fig. 1 is the block diagram of receiver module of the present invention；
Fig. 2 is the block diagram of sending module of the present invention；
Fig. 3 is the phase adjustment figure of cameralink input clocks of the present invention；
Fig. 4 is receiver module BASE, MEDIUM, FULL Three models schematic diagram of the present invention；
Fig. 5 is the phase controlling figure that cameralink of the present invention exports clock；
Fig. 6 is sending module BASE, MEDIUM, FULL Three models schematic diagram of the present invention.
Specific embodiment
Below in conjunction with accompanying drawing, by describing a preferably specific embodiment in detail, the present invention is further elaborated.
As shown in Figure 1, 2, a kind of cameralink interface systems based on IOSERDES, which is realized by FPGA
Cameralink interfaces, the interface system are included：Receiver module 100 and sending module 200；Described receiver module 100 is included：
Differential Input is cached, for the cameralink physical signallings of LVDS are converted to single-ended signal, using the numeral inside FPGA
Impedance match technique realizes the impedance matching of differential signal；Input clock module, for the cameralink clocks letter to being input into
Number carry out frequency multiplication, sequential alignment and time constraints；Serioparallel exchange module, which passes through ISERDES module control logics, for inciting somebody to action
The serial signal of cameralink interfaces input is parallel data according to sequential and logical transition；Input data logical mappings mould
Block, for by the parallel data after serioparallel exchange according to frame useful signal, row useful signal, data valid signal and data signal
Output；
Above-mentioned sending module 200 is included：Output data logical mappings module, for frame useful signal, row are effectively believed
Number, data valid signal and data signal be organized into the logical order before parallel-serial conversion；Parallel serial conversion module, which passes through
OSERDES module control logics, for exporting logical transition into serial signal by parallel signal according to cameralink interfaces；It is defeated
Go out clock module, which passes through OSERDES modules and generates cameralink output clocks；Difference output is cached, for inciting somebody to action
Cameralink output logical transitions are LVDS physical signallings.
The pin of the input clock module is configured on FPGA global clocks, cameralink input clocks phase place for-
103 °, enter horizontal phasing control to sampling clock to 0 ° using the phaselocked loop inside FPGA or digital dock manager；Its frequency is
The 1/7 of bit frequency, when carrying out frequency multiplication to input using the phaselocked loop inside FPGA or digital dock manager to sampling clock
7 times of clock；Time constraints are carried out to the clock after adjustment, for serioparallel exchanges of the ISERDES based on rising edge clock.
Described serioparallel exchange module includes several adjacent ISEDES modules, completes the serioparallel exchange of bit, controls
Logic realization first reaches low level of the bit positioned at transformation result, finally reaches the original that bit is located at a high position for transformation result
Then, the serioparallel exchange of 28 bits is specially completed using 4 ISERDES modules, and control logic realizes that first reaching bit is located at
The low level of transformation result, the bit for finally reaching are located at the principle of a high position for transformation result.Receiver module BASE,
1,2,3 serioparallel exchange modules are respectively necessary under MEDIUM, FULL pattern, that is, be respectively necessary for 4,8,12
ISERDES modules.It is each adjacent per 4 ISEDES modules by position constraint control, also control mutually each serioparallel exchange module
It is adjacent.
After above-mentioned input data logical mappings module converts parallel data into the gray value of image pixel, will be discrete
Grayvalue transition is the image pixel with logical order, the output of specific incoming serial sequence reference chip DS90CR287
Logic, the result of serioparallel exchange is converted to the gray scale of image pixel according to Camera Link Bit Assignment logics
Value, further according to Camera Link Data Routing for Base, Medium, and Full
Configurations logics are by the image pixel of the discrete certain logical order of grayvalue transition.Final mapping framing is effectively believed
Number, the form of row useful signal, data valid signal and data signal be easy to other image processing modules to use.
Described output data logical mappings module is by frame useful signal, row useful signal, data valid signal and data
After signal logic is converted into the permutation and combination of image data pixel values, image data pixel values is further mapped to bit and is patrolled
Volume, specifically, frame useful signal that other image processing modules are generated, row useful signal, data valid signal sum it is believed that
Number according to Camera Link Data Routing for Base, Medium, and Full Configurations logics turn
Change the permutation and combination of image data pixel values into, then according to Camera Link Bit Assignment logics by each pixel
Gray value is further mapped to bit logic, and the input logic of final reference DS90CR288 is mapped to the logic before parallel-serial conversion.
Described parallel serial conversion module includes several adjacent OSEDES modules, realizes that low level is first exported, defeated after a high position
Go out, specifically export primary frequency and the 7 frequency multiplication FREQUENCY CONTROL parallel-serial conversions of clock, every 28 bit consumption 4 according to cameralink
Individual OSERDES, control logic realize that low level is first exported, and export after a high position.Sending module is under BASE, MEDIUM, FULL pattern
1,2,3 output data parallel serial conversion modules are respectively necessary for, that is, are respectively necessary for 4,8,12 OSERDES modules.It is logical
Cross position constraint control it is each adjacent per 4 OSERDES modules, also controlled output data parallel serial conversion module is adjacent.
Above-mentioned output clock module carries out parallel-serial conversion using OSERDES modules, carries out time constraints to transformation result,
Export from FPGA global clocks pin and clock is exported as cameralink, i.e., export the primary frequency of clock according to cameralink
With 7 frequency multiplication FREQUENCY CONTROL parallel-serial conversion clocks, parallel-serial conversion is carried out to " 110011 " sequence using OSERDES modules, to output
As a result time constraints are carried out, is exported from global clock pin, clock is exported as cameralink.
Please refer to Fig. 3～6, embodiments of the present invention are specifically addressed：
The image way of output of hypothesis optics load camera is 8tap*8bit, with the FULL patterns of cameralink interfaces
As a example by, specific receiver module embodiment is described below：
1. LVDS pin input impedances are set to into 100 Ω using the digital impedance matching technique (DCM) inside FPGA；Will
12 couples of LVDS data signals (rx_X_p (n) [3 of optics load camera cameralink FULL outputs:0]、rx_Y_p(n)[3:
0]、rx_Z_p(n)[3:0] 12 single-ended signal (rx [3 are converted into by the IBUFDS inside FPGA):0]、ry[3:0]、rz
[3:0])；3 pairs of LVDS clock signals (rx_CLKX_p (n), rx_CLKY_p (n), rx_CLKZ_p (n)) are turned by IBUFGDS
Change 3 single-ended signals (clk_rx, clk_ry, clk_rz) into.
2. 7 frequencys multiplication are carried out to clk_rx using the digital dock manager inside FPGA and obtain clk_rx_x7, to clk_rx
Carry out 103 ° of Phase delay and obtain clk_rx_phase, the clock after adjustment carries out time constraints, referring to Fig. 1.
3. 3 serioparallel exchange modules are adopted, and the string that each serioparallel exchange module completes 28 bits using 4 ISERDES is simultaneously
Conversion.It is each adjacent per 4 ISEDES modules by position constraint control, also control mutually each input data serioparallel exchange module
It is adjacent, referring to Fig. 2.According to the low level that bit is located at transformation result is first reached, the bit for finally reaching is located at transformation result
The principle of a high position result of serioparallel exchange is adjusted.
Assume first group of 4 ISERDES serioparallel exchange result be Qx3 [6:0]、Qx2[6:0]、Qx1[6:0]、Qx0[6:
0], the serioparallel exchange result of 28 bits is adjusted to：
rx_data[27:0]={ Qx3 [0:6],Qx2[0:6],Qx1[0:6],Qx0[0:6]}；
The result for assuming second group of 4 ISERDES each serioparallel exchange is Qy3 [6:0]、Qy2[6:0]、Qy1[6:0]、
Qy0[6:0], the serioparallel exchange result of 28 bits is adjusted to：
ry_data[27:0]={ Qy3 [0:6],Qy2[0:6],Qy1[0:6],Qy0[0:6]}；
The result for assuming the 3rd group of 4 ISERDES each serioparallel exchanges is Qz3 [7:0]、Qz2[6:0]、Qz1[6:0]、
Qz0[6:0], the serioparallel exchange result of 28 bits is adjusted to：
rz_data[27:0]={ Qz3 [0:6],Qz2[0:6],Qz1[0:6],Qz0[0:6]}；
4. pair input data logical mappings obtain frame useful signal rx_f_valid, row useful signal rx_l_valid, number
According to useful signal rx_d_valid and data rx_image_data [63:0] result of signal is：
F_valid=rx_data [15]；
L_valid=rx_data [16]；
D_valid=rx_data [14]；
rx_image_data[63:0]=
{rz_data[24],rz_data[25],rz_data[9],rz_data[10],rz_data[11],rz_data
[12],rz_data[13],rz_data[0],
rz_data[26],rz_data[27],rz_data[1],rz_data[2],rz_data[3],rz_data[4],
rz_data[5],rz_data[6],
ry_data[22],ry_data[23],ry_data[17],ry_data[18],ry_data[19],ry_data
[20],ry_data[7],ry_data[8],
ry_data[24],ry_data[25],ry_data[9],ry_data[10],ry_data[11],ry_data
[12],ry_data[13],ry_data[0],
ry_data[26],ry_data[27],ry_data[1],ry_data[2],ry_data[3],ry_data[4],
ry_data[5],ry_data[6],
rx_data[22],rx_data[23],rx_data[17],rx_data[18],rx_data[19],rx_data
[20],rx_data[7],rx_data[8],
rx_data[24],rx_data[25],rx_data[9],rx_data[10],rx_data[11],rx_data
[12],rx_data[13],rx_data[0],
rx_data[26],rx_data[27],rx_data[1],rx_data[2],rx_data[3],rx_data[4],
rx_data[5],rx_data[6]
}；
By taking the FULL patterns of cameralink interfaces as an example, specifically introduced such as based on FPGA sending modules embodiment
Under.
1. pair output data carries out logical mappings, it is assumed that signal to be output is frame useful signal tx_f_valid, row has
Effect signal tx_l_valid, data valid signal tx_d_valid and data tx_image_data [63:0], by these signals point
It is fitted on tx_data [27:0]、ty_data[27:0]、tz_data[27:0].
tx_data[27:0]=
{tx_image_data[6],tx_image_data[7],tx_image_data[14],tx_image_data
[15],tx_image_data[22],tx_image_data[23],1’b0,
tx_image_data[18],tx_image_data[19],tx_image_data[20],tx_image_data
[21],tx_d_valid,tx_f_valid,tx_l_valid,
tx_image_data[9],tx_image_data[10],tx_image_data[11],tx_image_data
[12],tx_image_data[13],tx_image_data[16],tx_image_data[17],
tx_image_data[0],tx_image_data[1],tx_image_data[2],tx_image_data[3],
tx_image_data[4],tx_image_data[5],tx_image_data[8]}；
ty_data[27:0]=
{tx_image_data[30],tx_image_data[31],tx_image_data[38],tx_image_data
[39],tx_image_data[46],tx_image_data[47],1’b0,
tx_image_data[42],tx_image_data[43],tx_image_data[44],tx_image_data
[45],tx_d_valid,tx_f_valid,tx_l_valid,
tx_image_data[33],tx_image_data[34],tx_image_data[35],tx_image_data
[36],tx_image_data[37],tx_image_data[40],tx_image_data[41],
tx_image_data[24],tx_image_data[25],tx_image_data[26],tx_image_data
[27],tx_image_data[28],tx_image_data[29],tx_image_data[32],}；
tz_data[27:0]=
{tx_image_data[54],tx_image_data[55],tx_image_data[62],tx_image_data
[63],3’b0,
4’b0,tx_d_valid,tx_f_valid,tx_l_valid,
tx_image_data[57],tx_image_data[58],tx_image_data[59],tx_image_data
[60],tx_image_data[61],2’b0
tx_image_data[48],tx_image_data[49],tx_image_data[50],tx_image_data
[51],tx_image_data[52],tx_image_data[53],tx_image_data[56]}；
2. adopt 3 output data parallel serial conversion modules, each input data serioparallel exchange module to adopt 4 OSERDES
Complete the parallel-serial conversion of 28 bits.It is each adjacent per 4 OSERDES modules by position constraint control, also control each output
Data parallel serial conversion module is adjacent, referring to Fig. 4.
Above-mentioned tx_data [27:0] 4 OSERDES are needed to carry out parallel-serial conversion, input is respectively Dx3 [6:0]、Dx2
[6:0]、Dx1[6:0]、Dx0[6:0], it is output as tx [3:0], then have：
Dx3[6:0]=tx_data [21:27]；Dx2[6:0]=tx_data [14:20]；Dx1[6:0]=tx_data
[7:13]；Dx0[6:0]=tx_data [0:6]；
Above-mentioned ty_data [27:0] 4 OSERDES are needed to carry out parallel-serial conversion, input is respectively Dy3 [6:0]、Dy2
[6:0]、Dy1[6:0]、Dy0[6:0], it is output as ty [3:0], then have：
Dy3[6:0]=ty_data [21:27]；Dy2[6:0]=ty_data [14:20]；Dy1[6:0]=ty_data
[7:13]；Dy0[6:0]=ty_data [0:6]；
Above-mentioned tz_data [27:0] 4 OSERDES are needed to carry out parallel-serial conversion, input is respectively Dz3 [6:0]、Dz2
[6:0]、Dz1[6:0]、Dz0[6:0], it is output as tz [3:0], then have：
Dz3[6:0]=tz_data [21:27]；Dz2[6:0]=tz_data [14:20]；Dz1[6:0]=tz_data
[7:13]；Dz0[6:0]=tz_data [0:6]；
3. the primary frequency and 7 frequency multiplication FREQUENCY CONTROL parallel-serial conversion clocks of clock is exported according to cameralink, is utilized
OSERDES modules carry out parallel-serial conversion to " 110011 " sequence, carry out time constraints to output result, defeated from global clock pin
Go out, clock tx_clk is exported as cameralink, referring to Fig. 3.
4. OBUFDS is utilized by tx [3:0]、ty[3:0]、tz[3:0] be converted to the physical signalling tx_X_p of LVDS standards
(n)[3:0]、tx_Y_p(n)[3:0]、tx_Z_p(n)[3:0], tx_clk is converted to into LVDS physical signallings using OBUFDG
Tx_CLKX_p (n), tx_CLKY_p (n), tx_CLKZ_p (n), the collection that these signals can directly with cameralink interfaces
Card docking.
In sum, an a kind of Cameralink Interface for System based on IOSERDES of the invention, is realized by FPGA,
The correctness of high speed serial parallel exchange and parallel-serial conversion be ensure that using the specific resource of FPGA, can be substituted existing
The repertoire of cameralink protocol chips, can be configured to tri- kinds of mode of operations of BASE, MEDIUM, FULL, consume respectively
10,20,30 have LVDS function FPGA pins.
It is although present disclosure has been made to be discussed in detail by above preferred embodiment, but it should be appreciated that above-mentioned
Description is not considered as limitation of the present invention.After those skilled in the art have read the above, for the present invention's
Various modifications and substitutions all will be apparent.Therefore, protection scope of the present invention should be limited to the appended claims.
Claims (9)
1. a kind of cameralink interface systems based on IOSERDES, which passes through FPGA and realizes cameralink interfaces, and which is special
Levy and be, comprising：
Described receiver module is included：
Differential Input is cached, for the cameralink physical signallings of LVDS are converted to single-ended signal；
Input clock module, carries out frequency multiplication, sequential alignment and time constraints for the cameralink clock signals to being input into；
Serioparallel exchange module, the serial signal for cameralink interfaces are input into is simultaneously line number according to sequential and logical transition
According to；
Input data logical mappings module, for by the parallel data after serioparallel exchange according to the first frame useful signal, the first row
The output of useful signal, the first data valid signal and the first data signal；
Described sending module is included：
Output data logical mappings module, for by the second frame useful signal, the second row useful signal, the second data valid signal
The logical order before parallel-serial conversion is organized into the second data signal；
Parallel serial conversion module, for exporting logical transition into serial signal by parallel signal according to cameralink interfaces；
Output clock module, which passes through OSERDES modules and generates cameralink output clocks；
Difference output is cached, and is LVDS physical signallings for cameralink is exported logical transition.
2. cameralink interface systems based on IOSERDES as claimed in claim 1, it is characterised in that configuration is described defeated
Enter the pin of clock module on FPGA global clocks, using the phaselocked loop inside FPGA or digital dock manager to sampling
Clock enters horizontal phasing control and frequency multiplication, and carries out time constraints to the clock after adjustment, is based on rising edge clock for ISERDES
Serioparallel exchange.
3. cameralink interface systems based on IOSERDES as claimed in claim 2, it is characterised in that described string is simultaneously
Modular converter includes several adjacent ISEDES modules, completes the serioparallel exchange of bit, and control logic is realized first reaching bit
Position is located at the low level of transformation result, finally reaches the principle that bit is located at a high position for transformation result.
4. cameralink interface systems based on IOSERDES as claimed in claim 3, it is characterised in that described reception
Module is respectively necessary for 1,2,3 serioparallel exchange modules under BASE, MEDIUM, FULL pattern, in requisition for 4,8,
12 ISERDES modules.
5. cameralink interface systems based on IOSERDES as claimed in claim 1, it is characterised in that described input
After mathematical logic mapping block converts parallel data into the gray value of image pixel, it is with patrolling by discrete grayvalue transition
Collect the image pixel of order.
6. cameralink interface systems based on IOSERDES as claimed in claim 1, it is characterised in that described output
Mathematical logic mapping block is by frame useful signal, row useful signal, data valid signal and data signal logical transition into image
After the permutation and combination of data pixel values, image data pixel values are further mapped to bit logic.
7. cameralink interface systems based on IOSERDES as claimed in claim 1, it is characterised in that described and go here and there
Modular converter includes several adjacent OSEDES modules, realizes that low level is first exported, and exports after a high position.
8. cameralink interface systems based on IOSERDES as claimed in claim 1, it is characterised in that described transmission
Module is respectively necessary for 1,2,3 parallel serial conversion modules under BASE, MEDIUM, FULL pattern, in requisition for 4,8,
12 OSERDES modules.
9. cameralink interface systems based on IOSERDES as claimed in claim 1, it is characterised in that described output
Clock module carries out parallel-serial conversion using OSERDES modules, carries out time constraints to transformation result, from FPGA global clock pins
Output exports clock as cameralink.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611088523.1A CN106533647A (en) | 2016-11-30 | 2016-11-30 | IOSERDES-based cameralink interface system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611088523.1A CN106533647A (en) | 2016-11-30 | 2016-11-30 | IOSERDES-based cameralink interface system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106533647A true CN106533647A (en) | 2017-03-22 |
Family
ID=58354199
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611088523.1A Pending CN106533647A (en) | 2016-11-30 | 2016-11-30 | IOSERDES-based cameralink interface system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106533647A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107249101A (en) * | 2017-07-13 | 2017-10-13 | 浙江工业大学 | A kind of sample of high-resolution image and processing unit |
| CN108924459A (en) * | 2018-08-06 | 2018-11-30 | 上海顺久电子科技有限公司 | A kind of output interface circuit and device |
| CN109587411A (en) * | 2018-11-08 | 2019-04-05 | 中国航空工业集团公司洛阳电光设备研究所 | A kind of serial Camera Link coding method of FPGA driving |
| CN110515890A (en) * | 2019-08-02 | 2019-11-29 | 北京智行者科技有限公司 | The data analysis method and system of multiprocessor systems on chips MPSOC |
| CN111314645A (en) * | 2020-02-24 | 2020-06-19 | 南京理工大学 | Camera Link interface signal decoding method based on FPGA |
| CN112433975A (en) * | 2020-11-20 | 2021-03-02 | 中国航空工业集团公司洛阳电光设备研究所 | Camera Link data sending system based on FPGA |
| CN114442514A (en) * | 2020-11-02 | 2022-05-06 | 芯启源(上海)半导体科技有限公司 | USB3.0/3.1 control system based on FPGA |
| CN115061967A (en) * | 2022-06-30 | 2022-09-16 | 重庆秦嵩科技有限公司 | Method for reducing interface clock by using homemade FPGA (field programmable Gate array) based camera link image compression |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101312510A (en) * | 2008-05-29 | 2008-11-26 | 北京创毅视讯科技有限公司 | Modulation data conversion unit and modulation data conversion method |
| CN102064886A (en) * | 2010-11-03 | 2011-05-18 | 中国科学院长春光学精密机械与物理研究所 | Camera interface full-mode fiber transmission system |
| CN104113740A (en) * | 2014-07-28 | 2014-10-22 | 中国科学院光电技术研究所 | Mixed format signal optical fiber transmission device |
| CN104581095A (en) * | 2014-12-26 | 2015-04-29 | 北京航天控制仪器研究所 | Camera Link video optical transceiver |
-
2016
- 2016-11-30 CN CN201611088523.1A patent/CN106533647A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101312510A (en) * | 2008-05-29 | 2008-11-26 | 北京创毅视讯科技有限公司 | Modulation data conversion unit and modulation data conversion method |
| CN102064886A (en) * | 2010-11-03 | 2011-05-18 | 中国科学院长春光学精密机械与物理研究所 | Camera interface full-mode fiber transmission system |
| CN104113740A (en) * | 2014-07-28 | 2014-10-22 | 中国科学院光电技术研究所 | Mixed format signal optical fiber transmission device |
| CN104581095A (en) * | 2014-12-26 | 2015-04-29 | 北京航天控制仪器研究所 | Camera Link video optical transceiver |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107249101A (en) * | 2017-07-13 | 2017-10-13 | 浙江工业大学 | A kind of sample of high-resolution image and processing unit |
| CN107249101B (en) * | 2017-07-13 | 2020-01-10 | 浙江工业大学 | High-resolution image acquisition and processing device |
| CN108924459A (en) * | 2018-08-06 | 2018-11-30 | 上海顺久电子科技有限公司 | A kind of output interface circuit and device |
| CN108924459B (en) * | 2018-08-06 | 2021-04-13 | 上海顺久电子科技有限公司 | Output interface circuit and device |
| CN109587411A (en) * | 2018-11-08 | 2019-04-05 | 中国航空工业集团公司洛阳电光设备研究所 | A kind of serial Camera Link coding method of FPGA driving |
| CN110515890A (en) * | 2019-08-02 | 2019-11-29 | 北京智行者科技有限公司 | The data analysis method and system of multiprocessor systems on chips MPSOC |
| CN111314645A (en) * | 2020-02-24 | 2020-06-19 | 南京理工大学 | Camera Link interface signal decoding method based on FPGA |
| CN114442514A (en) * | 2020-11-02 | 2022-05-06 | 芯启源(上海)半导体科技有限公司 | USB3.0/3.1 control system based on FPGA |
| CN114442514B (en) * | 2020-11-02 | 2024-05-14 | 芯启源(上海)半导体科技有限公司 | USB3.0/3.1 control system based on FPGA |
| CN112433975A (en) * | 2020-11-20 | 2021-03-02 | 中国航空工业集团公司洛阳电光设备研究所 | Camera Link data sending system based on FPGA |
| CN115061967A (en) * | 2022-06-30 | 2022-09-16 | 重庆秦嵩科技有限公司 | Method for reducing interface clock by using homemade FPGA (field programmable Gate array) based camera link image compression |
| CN115061967B (en) * | 2022-06-30 | 2023-06-23 | 重庆秦嵩科技有限公司 | Method for reducing interface clock by adopting camera link image compression based on domestic FPGA |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106533647A (en) | IOSERDES-based cameralink interface system | |
| CN102457285B (en) | The communication interface of the calibration for multiple parallel data communication line roads and method | |
| CN105141877B (en) | A kind of chromacoder based on programming device | |
| CN104022828B (en) | A kind of optical fiber data transmission method based on asynchronous communication model | |
| CN108683536B (en) | Configurable dual-mode converged communication method of asynchronous network on chip and interface thereof | |
| CN203224621U (en) | Weather radar high-speed data transmission device based on PCI-E bus | |
| US20080084862A1 (en) | Apparatus and method for data processing having an on-chip or off-chip interconnect between two or more devices | |
| US8135872B2 (en) | USB controller and a testing method of the USB controller | |
| CN101951313A (en) | FPGA-based SFI4.1 device | |
| CN208013943U (en) | A kind of spaceborne high-resolution imaging data transmission and acquisition system | |
| CN107171728A (en) | 1B4B and the forward direction of Manchester's code, reverse transfer method and device, system | |
| CN101923840A (en) | High-capacity and ultra high-speed image digital signal generator based on programmable logic device | |
| JPH09307562A (en) | Optical network equipment | |
| CN109491940A (en) | A kind of conversion circuit and conversion method of TLK2711 coffret and USB3.0 coffret | |
| CN209312015U (en) | A kind of conversion circuit of TLK2711 coffret and USB3.0 coffret | |
| CN103676743A (en) | Remote control and master control communication interface | |
| CN113033087B (en) | High-speed data transmission method for optical neural network based on FPGA | |
| CN103426402A (en) | LED (light-emitting diode) display system, display module thereof and data transmission method | |
| CN102780598A (en) | Bus communication method, bus communication unit and bus communication system | |
| WO2019096128A1 (en) | Double-edge-triggered circular buffer and communication system | |
| CN112468162B (en) | Dual-generation tera-network intermediate-frequency signal processor, dual-path system and data transmission method | |
| CN111124982B (en) | Asynchronous clock data synchronous circuit | |
| CN113535619A (en) | High-speed serial interface for satellite based on Virtex-5 series FPGA and TLK2711 | |
| CN114756498A (en) | Chip, master control chip, chip communication method, chip array and related equipment | |
| CN113258941B (en) | Vector signal generation module and method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20170322 |
|
| RJ01 | Rejection of invention patent application after publication |