CN102780598A - Bus communication method, bus communication unit and bus communication system - Google Patents
Bus communication method, bus communication unit and bus communication system Download PDFInfo
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- CN102780598A CN102780598A CN2012102524619A CN201210252461A CN102780598A CN 102780598 A CN102780598 A CN 102780598A CN 2012102524619 A CN2012102524619 A CN 2012102524619A CN 201210252461 A CN201210252461 A CN 201210252461A CN 102780598 A CN102780598 A CN 102780598A
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Abstract
The invention discloses a bus communication method, a bus communication unit and a bus communication system, wherein the bus communication method comprises the steps that information to be transmitted of a unit on the end is converted into one or more data segments, each data segment consists of N bits, wherein N is not less than 1, the information to be transmitted includes address information, data information and control information, or the information to be transmitted includes address information and control information; and various data segments are transmitted to a unit on an opposite end by a data bus with a bit width as N. By adopting the technical scheme, the problem that fewer and fewer pins are reserved for a low-speed interface because the interface pins are insufficient when two communication units are communicated via a bus in the prior art is solved.
Description
Technical field
The present invention relates to the communications field, relate in particular to a kind of bus communication, bus communication unit and system.
Background technology
Along with integrated circuit technique and development of internet technology, (motherboard is like mainboard to interconnected between plate, motherboard and subcard; Subcard is the expansion of motherboard with respect to motherboard, links to each other with motherboard through connector, all belongs to subcard such as the network interface card and the video card that are inserted on the computer main board) interconnected bandwidth requirement is increasingly high.It is also more and more wider that high-speed serial bus is used, as 10 Gigabit Ethernet Attachment Unit Interface XAUI bus, packet interconnection protocol Interlaken bus of new generation etc. increasing be applied to interconnected between plate, motherboard and subcard interconnected.Because it is very high that high speed serialization link requires signal integrity, along with high speed serialization link quantity increases, the pin number that is used for interconnected between plate, motherboard and the interconnected high speed connector of subcard and is the low-speed interface reservation is fewer and feweri.But central processing unit (CPU) EBI is must be indispensable as the first-selected interface of configuration feature sometimes, has so just produced contradiction.
The prior art scheme that solves above-mentioned contradiction mainly contains following several kinds: 1) increase connector quantity.This kind scheme is applicable to veneer or the subcard design that arrangement space is more abundant; Veneer or this scheme of subcard for some layouts are at full stretch are inapplicable; And along with the increase of veneer, subcard design complexities, the scheme that increases connector quantity has received greatly restriction.2) reduce high speed serialization link quantity, improve high speed serialization link speed.Raising along with high speed serialization link speed; Require also increasingly high to high speed serialization link track lengths, connector selection, the selection of pcb board material, the processing of via hole stub etc.; Receiving also must the corresponding high speed serialization link speed of support with sending device, and these have increased considerably the cost of veneer, subcard.3) adopt the PCIE bus to substitute cpu bus.The use of this kind scheme has certain limitation, and the device that requires to be visited is supported the PCIE EBI, yet what most ground device adopted at present is cpu bus interface.4) use iic bus.Because of iic bus speed is low, the use of this kind scheme has certain limitation.5) parallel bus serialization.Parallel bus is changed into universal serial bus, and this kind scheme logical process is complicated, and is high to the requirement of PCB cabling, and in order to guarantee bandwidth, also requires the speed of universal serial bus higher.
Summary of the invention
The present invention provides a kind of bus communication, bus communication unit and system, solves when two communication units utilize bus to communicate in the prior art, and interface pin is not enough, is the pin number problem less and less of low-speed interface reservation.
For solving the problems of the technologies described above, the present invention takes following technical scheme.
A kind of bus communication comprises: this end unit information translation waiting for transmission is become one or more data segments, and each data segment is made up of N bit, wherein N >=1; Said information waiting for transmission comprises address information, data message and control information, and perhaps said information waiting for transmission comprises address information and control information; Is that the data/address bus of N is passed to end unit with each data segment through bit wide.
In an embodiment of the present invention, bus communication also comprises: through said bit wide is the said response message to end unit feedback data section form of data/address bus reception of N, and converts the response message of said data segment form to corresponding data information.
In an embodiment of the present invention, become the method for one or more data segments to be specially this end unit information translation waiting for transmission: earlier this end unit various information waiting for transmission are merged, the information after being combined is carried out the data segment conversion; Perhaps this end unit various information waiting for transmission are carried out the data segment conversion respectively.
In an embodiment of the present invention, this end unit various information waiting for transmission are carried out respectively in the process of data segment conversion: convert control information waiting for transmission to 1 data segment.
In an embodiment of the present invention, said control information comprises chip selection signal, read signal and/or write signal.
In an embodiment of the present invention, said data segment is the byte of being made up of 8 bits.
In an embodiment of the present invention; Is that the data/address bus of N is passed to before the end unit with each data segment through bit wide; Also comprise: data segment is formed one or more Frames, is that the data/address bus of N is passed to end unit with each data segment in each Frame through bit wide.
A kind of bus communication unit comprises data segment modular converter and interface module, and wherein, said data segment modular converter is used for information translation waiting for transmission is become one or more data segments, and each data segment is made up of N bit, wherein N >=1; Said information waiting for transmission comprises address information, data message and control information, and perhaps said information waiting for transmission comprises address information and control information; It is that the data/address bus of N is passed to end unit through bit wide that said interface module is used for each data segment.
In an embodiment of the present invention, also to be used for through said bit wide be that the data/address bus of N receives said response message to end unit feedback data section form to said interface module; Said data segment modular converter also is used for converting the response message of said data segment form to corresponding data information.
In an embodiment of the present invention, said data segment modular converter comprises the merging module and the first sub-modular converter; Said merging module is used for earlier various information waiting for transmission being merged; Information after the said first sub-modular converter is used to be combined is carried out the data segment conversion; Perhaps said data segment modular converter comprises the second sub-modular converter, is used for various information waiting for transmission are carried out the data segment conversion respectively.
In an embodiment of the present invention, said bus communication unit also comprises the framing module, is used for data segment is formed one or more Frames; It is that the data/address bus of N is passed to end unit through bit wide that said interface module is used for each data segment of each Frame.
A kind of bus communication system comprises that through bit wide be this end unit of communicating of the data/address bus of N and to end unit, and wherein, said end unit is above-mentioned each described bus communication unit; Said end unit is used for through said bit wide is the data segment of said the end unit transmission of data/address bus reception of N, and restores corresponding address information, data message and control information by the data segment that receives.
In an embodiment of the present invention, said end unit also is used for generating response message according to the data message that restores; Convert said response message to one or more data segment, each data segment is made up of N bit, wherein N >=1; Is that the data/address bus of N feeds back to said end unit with each data segment through said bit wide.
The invention has the beneficial effects as follows: bus communication provided by the invention, bus communication unit and system; Relying on bit wide is the data/address bus of N; Just can this end unit information waiting for transmission be passed to end unit, this end unit need be when writing data to end unit, and this end unit information waiting for transmission comprises address information, data message and control information; This end unit need be from the opposite end during unit reads data, and this end unit information waiting for transmission comprises address information and control information.In prior art; Between the double bus communication unit; Use the scheme of the control bus transmitting control information of the address bus transmission address information of corresponding bit wide, the data/address bus transfer data information of using corresponding bit wide, the corresponding bit wide of use, can significantly reduce interface pin.
Description of drawings
Fig. 1 a is the data segment that provides of an one embodiment of the invention and data/address bus sketch map one to one;
Fig. 1 b is the data segment that provides of an another embodiment of the present invention and data/address bus sketch map one to one;
Fig. 1 c is the data segment that provides of an another embodiment of the present invention and data/address bus sketch map one to one;
The sketch map of the bus communication system that Fig. 2 provides for one embodiment of the invention;
Fig. 3 is the sketch map of bus communication system in the prior art;
The sketch map of the bus communication system that Fig. 4 provides for another embodiment of the present invention.
Embodiment
Main design of the present invention is: when this end unit need be when writing data to end unit; This end unit is with address information waiting for transmission (address information of data message), data message (comprising the information that need write) and control information (in such cases; Control information comprises write signal, perhaps comprises chip selection signal and write signal) convert M1 data segment to, each data segment is made up of N bit; N >=1 wherein, M1 >=1; Be that the data/address bus of N is passed to end unit with each data segment through bit wide again; Because each data segment is made up of N bit; Once transmit a data segment so bit wide is the data/address bus of N, just can this M1 data segment be passed to end unit through M1 time; End unit is received after M1 the data segment of this end unit transmission, resolve according to corresponding resolution rules, restore address information, data message and control information, the write signal according in the control information writes corresponding devices with data message.
When this end unit need be from the opposite end during unit reads data, (in such cases, control information comprises read signal to this end unit with address information waiting for transmission and control information; Perhaps comprise chip selection signal and read signal) convert M2 data segment to, each data segment is made up of N bit, N >=1 wherein, M2 >=1; Be that the data/address bus of N is passed to end unit with each data segment through bit wide again, bit wide is that the data/address bus of N once transmits a data segment, just can this M2 data segment be passed to end unit through M2 time; End unit is received after M2 the data segment of this end unit transmission, resolve, restore address information and control information according to corresponding resolution rules; According to the read signal in the control information; Produce corresponding response message (reading the result), and convert this response message to M3 data segment according to the transformation rule identical with this end unit, each data segment is made up of N bit equally; M3 >=1; Is that the data/address bus of N feeds back to this end unit with each data segment through this bit wide, and bit wide is that the data/address bus of N once transmits a data segment, just can this M3 data segment be passed to this end unit through M3 time; This end unit is after the data/address bus of N receives the response message of data segment form through this bit wide, resolves according to resolution rules correspondingly, restores the response message that end unit is fed back.This end unit specifically can be main veneer, correspondingly, can be from veneer to end unit, and the local terminal unit further is female card, correspondingly, can be subcard to end unit.
This end unit or be the data/address bus of N when transmitting with each data segment through bit wide to end unit, bit wide N is corresponding with the bit number N that forms data segment, and each bit of data segment and bit wide are that each circuit of data/address bus of N is man-to-man corresponding relation.In order can detailed description to concern one to one; Suppose N=8; Be that data segment is made up of 8 bits; This end unit and also be 8 so to the bit wide of the data/address bus that is used to transmit data segment between the end unit; Represent 8 bits of data segment with position 0, position 1, position 2, position 3, position 4, position 5, position 6, position 7, use L0, L1, L2, L3, L4, L5, L6, L7 to represent that bit wide is 8 data/address bus, each bit of data segment can be corresponding one by one according to the order of high low level with data bus line; Shown in Fig. 1 a, the position is 0 corresponding with L0, the position is 1 corresponding with L1, the position is 2 corresponding with L2,3 corresponding with L3,4 corresponding with L4,5 corresponding with L5,6 corresponding with L6,7 corresponding with L7.Each bit of data segment can be corresponding one by one according to the order of height bit interleave with data bus line; Shown in Fig. 1 b; With the corresponding reversed in order of Fig. 1 a, the position is 0 corresponding with L7, the position is 1 corresponding with L6, the position is 2 corresponding with L5,3 corresponding with L4,4 corresponding with L3,5 corresponding with L2,6 corresponding with L1,7 corresponding with L0.Also can be the corresponding one by one of random order, shown in Fig. 1 c, the position be 0 corresponding with L1, the position is 1 corresponding with L6, the position is 2 corresponding with L2,3 corresponding with L4,4 corresponding with L7,5 corresponding with L3,6 corresponding with L5,7 corresponding with road L0.
In order to guarantee to the correct sampled data of end unit; This end unit and to also transmitting clock signal (like clock signal between clock signal between plate, card) between the end unit, when the needs transmit clock signal, can be with the sampled data of clock signal also as control information; After carrying out data segment conversion in the lump with other address informations, data message, control information; Through bit wide is that the data/address bus of N sends, and end unit to parsing after this sampled data, is restored clock signal.Consider from signal quality; Clock signal also can take a bit clock signal line separately and transmit at this end unit and between to end unit; If select this transfer mode; Then this end unit and to being the data/address bus of N except needing bit wide between the end unit also needs a bit clock signal line, is used to transmit clock signal.
This end unit, opposite end unit further are formed one or more Frames with the data segment that converts to; Is that the data/address bus of N transmits with each data segment in each Frame through bit wide, in such cases, and this end unit and to also transmitting frame signal between the end unit; Frame signal also can be used as control information; After carrying out the data segment conversion in the lump, be the data/address bus transmission of N, also can take a frame signal line separately and transmit through bit wide; If select the latter; Then this end unit and to being the data/address bus of N except needing bit wide between the end unit also needs a frame signal line, is used to transmit frame signal.Further, chip selection signal can lie in this frame signal, only need transmit read signal and/or write signal in the control information.
As shown in Figure 2, the sketch map of the bus communication system that provides for one embodiment of the invention, this bus communication system comprise this end unit 1 and to end unit 2.This end unit 1 comprises the first data segment modular converter 11 and first interface module 12, and is corresponding, and end unit 2 is comprised the second data segment modular converter 21 and second interface module 22.First interface module 12, second interface module 22 can be interconnected between plate for being used for, motherboard and the interconnected connector of subcard, in such cases, are that the data/address bus of N connects through bit wide directly between first interface module 12 and second interface module 22; Perhaps first interface module 12, second interface module 22 can also be AUI, this AUI be used for interconnected between plate, motherboard and be connected with the interconnected connector of subcard, the pin through connector connects the data/address bus that bit wide is N indirectly.The first data segment modular converter 11 and first interface module 12 can be integrated into a total module, and the second data segment modular converter 21 and second interface module 22 can be integrated into a total module.In the present embodiment; This end unit and the clock signal between the end unit (like clock signal between clock signal between plate, card) is taken a bit clock signal line separately transmit; Therefore; Be the data/address bus of N except needing bit wide between first interface module 12, second interface module 22, also need a bit clock signal line, be used to transmit clock signal.
If this end unit 1 need be to end unit 2 is write data; Then the first data segment modular converter 11 is used for converting this end unit 1 address information waiting for transmission, data message (comprising the information that need write) and control information (comprising chip selection signal and write signal) to M1 data segment; Each data segment is made up of N bit; N >=1 wherein, M1 >=1; Address information waiting for transmission, data message and control information can be generated by the first data segment modular converter 11; Also can be generated by a processing module of establishing in addition in this end unit 1, this processing module and/or the first data segment modular converter 11 can be integrated on the CPU in this end unit 1.The first data segment modular converter 11 converts this end unit 1 address information waiting for transmission, data message and control information after M1 the data segment to, and each data segment is transferred to first interface module 12 respectively; It is that the data/address bus of N is passed to second interface module 22 to end unit 2 through bit wide that first interface module 12 is used for each data segment.Because a data segment is made up of N bit, so being the data/address bus of N, bit wide once transmits a data segment, through M1 time M1 data segment is passed to second interface module 22.Second interface module 22 whenever receives after the data segment; Pass to the second data segment modular converter 21; The second data segment modular converter 21 is waited to collect after this M1 data segment, resolves according to corresponding resolution rules, restores address information, data message and control information; The second data segment modular converter 21 or to the processing module of establishing in addition in the end unit 2 according to the write signal in the control information, data message is write corresponding devices.
If this end unit 1 need be to end unit 2 reading of data; Then the first data segment modular converter 11 is used for converting this end unit 1 address information waiting for transmission and control information (comprising chip selection signal and read signal) to M2 data segment; Each data segment is made up of N bit, N >=1 wherein, M2 >=1; Address information waiting for transmission and control information can be generated by the first data segment modular converter 11; Also can be generated by a processing module of establishing in addition in this end unit 1, this processing module and/or the first data segment modular converter 11 can be integrated on the CPU in this end unit 1.The first data segment modular converter 11 converts this end unit 1 address information waiting for transmission and control information after M2 the data segment to, and each data segment is transferred to first interface module 12 respectively; It is that the data/address bus of N is passed to second interface module 22 to end unit 2 through bit wide that first interface module 12 is used for each data segment.Because a data segment is made up of N bit, so being the data/address bus of N, bit wide once transmits a data segment, through M2 time M2 data segment is passed to second interface module 22.Second interface module 22 whenever receives after the data segment; Pass to the second data segment modular converter 21; The second data segment modular converter 21 is waited to collect after this M2 data segment, resolves according to corresponding resolution rules, restores address information and control information; The second data segment modular converter 21 produces response message according to the read signal in the control information; Perhaps the second data segment modular converter 21 is used for this read signal is passed to the processing module to establishing in addition in the end unit 2, produces response message by this processing module according to this read signal, and this response message is fed back to the second data segment modular converter 21.The second data segment modular converter 21 is according to converting this response message to M3 data segment with the first data segment modular converter, 11 identical transformation rules, and each data segment is made up of N bit equally, and M3 >=1 transfers to second interface module 22 respectively with each data segment.Second interface module 22 is first interface module 12 that the data/address bus of N feeds back to this end unit 1 through this bit wide.First interface module 12 whenever receives after the data segment, passes to the first data segment modular converter 11.The first data segment modular converter 11 is received after M3 the data segment, resolves according to corresponding resolution rules, restores the response message that end unit 2 is fed back.
For this end unit 1; Information waiting for transmission comprises address information, data message and control information, is used for to end unit 2 is write data, and information perhaps waiting for transmission comprises address information and control information; Be used for to end unit 2 reading of data; For as far as end unit 2, information waiting for transmission comprises data message, i.e. response message.This end unit 1 need need convert address information waiting for transmission, data message and control information to one or more data segment when end unit 2 is write data; Need need convert address information waiting for transmission and control information to one or more data segment to end unit 2 reading of data the time; Need need convert response message waiting for transmission to one or more data segment when this end unit 1 feedback response information to end unit 2.
This end unit 1 can be identical with transformation rule to end unit 2 data segments, and transformation rule has multiple, and as earlier various information waiting for transmission being merged, the information after being combined is carried out data segment conversion.With this end unit 1 is example, and the first data segment modular converter 11 can comprise the merging module and the first sub-modular converter.If this end unit 1 need merge module and be used for address information waiting for transmission, data message and control information are merged when end unit 2 write data, the first sub-modular converter is used for the information translation after merging is become M1 data segment.Suppose that this end unit 1 address information waiting for transmission is that the binary bits data of A1 position, data message waiting for transmission are the binary bits data of D1 position; Control information waiting for transmission comprises 1 chip selection signal, 1 write signal; Merge the binary bits data that module is merged into address information waiting for transmission, data message and control information the A1+D1+1+1 position; The first sub-modular converter is used for the information translation after merging is become M1 data segment; M1=CEILING (A1+D1+1+1/N), CEILING () is for removing decimal capping integer, M1 >=1.If this end unit 1 need merge module and be used for address information waiting for transmission and control information are merged to end unit 2 reading of data the time, the first sub-modular converter is used for the information translation after the merging is become M2 data segment.Suppose that this end unit 1 address information waiting for transmission is that the binary bits data of A2 position, control information waiting for transmission comprise 1 chip selection signal, 1 read signal; Merge the binary bits data that module is merged into address information waiting for transmission and control information the A2+1+1 position; The first sub-modular converter is used for the information translation after merging is become M2 data segment; M2=CEILING (A2+1+1/N), CEILING () is for removing decimal capping integer, M2 >=1.
Transformation rule can also be that various information waiting for transmission are carried out the data segment conversion respectively.With this end unit 1 is example; The first data segment modular converter 11 comprises the second sub-modular converter; If this end unit 1 need be when writing data to end unit 2, the second sub-modular converter is used for respectively the data segment conversion being carried out in address information waiting for transmission, data message and control information.Suppose that this end unit address information waiting for transmission is that the binary bits data of A1 position, data message waiting for transmission are the binary bits data of D1 position, control information waiting for transmission comprises 1 chip selection signal, 1 write signal; The second sub-modular converter converts address information waiting for transmission into x1 data segment, x1=CEILING (A1/N), and CEILING () is for removing decimal capping integer; X1 >=1; Convert data message waiting for transmission into y1 data segment, y1=CEILING (D1/N), y1 >=1; Convert control information into 1 data segment, x1+y1+1=M1.Like this, the second sub-modular converter has just converted address information waiting for transmission, data message and control information to M1 data segment.12 of first interface modules need be the data/address bus of N through bit wide, once transmit a data segment, M1 transmission of process, just can this M1 data segment be transferred to end unit 2.If this end unit 1 need be to end unit 2 reading of data the time, the second sub-modular converter is used for respectively data segment conversion being carried out in address information waiting for transmission and control information.Suppose that this end unit address information waiting for transmission is that the binary bits data of A2 position, control information waiting for transmission comprise 1 chip selection signal, 1 read signal; The second sub-modular converter converts address information waiting for transmission into x2 data segment, x2=CEILING (A2/N), and CEILING () is for removing decimal capping integer, and x2 >=1 converts control information into 1 data segment, x2+1=M2.Like this, the second sub-modular converter has just converted address information waiting for transmission, data message and control information to M2 data segment.12 of first interface modules need be the data/address bus of N through bit wide, once transmit a data segment, M2 transmission of process, just can this M2 data segment be transferred to end unit 2.
Realization principle for description transformation rule that can be detailed; Suppose that this end unit 1 need be to end unit 2 is write data; Address information waiting for transmission is 22 binary bits data " 10 0,100 0,101 0,101 1,010 1010 "; Data message waiting for transmission is 16 binary bits data " 1,010 1,010 0,101 0101 "; Control information waiting for transmission comprises 1 chip selection signal and 1 write signal, and the bit wide of the data/address bus between first interface module 12 and second interface module 22 is 8, i.e. N=8.
So; The second sub-modular converter can convert this address information of 22 " 10 0,100 0,101 0,101 1,010 1010 " into 3 bytes (CEILING (22/8)=3); As convert following three bytes respectively into: " 0,010 0100 ", " 010 10101 ", " 1,010 1010 ", each byte is made up of 8 bits, wherein the low byte of " 1,010 1010 " corresponding address information; The high byte of " 0,010 0100 " corresponding address information; Because address information is 22, need fill two 0 on the left side of its high byte " 100 100 ", become " 0,010 0100 ".It is 8 data/address bus that each byte takies bit wide, and it is that 8 data/address bus transmits 3 times that 22 address information " 10 0,100 0,101 0,101 1,010 1010 " needs bit wide;
Convert this data message of 16 waiting for transmission " 1,010 1,010 0,101 0101 " into 2 bytes (CEILING (16/8)=2); As be respectively " 1,010 1010 ", " 0,101 0101 "; Each byte is made up of 8 bits; The low byte of " 0,101 0101 " corresponding data information wherein, the high byte of data message is answered in " 1,010 1010 ".It is 8 data/address bus that each byte takies bit wide, and it is that 8 data/address bus transmits 2 times that 16 data message " 1,010 1,010 0,101 0101 " needs bit wide;
Convert control information into 1 byte, it is that 8 data/address bus transmits 1 time that control information needs bit wide.Bit wide is the number of times M=3+2+1=6 that 8 data/address bus need transmit altogether.
After address information, control information, address information converted data segment to, sending order is the branch of priority not.Preferably; When 1 pair of this end unit carries out read operation to end unit 2; This end unit 1 can send control information earlier and the pairing data segment of address information, and then sends the corresponding data segment of data message, and the sending order of address information and the pairing data segment of control information is the branch of priority not; Can be that the corresponding data segment of control information is in preceding transmission; The corresponding data segment of address information sends in the back, and the data segment that also can be the address information correspondence is in preceding transmission, and the corresponding data segment of control information sends in the back.When 1 pair of this end unit carried out write operation to end unit 2, the pairing data segment of address information, control information and data message can send according to random order.
In another embodiment, this end unit 1 can also comprise the framing module, is used for the data segment that the first data segment modular converter 11 converts to is formed one or more Frames; It is that the data/address bus of N is passed to end unit 2 through bit wide that first interface module 12 is used for each data segment of each Frame.In such cases, this end unit 1 and to also transmitting frame signal between the end unit 2, frame signal also can be used as control information; After carrying out the data segment conversion in the lump, be the data/address bus transmission of N, also can take a frame signal line separately and transmit through bit wide; If select the latter; Then this end unit 1 and to being that data/address bus, the bit wide of N is 1 the clock cable except needing bit wide between the end unit 2 also needs a frame signal line, is used to transmit frame signal.Further, chip selection signal can lie in this frame signal, only need transmit read signal or write signal in the control information so.Correspondingly, also can comprise the framing module, be used for the data segment that the second data segment modular converter 21 converts to is formed one or more Frames end unit 2; It is that the data/address bus of N is passed to this end unit 1 through bit wide that second interface module 22 is used for each data segment of each Frame.
But the first data segment modular converter, the second data segment modular converter can be realized through the programming in logic device; XC3S400AN-4FGG400C, the Altera EP2AGZ350HF40C3N of producer like the XILINX of producer;, just can realize the function of the first data segment modular converter, the second data segment modular converter as long as but this programming in logic device is carried out the programming of respective rule.
As shown in Figure 3; Sketch map for bus communication system in the prior art; Bus communication system comprises first veneer 31 and second veneer 32, and is interconnected through connector, and CPU is arranged on first veneer 31; But also comprise the first programming in logic device 311 on first veneer 31, but first link 331 of the first programming in logic device, 311 external connectors 33; But the device (device 1, device 2 are to device n) that comprises the second programming in logic device 321 and a plurality of support cpu bus interfaces on second veneer 32; But second link, 332, the first links 331 and second link 332 of the second programming in logic device, 321 external connectors 33 are the matching component of connector 33.First veneer 31 is the address space that second veneer 32 provides 4M; CPU is used for clocking, multichannel chip selection signal, read signal, write signal, address date multiplexed signals etc.; But the first programming in logic device 311 is used for each signal that CPU produces is isolated and processing, produces that simplify, easy-operating cpu i/f, can dispose CPU simultaneously; Aiding CPU reads log-on message, to other cpu i/f devices of veneer conduct interviews the management etc.After but the first programming in logic device 311 is handled, obtain clock signal, 1 chip selection signal, 1 read signal, 1 write signal, 22 address information, 16 data message between 1 plate, according to traditional bus communication mode; These signals need take 42 pins of connector 33 at least, and wherein to be used for inserting bit wide be clock cable between 1 plate for 1 pin, are used for transmitting clock signal between 1 plate; It is 1 chip selection signal line that 1 pin is used for inserting bit wide; Be used for transmitting 1 chip selection signal, it is 1 reading signal lines that 1 pin is used for inserting bit wide, is used for transmitting 1 read signal; It is 1 write signal line that 1 pin is used for inserting bit wide; Be used for transmitting 1 write signal, it is 22 address bus that 22 pins are used for inserting bit wide, is used for transmitting 22 address information; It is 16 data/address bus that 16 pins are used for inserting bit wide, is used for transmitting 16 data message.
If adopt bus communication mode of the present invention; Then its bus pin quantity will significantly reduce; The pin number that takies connector accordingly also significantly reduces; As shown in Figure 4, comprise CPU on first veneer 41, but also comprise the first programming in logic device 411; But the first programming in logic device 411 can be realized the function of the first data segment modular converter, framing module and first interface module; But the first programming in logic device 411 is first link 431 of external connector 43 directly, also can pass through first link 431 of external this connector 43 of signal driver spare, but comprises the second programming in logic device 421 and a plurality of devices (device 1, device 2 are to device n) of supporting cpu bus interface on second veneer 42; But the second programming in logic device 421 can be realized the function of the second data segment modular converter, framing module and second interface module; But the second programming in logic device 421 is second link 432 of external connector 43 directly, can be the matching component of connector 43 through second link, 432, the first links 431 and second link 432 of external this connector 43 of signal driver spare also.First veneer 41 is the address space that second veneer 42 provides 4M; According to bus communication rule of the present invention, 1 realization of first veneer only need take 10 pins of connector 43 to the read-write operation of second veneer 2; Wherein to be used for inserting bit wide be clock cable between 1 plate for 1 pin; Be used for transmitting clock signal between 1 plate, wherein to be used for inserting bit wide be frame signal line between 1 plate for 1 pin, is used for transmitting frame signal between 1 plate; It is 8 data/address bus that 8 pins are used for inserting bit wide, is used for transmitting the byte of being made up of 8 bits.If further, with bit wide be 8 data/address bus to replace to bit wide be 4 data/address bus, the quantity that then takies the pin of connector can reduce to 6, the very big like this quantity that takies connector pinout that reduced.
Specifically describe the read-write operation process below, all processes all are benchmark with the clock signal, and it comprises clock signal between first veneer, 41 internal clock signals and plate, and first veneer, 41 internal clocks are used for the operation of first veneer, 41 internal logics.Clock is produced by first veneer 41 between plate, is used for the operation of second veneer, 42 internal logics.Clock can be a same frequency between first veneer, 41 internal clocks and plate, also can be different frequency, but must guarantee between plate clock frequency more than or equal to first veneer, 41 internal clock frequencies, otherwise may greatly influence bus performance.In example of the present invention, clock is 180 degree phase shift outputs of first veneer, 41 internal clocks between plate.
Read operation.The CPU of first veneer 41 initiates read operation, but the first programming in logic device 411 of first veneer 41 detects effective chip selection signal at the 1st rising edge clock; Detect effective read signal at the 2nd rising edge clock, represent that at this moment the read operation that CPU initiates begins; At the 3rd rising edge clock; But the first programming in logic device 411 becomes low level with frame signal by high level; A control byte C who simultaneously control information is converted to (" 0,000 0000 ") is that 8 data/address bus sends through bit wide between plate; The position 0 of control byte is " 0 ", represents this to be operating as read operation; At the 4th rising edge clock, but the first programming in logic device 411 becomes high level with frame signal by low level, and the upper byte A in 3 bytes that address information is converted to (A ', A ", A " ') " ' send through 8 bit data bus between plate; At the 5th rising edge clock, " send through 8 bit data bus between plate but the first programming in logic device 411 is with byte A; At the 6th rising edge clock, but the first programming in logic device 411 with address byte A ' through 8 bit data bus between plate send (byte A ', the sending order no requirement (NR) of A ", A " ', sending out a high byte earlier only is example); In 16 clocks of ensuing the 7th clock to the, but the first programming in logic device 411 is in wait state, waits for that second veneer 42 returns response message; At the 17th clock trailing edge, but 8 bit data bus are obtained data byte D that second veneer 42 returns " (second veneer 42 converts response message to byte D " and D ' between the first programming in logic device, 411 slave plates) and keep in; At the 18th clock trailing edge, but 8 bit data bus are obtained data byte D ' and are kept between the first programming in logic device, 411 slave plates; At the 19th rising edge clock, " and D ' is reduced into 16 bit data information to A veneer programmable logic device with temporary D; In the 20th clock to the 23 clock times, but the 16 bit data information that the first programming in logic device 411 will reduce offer the CPU sampling, and waiting for CPU is accomplished data sampling; At the 23rd rising edge clock, central processor CPU is accomplished data sampling, and chip selection signal and read signal are placed disarmed state, and read operation is accomplished.
But the second programming in logic device 421 of second veneer 42 is a benchmark with clock between plate; Frame signal is that low level is as the 1st clock between plate to detect; But 8 bit data between the 1st the rising edge clock second programming in logic device, 421 temporary frame signals and plate obtain control byte C; At the 2nd rising edge clock, but the second programming in logic device 421 judges it is read operation or write operation according to control byte C, detects that to put in place 0 be that " 0 " representes that this is operating as read operation; At the 3rd rising edge clock, but the second programming in logic device, 421 latch address byte A " '; At the 4th rising edge clock, but the second programming in logic device, 421 latch address byte A "; At the 5th rising edge clock, but the second programming in logic device, 421 latch address byte A ', and combine byte A " ', A " and A ', and restore 22 bit address information, simultaneously chip selection signal in the plate is changed to low level; At the 6th rising edge clock, but the second programming in logic device 421 is changed to low level with read signal in the plate; In 13 clock times of the 7th clock to the,, the second programming in logic device 421 returns read data but beginning to wait for 22 bit address institute respective devices; At the 14th rising edge clock, but the second programming in logic device 421 has obtained stable read data, and the most-significant byte formation data byte D of 16 place reading certificates " is sent through 8 bit data bus between plate.Simultaneously chip selection signal in the plate and read signal are changed to high level.In the present embodiment, second veneer, 42 chip selection signals were handled according to 9 clock cycle, if select in the scope at this sheet, the device in second veneer 42 can't be accomplished accessing operation, also can consider to adopt the indirect addressing mode to realize; At the 15th rising edge clock,, the second programming in logic device 421 sends (the sending order no requirement (NR) of byte D ", D ", sending out a high byte earlier only is example) through 8 bit data bus between plate but forming data byte D ' with the least-significant byte of 16 place reading certificates; The 16th clock, 8 bit data bus data keep between plate; The 17th clock, 8 bit data bus between release board, read operation is accomplished.
Write operation.The CPU of first veneer 41 initiates write operation, but the first programming in logic device 411 detects effective chip selection signal at the 1st rising edge clock; Detect effective write signal at the 2nd rising edge clock, represent that at this moment the write operation that CPU initiates begins; At the 3rd rising edge clock; But the first programming in logic device 411 becomes low level with frame signal by high level; A control byte C who simultaneously control information is converted to (" 0,000 0001 ") sends through 8 bit data bus between plate, and on behalf of this, the position 0 of control byte be operating as write operation for " 1 "; At the 4th rising edge clock; But the first programming in logic device 411 becomes high level with frame signal by low level; And the upper byte A in 3 bytes that address information is converted to (A ', A ", A " ') " ' through 8 bit data bus between plate send (byte A ', A ", A " ' the sending order no requirement (NR), sending out a high byte earlier only is example); At the 5th rising edge clock, " send through 8 bit data bus between plate but the first programming in logic device 411 is with byte A; At the 6th rising edge clock, but the first programming in logic device 411 sends byte A ' through 8 bit data bus between plate; At the 7th rising edge clock, but the upper byte D in 2 bytes that the first programming in logic device 411 converts data message to (D ", D ') " send through 8 bit data bus between plate; At the 8th rising edge clock, but the first programming in logic device 411 sends (the sending order no requirement (NR) of byte D ", D ", sending out a high byte earlier only is example) with data byte D ' through 8 bit data bus between plate; In 21 clocks of ensuing the 9th clock to the, but the first programming in logic device 411 is in wait state, waits for the completion of second veneer, 42 write operations; At the 22nd rising edge clock, CPU places disarmed state with write signal; At the 23rd rising edge clock, CPU places disarmed state with chip selection signal, and write operation is accomplished.
But the second programming in logic device 421 of second veneer 42 is a benchmark with clock between plate; Frame signal is that low level is as the 1st clock between plate to detect; But 8 bit data between the 1st the rising edge clock second programming in logic device, 421 temporary frame signals and plate obtain control byte C; At the 2nd rising edge clock, but the second programming in logic device 421 judges it is read operation or write operation according to control byte C, detects that to put in place 0 be that " 1 " representes that this is operating as write operation; At the 3rd rising edge clock, but the second programming in logic device, 421 latch address byte A " '; At the 4th rising edge clock, but the second programming in logic device, 421 latch address byte A "; At the 5th rising edge clock, but the second programming in logic device, 421 latch address byte A ', and combine byte A " ', A " and A ' to restore 22 bit address information; At the 6th rising edge clock, but the second programming in logic device, 421 latch data byte D "; At the 7th rising edge clock, but the second programming in logic device, 421 latch data byte D ', and combine byte D " and D ', when restoring 16 bit data information of same chip selection signal in the plate is changed to low level; At the 8th rising edge clock, but the second programming in logic device 421 is changed to low level with write signal in the plate; In 15 clock times of the 9th clock to the, but the second programming in logic device 421 begins to wait for 22 bit address institute respective devices data writing operation; At the 16th rising edge clock, but the second programming in logic device 421 is changed to high level with write signal in the plate; At the 17th rising edge clock, but the second programming in logic device 421 is changed to high level with chip selection signal in the plate, and write operation is accomplished.In this enforcement, second veneer, 42 chip selection signals were handled according to 9 clock cycle, if select in the scope at this sheet, the device in second veneer 42 can't be accomplished accessing operation, also can consider to adopt the indirect addressing mode to realize.
Present embodiment; Through frame signal and 8 bit data bus between clock signal between 1 plate, 1 plate; Just can accomplish the read-write operation of 41 pairs second veneers 42 of first veneer; In prior art, use the scheme of the control bus transmitting control information of the address bus transmission address information of corresponding bit wide, the data/address bus transfer data information of using corresponding bit wide, the corresponding bit wide of use, can significantly reduce interface pin.
Above content is to combine concrete execution mode to the further explain that the present invention did, and can not assert that practical implementation of the present invention is confined to these explanations.For the those of ordinary skill of technical field under the present invention, under the prerequisite that does not break away from the present invention's design, can also make some simple deduction or replace, all should be regarded as belonging to protection scope of the present invention.
Claims (13)
1. a bus communication is characterized in that, comprising:
This end unit information translation waiting for transmission is become one or more data segments, and each data segment is made up of N bit, wherein N >=1; Said information waiting for transmission comprises address information, data message and control information, and perhaps said information waiting for transmission comprises address information and control information;
Is that the data/address bus of N is passed to end unit with each data segment through bit wide.
2. bus communication as claimed in claim 1; It is characterized in that; Also comprise: through said bit wide is the said response message to end unit feedback data section form of data/address bus reception of N, and converts the response message of said data segment form to corresponding data information.
3. bus communication as claimed in claim 1; It is characterized in that; Become the method for one or more data segments to be specially this end unit information translation waiting for transmission: earlier this end unit various information waiting for transmission are merged, the information after being combined is carried out the data segment conversion; Perhaps this end unit various information waiting for transmission are carried out the data segment conversion respectively.
4. bus communication as claimed in claim 3 is characterized in that, this end unit various information waiting for transmission is carried out respectively in the process of data segment conversion: convert control information waiting for transmission to 1 data segment.
5. bus communication as claimed in claim 1 is characterized in that said control information comprises chip selection signal, read signal and/or write signal.
6. like each described bus communication of claim 1 to 5, it is characterized in that said data segment is the byte of being made up of 8 bits.
7. like each described bus communication of claim 1 to 5; Is that the data/address bus of N is passed to before the end unit with each data segment through bit wide; Also comprise: data segment is formed one or more Frames, is that the data/address bus of N is passed to end unit with each data segment in each Frame through bit wide.
8. a bus communication unit is characterized in that, comprises data segment modular converter and interface module, wherein,
Said data segment modular converter is used for information translation waiting for transmission is become one or more data segments, and each data segment is made up of N bit, wherein N >=1; Said information waiting for transmission comprises address information, data message and control information, and perhaps said information waiting for transmission comprises address information and control information;
It is that the data/address bus of N is passed to end unit through bit wide that said interface module is used for each data segment.
9. bus communication as claimed in claim 8 unit is characterized in that, it is the said response message to end unit feedback data section form of data/address bus reception of N that said interface module also is used for through said bit wide; Said data segment modular converter also is used for converting the response message of said data segment form to corresponding data information.
10. bus communication as claimed in claim 8 unit is characterized in that, said data segment modular converter comprises the merging module and the first sub-modular converter; Said merging module is used for earlier various information waiting for transmission being merged; Information after the said first sub-modular converter is used to be combined is carried out the data segment conversion; Perhaps said data segment modular converter comprises the second sub-modular converter, is used for various information waiting for transmission are carried out the data segment conversion respectively.
11. like each described bus communication unit of claim 8-10, it is characterized in that said bus communication unit also comprises the framing module, be used for data segment is formed one or more Frames; It is that the data/address bus of N is passed to end unit through bit wide that said interface module is used for each data segment of each Frame.
12. a bus communication system is characterized in that, comprises that through bit wide be this end unit of communicating of the data/address bus of N and to end unit, wherein, said end unit is each described bus communication unit of claim 8-11; Said end unit is used for through said bit wide is the data segment of said the end unit transmission of data/address bus reception of N, and restores corresponding address information, data message and control information by the data segment that receives.
13. bus communication system as claimed in claim 12 is characterized in that, said end unit also is used for generating response message according to the data message that restores; Convert said response message to one or more data segment, each data segment is made up of N bit, wherein N >=1; Is that the data/address bus of N feeds back to said end unit with each data segment through said bit wide.
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