CN108010476B - Video signal transmission clock generating device and method - Google Patents
Video signal transmission clock generating device and method Download PDFInfo
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Abstract
The invention discloses a video signal transmission clock generating device and a method, wherein the device is provided with a video clock interface, a video data interface, a configuration parameter interface, an input clock frequency accurate detection unit, an upper layer configuration module and a clock reconfiguration unit; the input clock frequency accurate detection unit generates a reference clock, performs stabilization, phase adjustment, clock domain adjustment and frequency multiplication on a received input video clock to generate a synchronous detection clock, and generates a unit time signal according to the reference clock; detecting and obtaining an input clock frequency value according to a reference clock, a synchronous detection clock and a unit time signal when a continuous and stable video clock is input; acquiring parameters configured by an upper layer through a configuration parameter interface, and performing clock reconfiguration according to the configuration parameters, a pre-stored PLL parameter table and an input clock frequency value to acquire a configurable video signal transmission clock; the device and the method can obtain the video signal transmission clock with flexibly configurable frequency and phase according to the video signal clock input at any frequency and the requirement.
Description
Technical Field
The invention belongs to the technical field of liquid crystal module detection, and particularly relates to a video signal transmission clock generating device and method.
Background
When the liquid crystal module is inspected on a production line, the dot screen effect of the module under different field frequencies and different image clock frequencies needs to be detected frequently, and switching is frequently performed under different field frequencies and different clock frequencies. However, after the conventional image signal generating device is powered on, the field frequency and the image clock of the output image of the conventional image signal generating device are fixed, and flexible switching cannot be performed, so that a device capable of flexibly adjusting the frequency and the phase of the output clock according to configuration is required to meet the detection requirement of the liquid crystal module.
Disclosure of Invention
In view of the above drawbacks and needs of the prior art, the present invention provides a video signal transmission clock generating apparatus and method, which is capable of converting a video signal clock input at an arbitrary frequency into a desired output video clock signal, and the frequency and phase of the output video clock signal can be flexibly changed by an upper layer configuration.
To achieve the above object, according to one aspect of the present invention, there is provided a video signal transmission clock generating apparatus, including an FPGA-based implementation, having a video clock interface, a video data interface, and a configuration parameter interface for receiving an input video clock, input video data, and output video signal configuration parameters;
the device also comprises an input clock frequency accurate detection unit, an upper layer configuration module and a clock reconfiguration unit;
the input clock frequency accurate detection unit is used for generating a reference clock, stabilizing an input video clock received through a video clock interface to generate a stable video clock, performing phase adjustment, clock domain adjustment and frequency multiplication on the stable video clock to generate a synchronous detection clock, and generating a unit time signal according to the reference clock; and detecting and obtaining an accurate input clock frequency value according to the reference clock, the synchronous detection clock and the unit time signal when the continuous and stable video clock is input;
the upper layer configuration module is used for acquiring the output video signal configuration parameters configured by the upper layer through the configuration parameter interface;
the clock reconfiguration unit is used for carrying out clock reconfiguration according to the output video signal configuration parameters, the pre-stored PLL parameter table and the input clock frequency value to obtain configurable IO serial clock of the output video clock, system byte clock of the output video clock, IO serial clock of the output video data and system byte clock of the output video data.
Preferably, the video signal transmission clock generating apparatus further includes a serializing unit, and a data serializing bit interface and a clock serializing bit interface for outputting a serializing bit of the video data and a serializing bit of the video clock;
the serializing unit is used for generating the serializing bits of the video clock according to the IO serializing clock for outputting the video clock and the system byte clock for outputting the video clock, and is used for generating the serializing module bits of the video data according to the IO serializing clock for outputting the video data and the system byte clock for outputting the video data.
Preferably, in the video signal transmission clock generating apparatus, the input clock frequency accurate detection unit includes an input clock stabilizing module, a reference clock generating module, a unit time generating module, and a clock frequency detecting module;
the input clock stabilization module is used for continuous input monitoring, and specifically generates an input clock monitoring signal under the condition that a continuous input video clock enters, and sends the input clock monitoring signal to the reference clock generation module and the clock frequency detection module; the video clock generating module is used for performing stabilization processing of removing jitter, removing burrs, balancing and increasing signal amplitude on a continuously input video clock, generating a stable video clock and sending the stable video clock to the reference clock generating module;
the reference clock generating module is used for generating a reference clock, performing precision improvement and jitter removal on the stable video clock according to an input clock monitoring signal and the reference clock, adjusting the phase, adjusting the clock domain to keep strict synchronization with the reference clock and keep the stable video clock in the same global clock domain, and performing M frequency multiplication on the adjusted video clock to generate a synchronous detection clock, wherein M is a natural number not less than 2;
the unit time generating module is used for generating a 'unit time signal' in the form of a pulse signal with continuous periods according to the reference clock;
the Clock frequency detection module is used for buffering the unit time signal by using a DCFIFO (Double Clock FIFO, read-write Clock independent) by taking the reference Clock as a write Clock, reading the buffered unit time signal from the DCFIFO by taking the synchronous detection Clock as a read Clock, converting the buffered unit time signal into a level state mark of a Clock domain of the synchronous detection Clock, and counting high levels in the level state mark; dividing the high level count by M to obtain the input video clock frequency value detected this time;
preferably, the video signal transmission clock generating device further includes a clock frequency value caching module, where the clock frequency value caching module is configured to cache the detected input video clock frequency value;
the clock frequency value caching module preferably comprises two RAMs, the frequency value detected at the nth second is stored in one RAM1, and the frequency value detected at the (n +1) th second is stored in the other RAM 2;
the clock frequency value caching module takes one second as a period, detects a frequency value at the nth second and stores the frequency value in the RAM1, continues the frequency detection at the (n +1) th second and stores the detected frequency value in the RAM2 at the (n +1) th second, and screens the frequency value stored in the RAM1 at the nth second to remove an abnormal frequency value caused by the jump of an input video clock; wherein n is a natural number.
Preferably, in the video signal transmission clock generating apparatus, the clock reconfiguration unit includes a clock reconfiguration module, a PLL doubling parameter storage table, a PLL reconfiguration operation module, a first PLL module, and a second PLL module;
the clock reconfiguration module is used for receiving an input clock frequency value output by the input clock frequency accurate detection unit, generating a frequency multiplication operation mode of the first PLL module and the second PLL module according to the configuration of the upper configuration module on the input video parameter and the output video parameter, and taking out a PLL frequency multiplication coefficient matched with the input clock frequency value and the upper configuration from the PLL frequency multiplication parameter storage table 8 according to the frequency multiplication operation mode, wherein the PLL frequency multiplication coefficient comprises a PLL frequency multiplication coefficient, a frequency division coefficient, an output frequency phase value, an input frequency phase value and a VCO oscillation frequency;
the PLL frequency multiplication parameter storage table is used for storing preset PLL parameters;
the PLL reconfiguration operation module is used for converting the PLL frequency multiplication coefficient into a device physical layer configuration signal of the PLL;
the first PLL module is used for generating an IO serial clock for outputting a video clock and a system byte clock for outputting the video clock according to the device physical layer configuration signal and the stable video clock output by the input clock stabilizing module;
the second PLL module is configured to generate an IO serial clock for outputting video data and a system byte clock for outputting video data according to the device physical layer configuration signal and the stable video clock output by the input clock stabilization module.
Preferably, the video signal transmission clock generating apparatus includes a serializing unit including a video data converting module, a serializing module for outputting a video clock, and a serializing module for outputting video data;
the serialization module of the output video clock is used for generating serialization bits of the video clock according to the IO serialization clock of the output video clock, the system byte clock of the output video clock and the serialization ratio value of the output video clock output by the clock reconfiguration module, which are output by the first PLL module;
the serialization module for outputting the video data is used for performing serial-parallel conversion on the video data output by the video data conversion module according to the IO serialization clock for outputting the video clock and the system byte clock for outputting the video data output by the second PLL module, and outputting the serialization bit of the serialized video data.
To achieve the object of the present invention, according to another aspect of the present invention, there is provided a video signal transmission clock generating method, including the steps of:
(1) under the condition that continuous input video clocks enter, stabilizing the received continuous input video clocks to generate stable video clocks;
(2) generating a reference clock, and generating a unit time signal according to the reference clock; the unit time signal is a pulse signal with continuous period;
carrying out phase adjustment, clock domain adjustment and frequency multiplication on the stable video clock to generate a synchronous detection clock; detecting and obtaining an input clock frequency value according to the reference clock, the synchronous detection clock and the unit time signal when the continuous and stable video clock is input;
under the condition that the input of the received video clock is unstable, stopping the stability processing of improving the precision and removing the jitter and the processing of phase adjustment, clock domain adjustment and frequency multiplication to avoid the introduction of external interference to cause misoperation;
(3) and performing clock reconfiguration according to the output video signal configuration parameters configured at the upper layer, the pre-stored PLL parameter table and the input clock frequency value to obtain a configurable IO serial clock for outputting the video clock, a system byte clock for outputting the video clock, an IO serial clock for outputting the video data and a system byte clock for outputting the video data.
Preferably, the above video signal transmission clock generating method further includes the following step (4) of serialization processing;
(4) generating serial bits of the video clock according to an IO serial clock of the output video clock and a system byte clock of the output video clock; and generating the serial bits of the video data according to the IO serial clock for outputting the video data, the system byte clock for outputting the video data and the video input data.
Preferably, the video signal transmission clock generating method described above, wherein the step (2) includes the following sub-steps:
(2.1) generating a high-precision reference clock; the reference clock has no jitter, is not influenced by the change of the ambient temperature and is not influenced by external interference; generating a pulse signal with continuous period as a unit time signal according to the reference clock;
(2.2) adjusting the phase of the stable video clock by adopting a clock management unit and an IO buffer delay adjusting unit contained in the FPGA device to keep strict synchronization with the reference clock;
adjusting the phase-adjusted video clock and the reference clock to the same global clock domain by using a global clock network in the FPGA device;
(2.3) carrying out M frequency multiplication on the synchronized video clock to generate a synchronous detection clock; m is a natural number not less than 2;
the beneficial effects of the treatment are as follows: avoiding the occurrence of timing errors when subsequently detecting and changing the clock frequency phase, thereby causing errors or errors in the detected frequency value and the changed frequency value; moreover, the detection clock with M times of the frequency of the input video clock is used for detecting the clock, so that the frequency of less than 1Mhz can be more accurately detected (for example, the input 75.5MHz can be detected, but the error is 75 MHz);
(2.4) buffering the unit time signal with the reference clock as a write clock when a continuous and stable video clock is input, reading the buffered unit time signal with the synchronous detection clock as a read clock, converting the buffered unit time signal into a level state flag, and counting high levels in the level state flag; and dividing the high-level counting value by M to obtain the input video clock frequency value detected this time.
Preferably, the above video signal transmission clock generating method further includes the step of buffering the detected input video clock frequency value as follows:
(a) taking one second as a period, detecting the frequency value at the nth second and storing the detected input clock frequency value into a random access memory RAM 1;
(b) at the (n +1) th second, the frequency detection of the (n +1) th second is continued and the detected input clock frequency value is saved into another random access memory RAM 2; synchronously screening the frequency value stored in the RAM1 at the nth second by adopting a probability majority rule and a normal distribution principle to remove an abnormal frequency value caused by the jump of an input video clock; wherein n is a natural number.
In general, compared with the prior art, the above technical solution contemplated by the present invention can achieve the following beneficial effects:
(1) the invention provides a video signal transmission clock generating device and a method, which are characterized in that parameters configured on an upper layer are obtained through a configuration parameter interface, and clock reconfiguration is carried out according to the configuration parameters, a pre-stored PLL parameter table and detected accurately input clock frequency values to obtain a configurable video signal transmission clock; the device and the method can obtain the video signal transmission clock with flexibly configurable frequency and phase according to the video signal clock input by any frequency and the requirement;
(2) the invention provides a video signal transmission clock generating device and a method, which are used for monitoring the continuous stability of an input video clock, indicating through an input clock monitoring signal only when the continuous and stable input video clock is received, and informing a subsequent module to process; otherwise, the video clock input interface is closed, and the subsequent synchronous processing is stopped, so that the misoperation caused by the entrance of external interference is avoided, and the accuracy of the input clock frequency detection is improved;
(3) the invention provides a video signal transmission clock generating device and method, wherein the clock frequency detection module 5 is in reset state when it does not receive the input clock monitoring signal, and only when it receives the input clock monitoring signal, the module and DCFIFO start working, thus avoiding the influence of the last frequency detection result on the current frequency detection; after receiving the "input clock monitoring signal", the DCFIFO in the clock frequency detection module 5 reads the unit time signal from the FIFO under the control of the synchronous detection clock, and performs clock domain conversion, which can avoid the problem of counting error caused by the clock domain crossing condition in the subsequent high-level counting operation, thereby further improving the accuracy of input clock frequency detection;
(4) the invention provides a video signal transmission clock generating device and a method, wherein the preferred scheme generates a synchronous detection clock after frequency multiplication of M times of a synchronous video clock to detect the frequency of an input video clock, thereby avoiding the occurrence of time sequence errors when subsequently detecting and changing the clock frequency phase, causing errors and errors of a detected frequency value and a changed frequency value, and detecting the clock by using the detection clock of M times of the frequency of the input video clock, so that the frequency of less than 1Mhz can be more accurately detected.
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Fig. 1 is a schematic diagram of an embodiment of a video signal transmission clock generating apparatus according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
The video signal transmission clock generating apparatus provided in the embodiment is implemented based on an FPGA, and specifically, referring to fig. 1, includes a video data conversion module 1, an input clock stabilization module 2, a reference clock generation module 3, a unit time generation module 4, a clock frequency detection module 5, an upper configuration module 6, a clock reconfiguration module 7, a PLL frequency multiplication parameter storage table 8, a PLL reconfiguration operation module 9, a first PLL module 10, a second PLL module 11, a serialization module 12 for outputting a video clock, a serialization module 13 for outputting video data, and a clock frequency value cache module 5-1;
the video data conversion module 1 is used for sampling input video data according to an input video clock and caching local image data obtained after sampling;
and is used for converting input video data into a configured output video data form (for example, converting input double-link video data into a single-link video data form for output) by using a system byte clock for outputting video data according to upper-layer video configuration parameters (for example, configuring the input double-link video data into input double-link video and outputting the single-link video).
The input clock stabilizing module 2 is used for judging whether a continuous input video clock enters or not, performing stabilization processing on the input video clock such as debouncing, deburring and balancing and increasing the signal amplitude when the continuous input video clock enters, restoring the input video clock into a stable video clock, sending the stable video clock to the reference clock generating module 3, generating an input clock monitoring signal, and sending the input clock monitoring signal to the reference clock generating module 3 and the clock frequency detecting module 5;
if the input video clock signal entering the input clock stabilization module 2 is short and discontinuous, the input video clock signal is determined as external interference, and the input clock stabilization module 2 does not take care of the external interference until the input video clock signal continues for a certain time and then the input clock stabilization module 2 performs stabilization processing.
The reference clock generating module 3 is used for generating a reference clock, and is used for performing precision improvement and jitter removal processing on the video clock output by the input clock stabilizing module 2 according to the input clock monitoring signal and the reference clock, adjusting the phase, adjusting the clock domain to keep strict synchronization with the reference clock and locate the clock domain on the same global clock domain, and performing quadruple frequency on the adjusted video clock to generate a synchronous detection clock.
The unit time generation block 4 is configured to generate a "unit time signal" in the form of a pulse signal having consecutive periods from the reference clock generated by the reference clock generation block 3.
The Clock frequency detection module 5 includes a DCFIFO (Double Clock FIFO, read/write Clock independent), writes the above-mentioned "unit time signal" into the DCFIFO with the reference Clock output by the reference Clock generation module 3 as the write operation Clock of the DCFIFO write side, and uses the synchronous detection Clock output by the reference Clock generation module 3 as the read operation Clock of the DCFIFO read side;
the clock frequency detection module 5 is configured to buffer the received "unit time signal" by using the DCFIFO, and is configured to read and convert the buffered "unit time signal" into a level status flag of a clock domain of the "synchronous detection clock" under the control of the "synchronous detection clock" after receiving the "input clock monitoring signal" output by the input clock stabilization module 2, count a high level in the level status flag, and divide a count value by a multiple of the frequency of the reference clock generation module 3 to obtain a frequency value of the input video clock detected this time, so as to avoid a count error caused by a clock domain crossing condition in a subsequent high level counting operation.
The clock frequency value caching module 5-1 is used for caching the detected frequency value of the input video clock;
the upper layer configuration module 6 is used for receiving externally input output video signal configuration parameters;
the clock reconfiguration module 7 is configured to receive the input clock frequency value output by the clock frequency detection module 5, generate a frequency doubling operation mode of each subsequent PLL according to the configuration of the upper configuration module 6 on the input video parameter and the output video parameter, and extract, from the PLL frequency doubling parameter storage table 8, a PLL frequency doubling coefficient matched with the "input clock frequency value" and the upper configuration, including a PLL frequency doubling coefficient, a frequency division coefficient, an output frequency phase value, an input frequency phase value, and a VCO oscillation frequency, according to the frequency doubling operation mode;
the PLL multiplication parameter storage table 8 is used for storing preset PLL parameters;
the PLL reconfiguration operation module 9 is used for converting the PLL frequency multiplication coefficient into a device physical layer configuration signal of the PLL;
the first PLL module 10 and the second PLL module 11 are respectively configured to generate an "IO serialized clock for outputting a video clock", "a system byte clock for outputting a video clock", "an IO serialized clock for outputting video data", and a "system byte clock for outputting video data" according to the device physical layer configuration signal and the stable video clock output by the input clock stabilization module 2;
the serialization module 12 for outputting the video clock is configured to generate the serialization bit of the video clock according to the "IO serialization clock for outputting the video clock", the "system byte clock for outputting the video clock", and the serialization ratio value of the output video clock output by the clock reconfiguration module 7, which are output by the first PLL module 10;
the serialization module 13 for outputting video data is configured to perform serial-parallel conversion on the video data output by the video data conversion module 1 according to the "IO serialization clock for outputting video clock" and the "system byte clock for outputting video data" output by the second PLL module 11, and output the serialization bit of the serialized video data.
The process of generating the required serialized video clock serialized bit and the video data serialized bit by the video signal transmission clock generation apparatus provided by the embodiment according to the upper layer configuration is described in detail as follows.
1. After power-on, the module 6 inputs parameters of the output video signal configured in the upper layer, such as the type of the output video, the output link number (or lane number), the output clock frequency and the phase.
2. After power-on, the input video data is sampled by adopting the input video clock in the video data conversion module 1 and the image data is cached in the video data conversion module 1.
3. The input clock is sent to an input clock stabilizing module 2 for stabilization, debouncing, deburring and equalization processing, the signal amplitude is increased, and the signal amplitude is restored to a standard video clock so as to facilitate the operation of a subsequent module; and the input clock stabilizing module 2 also checks whether an input clock enters or not, when the input clock exists, the input clock is output to a subsequent module after being stabilized, and on the one hand, an input clock monitoring signal is generated to inform the subsequent module of the possibility of operation. The input clock stabilization module 2 is also responsible for detecting whether continuous clock input exists, if the input signal is short, external interference is judged, the input clock stabilization module 2 does not process the input signal, and the input clock stabilization module 2 processes the input signal after the input signal lasts for a certain time.
4. The frequency of the input video clock is detected as follows:
after power-on, the module 3 generates a high-precision reference clock (frequency 100MHz), which has no jitter, is not affected by environmental temperature changes, and is not affected by external interference. When module 2 sends a stable standard input video clock to module 3, it generates an "input clock monitor signal";
after receiving the input clock monitoring signal, the reference clock generating module 3 firstly opens the input video clock interface, and further improves the precision and removes jitter of the video clock output by the input clock stabilizing module 2, so that the video clock is not influenced by environmental temperature change and external interference and reaches the level of the reference clock;
the phase of the FPGA device is adjusted by using a clock management unit and an IO buffering delay adjusting unit contained in the FPGA device, so that the FPGA device and a reference clock are kept strictly synchronous (namely, the rising edges of signals of the two clocks are synchronous at the initial moment, although the periods of the two clocks are different, the rising edges of the two clocks are synchronous again at the beginning of a new period after a plurality of periods);
then, the video clock after phase adjustment and the reference clock are adjusted to the same global clock domain by utilizing a global clock network in the FPGA device, namely the video clock and the reference clock are associated in a synchronous circuit system; performing quadruple frequency on the synchronized video clock to generate a synchronous detection clock, and sending the synchronous detection clock to a clock frequency detection module; the beneficial effects of the treatment are as follows: avoiding the occurrence of timing errors when subsequently detecting and changing the clock frequency phase, thereby causing errors or errors in the detected frequency value and the changed frequency value; moreover, the detection clock with the frequency 4 times that of the input video clock is used for detecting the clock, so that the frequency of less than 1Mhz can be more accurately detected (for example, the input 75.5MHz can be detected, but the error is 75 MHz); if the reference clock generating module 3 does not receive the "input clock monitoring signal", the input video clock is turned off, and the subsequent precision improvement, jitter removal and synchronization operations are stopped, so as to avoid the introduction of external interference to cause misoperation.
The unit time generation module 4 generates a 'unit time signal' in the form of a pulse signal of continuous cycles according to the reference clock generated by the reference clock generation module 3 and sends the 'unit time signal' to the clock frequency detection module 5, wherein the high level of the pulse lasts for 1 mus, and the low level lasts for 1 ms.
A DCFIFO (Double Clock FIFO, read-write Clock independent) is arranged in the Clock frequency detection module 5, a reference Clock is a DCFIFO write operation Clock at the write-in test of the DCFIFO, and a unit time signal is sent to a write operation port of the DCFIFO; at the read side of the DCFIFO, the synchronous detection clock is the clock for the DCFIFO read operation.
When the clock frequency detection module 5 does not receive the input clock monitoring signal, the internal FIFO of the module is reset; when receiving the input clock monitoring signal, the clock frequency detection module 5 and its DCFIFO start working, thus avoiding the influence of the last detection result on the current detection.
After receiving the "input clock monitoring signal", the FIFO in the clock frequency detection module 5 reads the unit time signal from the FIFO under the control of the synchronous detection clock, and converts it into the level status flag of the clock domain of the synchronous detection clock (the purpose of converting it into the same clock domain is to avoid the counting error caused by the clock domain crossing condition in the subsequent high level counting operation); when the level state flag is at high level, the high level is counted, when the flag changes to low level, the counting is stopped, because the frequency of the video clock is 4 times the frequency, the frequency value of the input video clock detected this time is obtained by dividing the count value by 4, the frequency value obtained this time is cached in the RAM1 of the module 5-1, when the next high level is reached, the frequency of the video clock is counted again, when the next high level is reached, the next frequency value is calculated and cached in the RAM1 of the module 5-1 again.
In this embodiment, the clock frequency detection module 5 takes one second as a large period, checks frequency values and stores them in the RAM1 when the nth second is, continues to detect frequency values and stores them in the RAM2 when the nth +1 second is, and filters frequency values stored in the RAM1 when the nth second is, because the input video clock is input and detected without interruption, but because of external environment reasons or stability of the image signal source, the input video clock frequency value does not always keep an ideal constant, but has sudden up and down jumps (e.g. up jump to 76MHz and down to 74MHz) at a nominal frequency value (e.g. 75MHz), the suddenly changed clock value is an abnormal value, in order to avoid the influence of the sudden clock change on the subsequent clock frequency multiplication change and video clock output, therefore, these abnormal values should be eliminated and the normal values should be retained.
When the frequencies are screened, all the stored frequency values are counted, and an ideal input clock frequency value is obtained by adopting a probability majority rule and a normal distribution principle (that is, most of the values are uniformly changed in a small range, and only few of the values are changed outside the range in different degrees, the most of the values are averaged in the small range, so that an average value can be regarded as a nominal frequency value), and the frequency value is sent to the clock reassembling module 7;
thus, the clock frequency detection module 5 detects and buffers the frequency in the RAM1 within a certain second, and at the same time filters another RAM2 for a nominal value, this filtering having been completed and the frequency value being sent to the next module until the next second begins; detecting the current frequency value in the next second, buffering the current frequency value in the RAM2, and screening the previous second value in the RAM 1; namely, the frequency value of the last second is screened and the frequency value of the current second is detected and cached at the same time.
5. When the clock reconfiguration module 7 receives the screened input clock frequency value, the appropriate PLL frequency multiplication parameter is taken out from the PLL frequency multiplication parameter storage table 8 according to the configuration of the input video parameter and the output video parameter by the upper configuration module 6 (the subsequent module generates the required clock frequency by PLL).
For example, when the upper layer is configured to input a dual link video signal and output a single link video signal, the phase of the output video clock and the phase of the output video data signal are reversed, i.e., the edge of the output clock bit is at the center of the output data bit, and the output clock is in the DDR mode (i.e., both the rising edge and the falling edge of the output clock can be sampled to the data center); data generated by internal logic of the FPGA is obtained at the rising edge of the clock, and equipment behind the FPGA receives the output data of the FPGA at the rising edge of the output clock of the FPGA; to ensure reception reliability, the output clock phase is reversed at the output of the FPGA so that the rising edge of the output clock occurs in the middle of the output data.
The clock reconfiguration module 7 generates a frequency doubling operation mode of each PLL, so that the subsequent PLL needs to perform a frequency doubling operation, specifically: (1) PLL-1 for outputting video clock: the input video clock is 75MHz, the output system byte clock frequency is 150MHz of double frequency, the output IO serialized clock is 150MHz multiplied by 4 which is 600MHz, and the output clock phase is 180 degrees; (2) PLL-2 for outputting video data: the input video clock is 75MHz, the output system byte clock frequency is doubled 150MHz, the output IO serialized clock is 150MHz × 8 — 1200MHz, and the output clock phase is 0 °.
The clock reconfiguration module 7 also searches and looks up each PLL frequency multiplication coefficient matched with the requirement from the PLL frequency multiplication parameter storage table 8 according to the frequency multiplication operation mode of each PLL; such as PLL multiplication factor, division factor, output frequency phase value, input frequency phase value, VCO oscillation frequency, etc. The values of the parameters are different due to different input frequency ranges, different frequency doubling requirements and different phases, and are determined according to the characteristics of the PLL, if the input frequency, the frequency doubling and the phase ranges are large, the parameter values are more, and in order to quickly obtain the parameters, the invention adopts a table look-up method to determine and solidify each PLL parameter corresponding to the variables of different frequencies, frequency doubling, phases and the like in advance into a PLL frequency doubling parameter storage table 8; when the input video clock is detected to be a certain frequency value and the frequency multiplication requirement and the phase requirement are obtained according to the upper layer configuration, each PLL frequency multiplication coefficient matched with the requirement is found out from the PLL frequency multiplication parameter storage table 8, so that a proper parameter value is quickly and accurately found out, and the output clock can be quickly changed to the correct frequency.
Moreover, the clock reconfiguration module 7 further generates a to-be-serialized clock value of the output video clock according to the parameter configured in the upper layer, for example, in the above example, the output video clock is in a 4-times DDR mode, and then the module 7 generates a 4-bit clock value: 1010, the clock value is serialized into a standard clock transmission bit through a module 12.
6. When the PLL reconfiguration operation module 9 receives the two PLL frequency multiplication coefficients sent by the clock reconfiguration module 7, it converts them into device physical layer configuration signals of the PLL according to the FPGA PLL reconfiguration operation steps and requirements, and sends them to the first PLL module 10 and the second PLL module 11; the first PLL module 10 generates an IO serial clock for outputting a video clock and a system byte clock for outputting the video clock according to a stable video clock, and sends the IO serial clock for outputting the video clock and the system byte clock for outputting the video clock to the serial module 12 for outputting the video clock, and the second PLL module 11 generates an IO serial clock for outputting video data and a system byte clock for outputting the video data according to a stable video clock, and sends the IO serial clock for outputting the video data and the system byte clock for outputting the video data to the serial module 13 for outputting the video data, and the IO serial clock and the system byte clock are converted into video serial.
7. When the video data conversion module 1 receives the "system byte clock of the output video data" output by the second PLL module 11, it converts the input video data (for example, converts the input dual link video data into a single link video data format for output) by using the system byte clock according to the received output video signal configuration parameters (for example, converts the input dual link video data into a single link video data format for output), and sends the output video data obtained by conversion to the SERDES component unit of the serialization module 13 of the output video data for serial-parallel conversion, and outputs the required serialized video bit data.
It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (10)
1. A video signal transmission clock generating device is realized based on FPGA and is characterized by comprising a video clock interface, a video data interface and a configuration parameter interface, wherein the video clock interface is used for receiving an input video clock, inputting video data and outputting configuration parameters of a video signal;
the device also comprises an input clock frequency accurate detection unit, an upper layer configuration module and a clock reconfiguration unit;
the input clock frequency accurate detection unit is used for generating a reference clock, stabilizing an input video clock received through a video clock interface to generate a stable video clock, performing phase adjustment, clock domain adjustment and frequency multiplication on the stable video clock to generate a synchronous detection clock, and generating a unit time signal according to the reference clock; and is used for detecting and obtaining an input clock frequency value when a continuous and stable video clock is input according to the reference clock, the synchronous detection clock and the unit time signal;
the upper layer configuration module is used for acquiring the output video signal configuration parameters configured by the upper layer through the configuration parameter interface;
the clock reconfiguration unit is used for carrying out clock reconfiguration according to the output video signal configuration parameters, the pre-stored PLL parameter table and the input clock frequency value to obtain an IO (input/output) serial clock of the output video clock with configurable frequency and phase, a system byte clock of the output video clock, an IO serial clock of the output video data and a system byte clock of the output video data.
2. The video signal transmission clock generating apparatus according to claim 1, further comprising a serializing unit, and a data serializing bit interface for outputting a serializing bit of the video data, a serializing bit of the video clock, a clock serializing bit interface;
the serialization unit is used for generating the serialization bit of the video clock according to the IO serialization clock of the output video clock and the system byte clock of the output video clock, and is used for generating the serialization bit of the video data according to the IO serialization clock of the output video data and the system byte clock of the output video data.
3. The video signal transmission clock generating apparatus of claim 1 or 2, wherein the input clock frequency accurate detection unit includes an input clock stabilization module, a reference clock generation module, a unit time generation module, and a clock frequency detection module;
the input clock stabilizing module is used for carrying out continuous input monitoring, generating an input clock monitoring signal under the condition that a continuous input video clock enters and sending the input clock monitoring signal to the reference clock generating module and the clock frequency detecting module; the device is used for performing stabilization processing of removing jitter, removing burrs, balancing and increasing signal amplitude on a continuous input video clock, generating a stable video clock and sending the stable video clock to a reference clock generation module;
the reference clock generation module is used for generating a reference clock, performing precision improvement and jitter removal on the stable video clock according to the input clock monitoring signal and the reference clock, adjusting the phase, adjusting the clock domain to keep the stable video clock and the reference clock synchronous and in the same global clock domain, and performing M frequency multiplication on the adjusted video clock to generate a synchronous detection clock, wherein M is a natural number not less than 2;
the unit time generating module is used for generating a unit time signal in a pulse signal form with continuous cycles according to the reference clock;
the clock frequency detection module is used for caching the unit time signal by using the DCFIFO and taking the reference clock as a write clock, reading the cached unit time signal from the DCFIFO and converting the unit time signal into a level state mark of a clock domain of the synchronous detection clock by taking the synchronous detection clock as a read clock, and counting high levels in the level state mark; and dividing the high level count by M to obtain the input clock frequency value detected this time.
4. The video signal transmission clock generating apparatus according to claim 3, further comprising a clock frequency value buffering module for buffering the detected input clock frequency value;
the clock frequency value cache module comprises two RAMs, the input clock frequency value detected at the nth second is stored in one RAM1, and the input clock frequency value detected at the (n +1) th second is stored in the other RAM 2;
the clock frequency value caching module takes one second as a period, detects frequency values at the nth second and stores the detected input clock frequency values into the RAM1, continues the frequency detection at the (n +1) th second and stores the detected input clock frequency values into the RAM2 at the (n +1) th second, and screens the input clock frequency values stored into the RAM1 at the nth second to remove abnormal frequency values caused by the jump of the input video clock; wherein n is a natural number.
5. The video signal transmission clock generating apparatus of claim 3, wherein the clock reconfiguring unit includes a clock reconfiguring module, a PLL multiplication parameter storage table, a PLL reconfiguration operating module, a first PLL module, and a second PLL module;
the clock reconfiguration module is used for receiving an input clock frequency value output by the input clock frequency accurate detection unit, generating a frequency multiplication operation mode of the first PLL module and the second PLL module according to the configuration of the upper configuration module on the input video parameter and the output video parameter, and taking out a PLL frequency multiplication coefficient matched with the input clock frequency value and the upper configuration from a PLL frequency multiplication parameter storage table according to the frequency multiplication operation mode;
the PLL frequency multiplication parameter storage table is used for storing preset PLL parameters;
the PLL reconfiguration operation module is used for converting a PLL frequency multiplication coefficient into a device physical layer configuration signal of the PLL;
the first PLL module is used for generating an IO serial clock for outputting a video clock and a system byte clock for outputting the video clock according to the device physical layer configuration signal and the stable video clock output by the input clock stabilizing module;
the second PLL module is used for generating an IO serial clock for outputting video data and a system byte clock for outputting the video data according to the device physical layer configuration signal and the stable video clock output by the input clock stabilizing module.
6. The video signal transmission clock generating apparatus according to claim 5, further comprising a serializing unit including a video data converting module, a serializing module that outputs a video clock, and a serializing module that outputs video data;
the serialization module of the output video clock is used for generating serialization bits of the video clock according to an IO serialization clock of the output video clock output by the first PLL module, a system byte clock of the output video clock and a serialization ratio value of the output video clock output by the clock reconfiguration module;
and the serialization module for outputting the video data is used for performing serial-parallel conversion on the video data output by the video data conversion module according to the IO serialization clock of the output video data output by the second PLL module and the system byte clock of the output video data, and outputting the serialization bit of the serialized video data.
7. A video signal transmission clock generating method, comprising the steps of:
(1) under the condition that continuous input video clocks enter, stabilizing the received continuous input video clocks to generate stable video clocks;
(2) generating a reference clock, and generating a unit time signal according to the reference clock; the unit time signal is a pulse signal with continuous period;
performing phase adjustment, clock domain adjustment and frequency multiplication on the stable video clock to generate a synchronous detection clock;
detecting and obtaining an input clock frequency value according to the reference clock, the synchronous detection clock and the unit time signal when the continuous and stable video clock is input;
(3) and performing clock reconfiguration according to the output video signal configuration parameters configured at the upper layer, the pre-stored PLL parameter table and the input clock frequency value to obtain a configurable IO serial clock for outputting the video clock, a system byte clock for outputting the video clock, an IO serial clock for outputting the video data and a system byte clock for outputting the video data.
8. The video signal transmission clock generating method according to claim 7, further comprising the step (4) of serializing processing;
(4) generating serial bits of the video clock according to the IO serial clock of the output video clock and the system byte clock of the output video clock; and generating the serial bits of the video data according to the IO serial clock for outputting the video data, the system byte clock for outputting the video data and the video input data.
9. The video signal transmission clock generating method according to claim 7 or 8, wherein the step (2) comprises the substeps of:
(2.1) generating a high-precision reference clock; the reference clock has no jitter, is not influenced by the change of the ambient temperature and is not influenced by external interference; generating a pulse signal with continuous period as a unit time signal according to the reference clock;
(2.2) adjusting the phase of the stable video clock by adopting a clock management unit and an IO buffer delay adjusting unit contained in the FPGA device to keep strict synchronization with the reference clock;
adjusting the phase-adjusted video clock and the reference clock to the same global clock domain by using a global clock network in the FPGA device;
(2.3) carrying out M frequency multiplication on the synchronized video clock to generate a synchronous detection clock; m is a natural number not less than 2;
(2.4) buffering the unit time signal with the reference clock as a write clock when a continuous and stable video clock is input, reading the buffered unit time signal with the synchronous detection clock as a read clock, converting the buffered unit time signal into a level state flag, and counting high levels in the level state flag; and dividing the high-level counting value by M to obtain the input clock frequency value detected this time.
10. The video signal transmission clock generating method according to claim 7 or 8, further comprising the step of buffering the detected input clock frequency value as follows:
(a) taking one second as a period, detecting the frequency value at the nth second and storing the detected input clock frequency value into a random access memory RAM 1;
(b) at the (n +1) th second, the frequency detection of the (n +1) th second is continued and the detected input clock frequency value is saved into another random access memory RAM 2; synchronously screening the frequency value stored in the RAM1 at the nth second by adopting a probability majority rule and a normal distribution principle to remove an abnormal frequency value caused by the jump of an input video clock; wherein n is a natural number.
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| CN109521834B (en) * | 2018-10-31 | 2021-04-06 | 武汉精立电子技术有限公司 | DP signal generating device and method |
| CN110896431B (en) * | 2019-12-23 | 2023-12-29 | 中国电子科技集团公司第三十四研究所 | Non-compression high-definition video transmission method and system |
| CN111669648B (en) * | 2020-06-19 | 2022-03-25 | 艾索信息股份有限公司 | Video frequency doubling method |
| CN114520856A (en) * | 2020-11-20 | 2022-05-20 | 西安诺瓦星云科技股份有限公司 | Video time sequence signal generation method, programmable logic device and video control equipment |
| CN112486447B (en) * | 2020-12-01 | 2022-06-07 | 佛吉亚歌乐电子(丰城)有限公司 | DPI clock configuration method, system, terminal and computer storage medium |
| CN112992023A (en) * | 2021-01-29 | 2021-06-18 | 苏州华兴源创科技股份有限公司 | Self-checking method and self-checking circuit of input signal |
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