CN109521834B - DP signal generating device and method - Google Patents
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Abstract
The invention discloses a DP signal generating device and a method, wherein the device comprises a control unit, a clock adjusting unit and a signal adjusting unit; the control unit is used for calculating a frequency division coefficient and a frequency multiplication coefficient according to the output bandwidth required by the module to be tested and the frequency of the first reference clock; configuring a clock adjusting unit according to the frequency multiplication coefficient, and configuring a signal adjusting unit according to the frequency division coefficient; the clock adjusting unit is used for carrying out frequency multiplication processing on the first reference clock according to the frequency multiplication coefficient to obtain a high-frequency clock signal; the signal adjusting unit is used for carrying out frequency division processing on the high-frequency clock signal according to the frequency division coefficient and converting the received DP parallel data into serial data according to the clock after the frequency division processing and outputting the serial data; the invention can carry out frequency conversion processing on the reference clock according to the output bandwidth required by the module to be tested, automatically adapt to liquid crystal modules with different bandwidth requirements, meet the generation of standardized and nonstandard customized DP signals and have general applicability.
Description
Technical Field
The invention belongs to the technical field of signal generation and panel detection, and particularly relates to a DP signal generation method and device.
Background
With the development and update of display technology, the video transmission protocol is continuously updated, the DP protocol of VESA has been gradually developed from version 1.1a to version 1.4 so far, the video transmission bandwidth has been gradually developed from 1.62Gbps/lane to the latest 8.1Gbps/lane, and manufacturers such as dell in the market also start to produce 8K resolution commercial liquid crystal displays corresponding to the 8.1Gbps rate of the DP1.4 protocol. The latest DP1.4 protocol specifies the four standard transmission rates of 1.62/2.7/5.4/8.1Gbps, but for some technically-sophisticated liquid crystal panel manufacturers, they will use custom transmission rates other than these four standard rates based on the DP protocol according to their own requirements.
Under the background of continuous iterative updating of the technology, new requirements are also put forward for traditional liquid crystal panel detection manufacturers. For the detection of the liquid crystal panel using the DP protocol, the liquid crystal panel is not only downward compatible with 1.62Gbps with low speed but also upward compatible with 8.1Gbps with highest speed, and in addition, customized nonstandard solutions are provided for customized speed requirements of different customers.
In the existing panel detection field, for a part of detection equipment (mainly original inherent model equipment) only supporting an old version DP protocol, the highest transmission rate capable of being supported by the detection equipment is 5.4 Gbps; for the recently newly developed DP1.4 detection device, the four standard rates of 1.62/2.7/5.4/8.1Gbps in the DP1.4 protocol can be supported; for some detection devices which adopt special chips such as customized ASIC, FPGA and the like, the detection devices are mainly developed for specific manufacturers to match modules with specific transmission rates, and the detection devices have no general applicability.
Disclosure of Invention
In view of at least one of the drawbacks and needs of the prior art, the present invention provides a DP signal generating apparatus and method, which calculate a frequency conversion coefficient according to a target output bandwidth required by a module to be tested and a frequency of a reference clock, and perform frequency conversion processing on the reference clock according to the frequency conversion coefficient, so as to match a bandwidth of a DP signal output by a signal conditioning unit with the target output bandwidth required by the module to be tested.
To achieve the above object, according to one aspect of the present invention, there is provided a DP signal generating apparatus including a control unit, a clock adjusting unit, and a signal adjusting unit;
the control unit is used for calculating a frequency division coefficient and a frequency multiplication coefficient according to the output bandwidth required by the module to be tested and the acquired frequency of the first reference clock; configuring a clock adjusting unit according to the frequency multiplication coefficient, and configuring a signal adjusting unit according to the frequency division coefficient;
the clock adjusting unit is used for carrying out frequency multiplication processing on the first reference clock according to the frequency multiplication coefficient to obtain a high-frequency clock signal;
and the signal adjusting unit is used for carrying out frequency division processing on the high-frequency clock signal according to the frequency division coefficient and converting the received DP parallel data into serial data according to the clock subjected to frequency division processing and outputting the serial data.
Preferably, the DP signal generating apparatus comprises a clock adjusting unit including at least two clock frequency multiplying modules and a clock selecting module; different clock frequency multiplication modules have different frequency multiplication coefficient adjustment ranges; the control unit selects a matched clock frequency multiplication module according to the calculated frequency multiplication coefficient and configures the clock frequency multiplication module;
the clock selection module is used for selecting the high-frequency clock signal output by the clock frequency doubling module matched with the frequency doubling coefficient according to the frequency doubling coefficient calculated by the control unit and outputting the high-frequency clock signal to the signal adjusting unit.
Preferably, in the DP signal generating apparatus, the signal adjusting unit includes a clock frequency dividing module and a signal output module;
the clock frequency division module is used for carrying out frequency division processing on the high-frequency clock signal output by the clock adjusting unit according to the frequency division coefficient to obtain a second reference clock;
and the signal output module is used for receiving DP parallel data, converting the DP parallel data into serial data according to the second reference clock and outputting the serial data to obtain a DP signal with the output bandwidth adaptive to the bandwidth required by the module to be tested.
Preferably, the DP signal generating apparatus further comprises a clock source for generating the first reference clock.
Preferably, the DP signal generating apparatus has an adjustable frequency of the first reference clock outputted from the clock source, the adjustable range covers 27MHz-270MHz, and the adjustment precision is not lower than 0.05 MHz.
Preferably, the clock frequency of the second reference clock of the DP signal generating device may cover 810MHz-4050 MHz.
Preferably, the control unit of the DP signal generating device is an ARM, NiosII or MicroBlaze processor; the signal adjusting unit adopts a serial deserializer; the clock frequency multiplication module is realized by a phase-locked loop.
According to another aspect of the present invention, there is also provided a DP signal generating method including the steps of:
s1: acquiring a first reference clock, and calculating a frequency division coefficient and a frequency multiplication coefficient according to the output bandwidth required by a module to be tested and the frequency of the first reference clock;
s2: performing frequency multiplication processing on the first reference clock according to the frequency multiplication coefficient to obtain a high-frequency clock signal;
s3: performing frequency division processing on the high-frequency clock signal according to the frequency division coefficient to obtain a second reference clock; and converting the received DP parallel data into serial data according to the second reference clock and outputting the serial data.
Preferably, in the DP signal generating method, the frequency of the first reference clock is adjustable, the adjustment range covers 27MHz-270MHz, and the adjustment precision is not lower than 0.05 MHz.
Preferably, in the DP signal generating method, the clock frequency of the second reference clock may cover 810MHz to 4050 MHz.
In general, compared with the prior art, the above technical solution contemplated by the present invention can achieve the following beneficial effects:
(1) according to the DP signal generation method and device provided by the invention, the frequency conversion coefficient is calculated through the target output bandwidth required by the module to be tested and the frequency of the reference clock, the frequency conversion processing is carried out on the reference clock according to the frequency conversion coefficient, so that the bandwidth of the DP signal output by the signal conditioning unit is matched with the target output bandwidth required by the module to be tested, the generation of the standardized and non-standardized DP signal is realized through closed-loop feedback, the method and device have universality (supporting standard protocol parameters) and customizability (supporting non-standard protocols), the ASIC or FPGA is prevented from being redesigned for the customized DP signal, and the research and development cost and the research and development time in the non-standard requirements are greatly saved;
(2) according to the DP signal generation method and device provided by the invention, the control unit, the clock regulation unit and the signal regulation unit are integrated in the FPGA, so that the method and device have programmability, and can quickly iterate technical schemes according to different application requirements;
(3) according to the DP signal generation method and the DP signal generation device, the clock source, the phase-locked loop and the deserializer which are required by the device are all in conventional specifications, have mass production conditions, and can replace the existing new/old detection equipment.
Drawings
Fig. 1 is a logic block diagram of a DP signal generating apparatus according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a DP signal generating device according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
The invention provides a DP signal generating device, comprising a clock source, a control unit, a clock adjusting unit and a signal adjusting unit;
the clock source is used for outputting a first reference clock to the control unit and the clock adjusting unit;
the control unit is used for calculating a frequency division coefficient and a frequency multiplication coefficient according to a target output bandwidth required by the module to be tested and the frequency of the first reference clock; configuring a clock adjusting unit according to the frequency multiplication coefficient, and configuring a signal adjusting unit according to the frequency division coefficient;
the clock adjusting unit is used for carrying out frequency multiplication processing on the first reference clock according to the frequency multiplication coefficient and outputting a high-frequency clock signal;
the signal adjusting unit is used for carrying out frequency division processing on the high-frequency clock signal output by the clock adjusting unit according to the frequency division coefficient, converting the received DP parallel data into serial data according to the clock signal after the frequency division processing, and outputting the serial data to obtain a DP signal with a target output bandwidth required by the module to be tested.
The frequency conversion coefficient is calculated through the target output bandwidth required by the module to be tested and the frequency of the reference clock, and the frequency conversion processing is carried out on the reference clock according to the frequency conversion coefficient, so that the bandwidth of the DP signal output by the signal adjusting unit is matched with the target output bandwidth required by the module to be tested, and closed loop feedback is formed, thereby realizing the generation of the standardized and non-standardized DP signal, and having universality and customizability.
Furthermore, the clock adjusting unit comprises at least two clock frequency multiplication modules and a clock selection module; different clock frequency multiplication modules have different frequency multiplication coefficient adjustment ranges and can output high-frequency clock signals in different frequency ranges; the control unit selects a proper clock frequency multiplication module according to the calculated frequency multiplication coefficient and adjusts the frequency multiplication coefficient;
the clock selection module is used for selecting matched high-frequency clock signals from the high-frequency clock signals output by the plurality of clock frequency doubling modules under the control of the control unit according to the frequency doubling coefficient calculated by the control unit and outputting the high-frequency clock signals to the signal adjusting unit.
Furthermore, the signal adjusting unit comprises a clock frequency dividing module and a signal output module;
the clock frequency division module performs frequency division processing on the high-frequency clock signal output by the clock adjusting unit according to the frequency division coefficient to obtain a second reference clock; the frequency division coefficient of the clock frequency division module is adjustable, and the frequency division coefficient is adjusted to enable the clock frequency obtained by frequency division of the clock frequency division module to cover 810MHz-4050MHz, so that 1.62Gbps-8.1Gbps full-bandwidth transmission rate output can be realized.
The signal output module is used for receiving the DP parallel data, converting the DP parallel data into serial data according to a second reference clock output by the clock frequency division module, and obtaining a DP signal with the output bandwidth adaptive to the bandwidth required by the module to be tested.
As a preferred embodiment of the invention, the clock frequency of the reference clock output by the clock source is adjustable, the adjusting range is preferably 27MHz-270MHz, and the configurable precision is not lower than 0.05 MHz; when the frequency division coefficient or the frequency multiplication coefficient calculated by the control unit exceeds the frequency regulation range of the clock regulation unit and the signal regulation unit, or the bandwidth of the DP signal output by the signal regulation unit cannot cover 1.62Gbps-8.1Gbps, the generation of the DP signal with the full-bandwidth transmission rate can be realized by regulating the clock frequency output by the clock source or switching the clock frequency multiplication modules in different output ranges.
The DP signal generating apparatus and the operation principle according to the present invention will be described in detail with reference to the following embodiments and the accompanying drawings.
Fig. 2 is a schematic structural diagram of a DP signal generating apparatus provided in this embodiment, as shown in fig. 2, the DP signal generating apparatus includes a clock source, a processor, two Phase-Locked loops (PLLs), a clock selector, and four serializers/deserializers (Serdes); the processor, the phase-locked loop, the clock selector and the serial deserializer are integrated on the FPGA, and the processor can be an embedded processor of the FPGA, including but not limited to ARM, NiosII or MicroBlaze and other processors;
the serializer supports the bandwidth output of not less than 8.1Gbps, a set of clock frequency ranges obtained by frequency division of output clocks of all phase-locked loops through the serializer can cover 810MHz-4050MHz, a clock source (a programmable clock chip) can be configured, the adjusting range of the output clocks can cover 27MHz-270MHz, and the configurable precision is higher than 0.05 MHz; the above required chips are all in the conventional specification in the market.
Because the output clock of a single phase-locked loop can cover the frequency range from 810MHz to 4050MHz after frequency division does not exist at present, the number of the phase-locked loops is at least two; the clock frequency output by the phase-locked loop is mainly limited by an internal voltage-controlled oscillator, generally speaking, an output upper frequency limit Fmax and an output lower frequency limit Fmin exist, and the phase-locked loop cannot obtain the clock frequency covering 810MHz to 4050MHz without limitation; the clock frequency of the phase locked loop output follows the following equation:
FClkout＝FClkin*Y (1)
wherein, FClkout is the clock frequency output by the phase-locked loop, FClkin is the reference clock frequency input by the clock source, and Y is the frequency multiplication coefficient;
different phase-locked loops have different settable numerical values of the frequency multiplication coefficient Y; the frequency multiplication coefficients of the two phase-locked loops are set to be different, so that the output clock frequency ranges of the two phase-locked loops are different, and the clock frequency obtained after frequency division by the serial deserializer can cover 810MHz-4050 MHz.
The serializer comprises a Physical Code Sublayer (PCS) and a Physical media Attachment Sublayer (PMA), wherein a clock frequency divider is arranged in the PMA and can divide the high-frequency clock signal FClkout selectively output by a clock selector to obtain a second reference clock Fclk;
FClk＝FClkout*X (2)
wherein, FClk is the clock frequency output by the deserializer, and X is the frequency division coefficient;
the common frequency division coefficient X is 1, 2, 4, 8, that is, the frequency division is not performed or the high-frequency clock signal is subjected to the frequency division by 2, 4, 8, so that the clock frequency of the high-frequency clock signal FClkout is not changed or reduced to the original clock frequencies of 1/2, 1/4, 1/8, and a second reference clock Fclk is obtained;
after the clock frequency divider performs frequency division processing on the high-frequency clock signal FClkout selectively output by the clock selector to obtain a second reference clock Fclk, the serializer deserializer converts Link Layer parallel data into serial data and outputs the serial data according to the second reference clock Fclk, and 1-bit serial data is respectively sent on the rising edge of the second reference clock and the falling edge of the clock, so that the bandwidth of a DP signal output by the serializer is as follows:
Bandwidth＝2bit*Fclk (3)
the working principle of the DP signal generating device provided in this embodiment to realize full bandwidth output is explained below; according to the basic principle of PLL, assuming that the maximum and minimum clocks output by PLL1 in fig. 2 are Fmax1 and Fmin1, respectively, and the maximum and minimum clocks output by PLL2 are Fmax2 and Fmin2, and the signal bandwidth output by Serdes is calculated according to equation (3), as shown in table 1:
TABLE 1 theoretical clock frequency and output Bandwidth
As can be seen from the above table, the PLL1 can support bandwidths of the sets Bandwidth1 ═ Fmax1 × 2, Fmin1 × 2 ═ Fmax1, Fmin1 [ Fmax1/2, Fmin1/2], [ Fmax1/4, Fmin1/4 ];
in the same way, the bandwidths Bandwidth2 ═ Fmax2 × 2, Fmin2 × 2 ═ Fmax2, Fmin2 [ Fmax2/2, Fmin2/2], [ Fmax2/4, Fmin2/4] that can be supported by the available PLL 2;
the set of bandwidths that all PLLs can eventually support is:
Bandwidth＝Bandwidth1∪Bandwidth2∪…∪BandwidthN (4)
the DP signal generating apparatus provided in this embodiment can support full Bandwidth applications of 1.62Gbps-8.1Gbs as long as the set [1.62Gbps, 8.1Gbps ] ∈ Bandwidth.
The following is illustrated by way of example: it is assumed that the DP signal generating apparatus provided in this embodiment includes two PLLs, where the maximum clock frequency Fmax1 output by the PLL1 is 5000MHz, the minimum clock frequency Fmin1 is 3000MHz, the maximum clock frequency Fmax2 output by the PLL2 is 3200MHz, and the minimum clock frequency Fmin2 is 2000 MHz; serdes may divide the clock signal by 2/4/8; the configurable clock chip is selected as the clock source, and the output requirements of the PLL1 and the PLL2 can be met simultaneously after calculation according to the formula (1); the actual output signal bandwidth of Serdes is calculated according to table 1, as shown in table 2:
TABLE 2 actual clock frequency and output Bandwidth
From table 2 and equation 4, we find that Bandwidth ═ 0.5Gbps, 10Gbps, [1.62Gbps, 8.1Gbps ] ∈ Bandwidth. Therefore, we can support the full bandwidth output of DP by adjusting the clock source, the multiplication factor Y of PLL, the clock selector switching PLL, or setting the division factor of Serdes.
The present embodiment further provides a DP signal generating method, including the following steps:
s1: the processor acquires a first reference clock from the clock source, and calculates a frequency division coefficient and a frequency multiplication coefficient according to the output bandwidth required by the module to be tested and the frequency of the first reference clock;
the processor configures the phase-locked loop according to the frequency multiplication coefficient, and configures each serial deserializer according to the frequency division coefficient; the frequency of the first reference clock output by the clock source is adjustable, the adjusting range covers 27MHz-270MHz, and the adjusting precision is not lower than 0.05 MHz.
S2: the phase-locked loop carries out frequency multiplication processing on the first reference clock according to the frequency multiplication coefficient to obtain a high-frequency clock signal;
s3: each serial deserializer performs frequency division processing on the high-frequency clock signal according to the frequency division coefficient to obtain a second reference clock; converting the received DP parallel data into serial data according to a second reference clock and outputting the serial data; the clock frequency of the second reference clock may cover 810MHz-4050 MHz.
It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (8)
1. A DP signal generating device is characterized by comprising a clock source, a control unit, a clock adjusting unit and a signal adjusting unit;
the clock source is used for generating a first reference clock, the frequency of the first reference clock is adjustable, and the adjusting range covers 27MHz-270 MHz;
the control unit is used for calculating a frequency division coefficient and a frequency multiplication coefficient according to the output bandwidth required by the module to be tested and the acquired frequency of the first reference clock; configuring a clock adjusting unit according to the frequency multiplication coefficient, and configuring a signal adjusting unit according to the frequency division coefficient;
the clock adjusting unit is used for carrying out frequency multiplication processing on the first reference clock according to the frequency multiplication coefficient to obtain a high-frequency clock signal; the clock adjusting unit comprises at least two clock frequency multiplication modules and a clock selection module; different clock frequency multiplication modules have different frequency multiplication coefficient adjustment ranges;
the clock selection module is used for selecting a high-frequency clock signal output by the clock frequency doubling module matched with the frequency doubling coefficient according to the frequency doubling coefficient calculated by the control unit and outputting the high-frequency clock signal to the signal adjusting unit;
the signal adjusting unit is used for carrying out frequency division processing on the high-frequency clock signal according to the frequency division coefficient to obtain a second reference clock; and converting the received DP parallel data into serial data according to the second reference clock and outputting the serial data to obtain a DP signal with the output bandwidth adaptive to the bandwidth required by the module to be tested.
2. The DP signal generating apparatus of claim 1, wherein said signal conditioning unit comprises a clock divider module and a signal output module;
the clock frequency division module is used for carrying out frequency division processing on the high-frequency clock signal output by the clock adjusting unit according to the frequency division coefficient to obtain a second reference clock;
and the signal output module is used for receiving the DP parallel data, converting the DP parallel data into serial data according to the second reference clock and outputting the serial data.
3. The DP signal generating apparatus of claim 1, wherein the adjustment accuracy of said first reference clock is not lower than 0.05 MHz.
4. The DP signal generating apparatus of claim 2, wherein the clock frequency of said second reference clock may cover 810MHz-4050 MHz.
5. The DP signal generating device of claim 1, wherein said control unit is selected from an ARM, nios ii or MicroBlaze processor; the signal adjusting unit adopts a serial deserializer; and the clock frequency multiplication module is realized by a phase-locked loop.
6. A DP signal generating method, comprising the steps of:
s1: acquiring a first reference clock, and calculating a frequency division coefficient and a frequency multiplication coefficient according to the output bandwidth required by a module to be tested and the frequency of the first reference clock; the frequency of the first reference clock can be adjusted, and the adjusting range covers 27MHz-270 MHz;
s2: selecting a clock frequency multiplication module matched with the frequency multiplication coefficient to carry out frequency multiplication processing on the first reference clock to obtain a high-frequency clock signal; different clock frequency multiplication modules have different frequency multiplication coefficient adjustment ranges;
s3: performing frequency division processing on the high-frequency clock signal according to the frequency division coefficient to obtain a second reference clock; and converting the received DP parallel data into serial data according to the second reference clock and outputting the serial data to obtain a DP signal with the output bandwidth adaptive to the bandwidth required by the module to be tested.
7. The DP signal generating method of claim 6, wherein the adjustment accuracy of said first reference clock is not lower than 0.05 MHz.
8. The DP signal generation method of claim 6, wherein the clock frequency of the second reference clock may cover 810MHz-4050 MHz.
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| CN113900477A (en) * | 2020-06-22 | 2022-01-07 | 深圳市中兴微电子技术有限公司 | Clock configuration system and method |
| CN112636751A (en) * | 2020-12-18 | 2021-04-09 | 深圳市紫光同创电子有限公司 | SerDes module clock network architecture |
| CN113573000A (en) * | 2021-07-27 | 2021-10-29 | 武汉帆茂电子科技有限公司 | Displayport HBR3 signal conversion device based on FPGA |
| CN114649011B (en) * | 2022-03-31 | 2024-03-08 | 西安紫光国芯半导体有限公司 | Data transmission device, data transmission method and related equipment of memory |
| CN116318516B (en) * | 2023-05-25 | 2023-08-15 | 芯动微电子科技(珠海)有限公司 | DP protocol-based dynamic accurate realization method and device for regenerated stream clock |
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| CN103338041A (en) * | 2013-07-16 | 2013-10-02 | 广州致远电子股份有限公司 | Synchronous sampling clock generation circuit and method as well as power quality analyzer |
| CN104978917A (en) * | 2015-07-20 | 2015-10-14 | 武汉精测电子技术股份有限公司 | DP video signal automatic test method and device thereof |
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