CN109547017A - A kind of dual loop phase-locked loop analog core circuit and phaselocked loop applied to FPGA - Google Patents
A kind of dual loop phase-locked loop analog core circuit and phaselocked loop applied to FPGA Download PDFInfo
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- CN109547017A CN109547017A CN201811638972.8A CN201811638972A CN109547017A CN 109547017 A CN109547017 A CN 109547017A CN 201811638972 A CN201811638972 A CN 201811638972A CN 109547017 A CN109547017 A CN 109547017A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
- H03L7/0992—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider
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Abstract
The present invention relates to a kind of dual loop phase-locked loop analog core circuits applied to FPGA characterized by comprising low-pass filter, for being integrated and being filtered to current signal, obtain voltage signal, wherein voltage signal includes fine tuning voltage signal and coarse tuning voltage signal；Voltage controlled oscillator, the low-pass filter connects the voltage controlled oscillator with coarse tuning loop by fine tuning loop, frequency modulation process is carried out for adjusting the gain of the voltage controlled oscillator, and to the fine tuning voltage signal and the coarse tuning voltage signal, obtains the first clock signal.The phaselocked loop analog core circuit of the embodiment of the present invention is not under the premise of increasing additional charge pump and filter, utilize the nesting of low-pass filter, realize dual loop phase-locked loop structure, both the requirement of locking time and operating frequency range had been met, output clock jitter can also be significantly reduced, while having saved power consumption and chip area.
Description
Technical field
The present invention relates to programmable logic cells technical fields, more particularly to a kind of double loop locking phase applied to FPGA
Ring moulds intend core circuit and phaselocked loop.
Background technique
Field programmable gate array (Field-Programmable Gate Array, FPGA) is a kind of electricity of semi-custom
Road chip has Resources on Chip abundant for exploitation, and design method is flexible and convenient, has both solved what custom circuit can not upgrade
Deficiency, and overcome the limited disadvantage of conventional programmable device gate circuit number.With the rise of artificial intelligence, to data operation quantity
More stringent requirements are proposed with arithmetic speed, this also results in FPGA (Field-Programmable Gate Array, scene
Programmable gate array) accelerating operation field to play an increasingly important role, many application and service are provided by FPGA
Support can be obviously improved arithmetic speed and efficiency.
As the integrated level of FPGA constantly increases, the on piece clock of high quality is become more and more important.Inside many FPGA
Framework PLL (phaselocked loop) unit is used for various Clock managements, such as injection of removal clock, clock phase adjustment, clocked sequential
Adjustment and frequency synthesis etc..
But the existing performance indexes for needing to meet unified shader under multi-protocols for PLL inside fpga chip,
This proposes stern challenge to PLL analog core framework.It is required that it meets quick lock in, and there is big frequency coverage
With low output jitter, while the power consumption and area of chip are reduced, so designing the PLL mould for meeting FPGA internal clocking performance
Quasi- core architecture is extremely urgent.
Summary of the invention
Therefore, to solve technological deficiency and deficiency of the existing technology, the present invention proposes a kind of applied to the double of FPGA
Looped phase locking ring moulds intend core circuit and phaselocked loop.
Specifically, a kind of dual loop phase-locked loop analog core electricity applied to FPGA that one embodiment of the invention proposes
Road, comprising:
Low-pass filter obtains voltage signal for being integrated and being filtered to current signal, wherein voltage letter
Number include fine tuning voltage signal and coarse tuning voltage signal；
Voltage controlled oscillator, the low-pass filter connect the voltage controlled oscillator with coarse tuning loop by fine tuning loop, use
Frequency modulation(PFM) is carried out in the gain for adjusting the voltage controlled oscillator, and to the fine tuning voltage signal and the coarse tuning voltage signal
Processing, obtains the first clock signal.
In one embodiment of the invention, the low-pass filter includes:
Resistance capacitance module obtains fine tuning voltage signal and feedback voltage for being integrated and being filtered to current signal
Signal；
Transconductance capacitor module, for receiving reference voltage signal and the feedback voltage signal, and according to the feedback electricity
Pressure signal and the reference voltage signal obtain the coarse tuning voltage signal.
In one embodiment of the invention, the resistance capacitance module includes capacitor C1, capacitor C2 and resistance R, wherein
One end of the capacitor C1 is connected to the fine tuning loop, and the other end of the capacitor C1 is connected to ground terminal, the capacitor C2
And the resistance R is sequentially connected in series between the fine tuning loop and ground terminal.
In one embodiment of the invention, the transconductance capacitor module includes operational transconductance amplifier and capacitor C3,
In, the first input end of the operational transconductance amplifier is connected between the resistance R and the capacitor C2, the operational transconductance
Second input terminal of amplifier is connected to reference voltage signal end, and the output end of the operational transconductance amplifier is connected to described thick
Loop is adjusted, one end of the capacitor C3 is connected to the output end of the operational transconductance amplifier, and the other end of the capacitor C3 connects
It is connected to ground terminal.
In one embodiment of the invention, further includes:
Phasing unit connects the voltage controlled oscillator, for carrying out phase adjustment to first clock signal, obtains
To second clock signal.
In one embodiment of the invention, the phasing unit includes selector, connects the voltage controlled oscillator,
Phase adjustment is carried out to first clock signal for obtaining first phase, and according to first phase, obtains second clock letter
Number.
In one embodiment of the invention, the phasing unit further includes phase conversion, connects the choosing
Device is selected, is transmitted to the selector for obtaining second phase, and by the second phase, to pass through first phase and the second phase
Position carries out phase adjustment to first clock signal, obtains second clock signal.
In one embodiment of the invention, further includes:
Charge pump connects the low-pass filter, is converted to electric current for obtaining signal difference, and by the signal difference
Signal.
In one embodiment of the invention, further includes:
Phase frequency detector connects the charge pump, for obtaining reference clock signal and feedback clock signal, and detects ginseng
Examine the signal difference between clock signal and feedback clock signal.
One embodiment of the present of invention also provides a kind of phaselocked loop, including double loop described in above-mentioned any one embodiment
Phaselocked loop analog core circuit.
The embodiment of the present invention, have it is following the utility model has the advantages that
The phaselocked loop analog core circuit of the embodiment of the present invention is not under the premise of increasing additional charge pump and filter, benefit
With the nesting of low-pass filter, dual loop phase-locked loop structure is realized, has both met wanting for locking time and operating frequency range
It asks, can also significantly reduce output clock jitter, while having saved power consumption and chip area.
Through the following detailed description with reference to the accompanying drawings, other aspects of the invention and feature become obvious.But it should know
Road, which is only the purpose design explained, not as the restriction of the scope of the present invention, this is because it should refer to
Appended claims.It should also be noted that unless otherwise noted, it is not necessary to which scale attached drawing, they only try hard to concept
Ground illustrates structure and process described herein.
Detailed description of the invention
Below in conjunction with attached drawing, specific embodiments of the present invention will be described in detail.
Fig. 1 is a kind of structural schematic diagram of phaselocked loop analog core circuit provided in an embodiment of the present invention；
Fig. 2 is the structural schematic diagram of another phaselocked loop analog core circuit provided in an embodiment of the present invention；
Fig. 3 is a kind of structural schematic diagram of low-pass filter provided in an embodiment of the present invention；
Fig. 4 is a kind of structural schematic diagram of phasing unit provided in an embodiment of the present invention；
Fig. 5 is the structural schematic diagram of another phasing unit provided in an embodiment of the present invention.
Specific embodiment
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
Referring to Figure 1, Fig. 1 is a kind of structural schematic diagram of phaselocked loop analog core circuit provided in an embodiment of the present invention.
The embodiment of the present invention provides a kind of dual loop phase-locked loop analog core circuit applied to FPGA, which includes: frequency discrimination mirror
Phase device (PFD, Phase Frequency Detector), charge pump (CP, Charge Pump), low-pass filter (LPF, Low
Pass Filter), voltage controlled oscillator (VCO, Voltage-Controlled Oscillator) and phasing unit
(Phase Adjust), wherein phase frequency detector, charge pump, low-pass filter, voltage controlled oscillator and phasing unit are successively
Connection.
Specifically, phase frequency detector connects charge pump, for obtaining reference clock signal and feedback clock signal, and examines
Survey the signal difference between reference clock signal and feedback clock signal.
Further, reference clock (refclk) and feedback clock (fbclk) are transmitted by the input terminal of phase frequency detector
To phase frequency detector, phase frequency detector detects the signal difference between reference clock and feedback clock, and the signal difference is passed
It transports in charge pump, phase difference of the signal difference between reference clock and feedback clock.Reference clock is as feedback clock
Reference signal, so that feedback clock is adjusted according to reference clock, so that phaselocked loop can export required clock signal.
Specifically, charge pump connects phase frequency detector, is converted to electric current for obtaining signal difference, and by signal difference
Signal (Icp_out).
Further, signal difference is transmitted in charge pump by phase frequency detector, so that charge pump converts signal difference
For current signal, and the current signal is transmitted to low-pass filter.
Specifically, low-pass filter connects charge pump for being integrated and being filtered to current signal and obtains electricity
Press signal, wherein voltage signal includes fine tuning voltage signal (vhf) and coarse tuning voltage signal (vlf)；
Further, low-pass filter is for being integrated and being filtered to current signal, integrated and filtering processing
Voltage signal is formed, which includes coarse tuning voltage signal and fine tuning voltage signal.
Fig. 2 is referred to, low-pass filter includes resistance capacitance module (RC) and transconductance capacitor module (GMC), wherein resistance
The input terminal of capacitance module is connected to the output end of charge pump, and the output end of resistance capacitance module is connected to pressure by fine tuning loop
Control oscillator, the input terminal of transconductance capacitor module is connected to resistance capacitance module and reference signal end, transconductance capacitor module it is defeated
Outlet is connected to voltage controlled oscillator by coarse tuning loop, wherein
Resistance capacitance module obtains fine tuning voltage signal and feedback voltage signal for being filtered to current signal
(vcf), wherein resistance capacitance module is a kind of passive resistor-capacitor filter；
Transconductance capacitor module is believed for receiving reference voltage signal and feedback voltage signal, and according to the feedback voltage
Number and the reference voltage signal obtain the coarse tuning voltage signal.
Fig. 3 is referred to, resistance capacitance module includes capacitor C1, capacitor C2With resistance R, wherein capacitor C1One end be connected to
Fine tuning loop, capacitor C1The other end be connected to ground terminal, capacitor C2With resistance R be sequentially connected in series in fine tuning loop and ground terminal it
Between.Transconductance capacitor module includes operational transconductance amplifier (GM) and capacitor C3, wherein the first input end of operational transconductance amplifier
It is connected to resistance R and capacitor C2Between, the second input terminal of operational transconductance amplifier is connected to reference voltage signal end, mutual conductance fortune
The output end for calculating amplifier is connected to coarse tuning loop, capacitor C3One end be connected to the output end of operational transconductance amplifier, capacitor C3
The other end be connected to ground terminal.
Phase frequency detector comparison reference clock and feedback clock first, by charge pump by reference clock and feedback clock
Difference is converted into the current forms (Icp_out) that low-pass filter can identify, which is low pass filtering device and is accumulated
Divide and be filtered, current signal is changed by fine tuning voltage signal and feedback electricity by the resistance capacitance module of low-pass filter
Signal is pressed, wherein fine tuning voltage signal controls fine tuning loop as fine tuning voltage；On the one hand feedback arrives charge to feedback voltage signal
In pump, another aspect feedback voltage signal generates coarse tuning voltage by transconductance capacitor module, controls coarse tuning loop.Fine tuning voltage
Signal and coarse tuning voltage signal collective effect control voltage controlled oscillator and generate the clock frequency needed in voltage controlled oscillator.Coarse adjustment
Loop passes through PFD, CP, LPF, VCO and divider (frequency divider), and wherein low-pass filter provides two zero pole points, a non-zero
(transconductance capacitor module provides a pole very close to origin to pole, it can be similar to a zero pole point, transconductance capacitor
Module also provides some zero pole points for being far longer than bandwidth, can be not considered, so coarse tuning loop is corresponding low for approximation
Bandpass filter provides two zero pole points, a non-zero pole point), a narrow bandwidth is provided, voltage controlled oscillator passes through coarse tuning loop
High gain is provided, the high-gain collective effect that the narrow broadband and voltage controlled oscillator that low-pass filter provides provide determines lock
The centre frequency (i.e. the frequency of phase-locked loop operation) of phase ring work, expands the coverage area of phase-locked loop operation frequency；Phaselocked loop
Fine tuning loop by RC, VCO and divider in PFD, CP, LPF, wherein the resistance capacitance module in low-pass filter mentions
It has supplied two poles (zero pole point, a non-zero pole point), a zero point, a wide bandwidth is provided, voltage controlled oscillator is logical
It crosses fine tuning loop and provides low gain, the low gain that the wide band and voltage controlled oscillator that low-pass filter provides provide is made jointly
With accelerating locking time, reduce output clock jitter.Phaselocked loop analog core circuit module is connected with frequency divider, is formed
One feedback system, the feedback system when reference clock is consistent with feedback clock phase or one fixed value of difference,
Just by phase lock loop locks.
The circuit is connected by the nested type of low-pass filter, so that coarse tuning loop and fine tuning loop share a charge pump
And low-pass filter, improve the reusability of circuit.On the one hand power consumption is reduced using a charge pump, on the other hand, for
Passive resistor-capacitor filter, the multiplexing of low-pass filter substantially reduce the area of chip, are conducive to the integrated of system.Relatively
In traditional low-pass filter, transconductance capacitor module is added, an input terminal of transconductance capacitor module is connected to feedback voltage letter
Number, another input terminal is connected to reference voltage signal.Reference voltage signal is produced by Vref_gen (generating circuit from reference voltage)
Raw, the value of reference voltage signal is about the half of supply voltage (1/2*vdd), while in order to make up different process different temperatures
Under deviation, reference voltage signal can be configured as different voltage according to the control signal of internal programmable logic unit
Value, the voltage value are positive and negative 20 the percent of 1/2*vdd, and by taking supply voltage 1V as an example, reference voltage signal, which can pass through, to be configured
Position is configured as 0.4V, 0.45V, 0.5V, 0.55V or 0.6.In addition to the framework of application double loop, in order to further increase locking phase
The clock performance of ring output, also utilizes operational transconductance amplifier, feedback voltage signal is forced to level off to Vref (1/2*vdd), and one
The feedback voltage signal is fed back filling for the parasitic capacitance that charge pump current source is reduced to charge pump input terminal to substrate by aspect
Electric discharge problem reduces the charge matching error of charge pump, reduces the shake of cycle of phase-locked loop to eliminate charge shunting.
Another aspect fine tuning voltage signal can finally level off to feedback voltage signal due to the feedback effect of cycle of phase-locked loop, and feed back
Voltage signal levels off to reference voltage signal (1/2*vdd) again, no matter this makes phase-locked loop operation under which type of frequency, carefully
Adjusting the gain of loop can work in the preferable range of a linearity, further increase phaselocked loop to the inhibition energy of shake
Power.Meanwhile the buffer action of transconductance capacitor module, coarse tuning loop and fine tuning loop are isolated well, so that they it
Between be independent of each other under the conditions of different agreement different operating.
Low-pass filter connects voltage controlled oscillator with coarse tuning loop by fine tuning loop, and fine tuning loop is used for fine tuning voltage
It is transmitted to voltage controlled oscillator, coarse tuning loop is used to coarse tuning voltage signal being transmitted to voltage controlled oscillator.Low-pass filter includes two
A output end, respectively the first output end and second output terminal, voltage controlled oscillator include two input terminals, the respectively first input
End and the second input terminal, the first output end of low-pass filter and the first input end of voltage controlled oscillator pass through coarse tuning loop
(coarse_tune) it is connected, the first output end of low-pass filter exports coarse tuning voltage signal to voltage-controlled by coarse tuning loop
In oscillator, the second output terminal of low-pass filter and the second input terminal of voltage controlled oscillator pass through fine tuning loop (fine_
Tune) it is connected, the second output terminal of low-pass filter exports fine tuning voltage signal into voltage controlled oscillator by fine tuning loop.
Wherein, the gain of the voltage controlled oscillator of coarse tuning loop is far longer than the gain of the voltage controlled oscillator of fine tuning loop, such as coarse adjustment ring
The gain of the voltage controlled oscillator on road is 5 times or 10 times of the gain of the voltage controlled oscillator of fine tuning loop, and coarse adjustment gain and fine tuning increase
The size of benefit can be configured according to the specific requirements of user, and the present embodiment does not do concrete restriction to it.
Specifically, voltage controlled oscillator, the low-pass filter connect the voltage-controlled vibration with coarse tuning loop by fine tuning loop
Device is swung, is carried out for adjusting the gain of the voltage controlled oscillator, and to the fine tuning voltage signal and the coarse tuning voltage signal
Frequency modulation process obtains the first clock signal.
Further, voltage controlled oscillator is used to carry out frequency modulation process to voltage signal, obtains the first clock signal.Pressure
Control oscillator may include the output of the road i, wherein i is the integer more than or equal to 1, and i is even number.
Coarse tuning voltage signal transmits most voltage controlled oscillator by coarse tuning loop, and biggish gain can be provided for phaselocked loop
With lower bandwidth, the centre frequency of voltage controlled oscillator can be quickly determined, expand phase-locked loop frequency coverage area, fine tuning electricity
It presses signal by fine tuning loop transfer most voltage controlled oscillator, lesser gain and higher bandwidth can be provided for phaselocked loop,
The fine tuning loop plays a decisive role to the bandwidth of phase-locked loop apparatus, and can reduce the shake of phase-locked loop apparatus, accelerates lock
It fixes time.
Specifically, phasing unit connects voltage controlled oscillator, for carrying out phase adjustment to the first clock signal, obtains
To second clock signal.
Further, for carrying out phase adjustment to the first clock signal, second clock signal is obtained.Phasing unit
It may include the output of the road j, wherein j is the integer more than or equal to 1, and j is more than or equal to the output channel of entire phase-locked loop apparatus
Number.
Wherein, phasing unit includes two kinds of phase adjustment modes, the first is when carrying out by selector to first
Clock signal carries out phase adjustment, and second is to be adjusted by selector and phase conversion (phase shift).
For the first phase adjustment mode, Fig. 4 is referred to, phasing unit includes selector, the selector
First input end connection voltage controlled oscillator output end, the second input terminal of the selector is connected to static configuration position SDX < 2:
0 > (by taking the output of four tunnels as an example, X A/B/C/D), phasing unit is for obtaining first phase, and according to first phase to the
One clock signal carries out phase adjustment, obtains second clock signal.The first phase adjustment mode belongs to a kind of static configuration.
First phase is user's set configuration bit according to demand, i.e., required for phaselocked loop output clock signal phase
Position size, selector is according to the demand corresponding selection phase size to be output of configuration bit, such as the required phase of configuration bit
Size is 45, then selector forces the first clock signal that VCO is exported to be adjusted to the second clock signal progress that phase is 45
Output.Common this usually adjustable phase relation of phaselocked loop being applied in FPGA is with 45 degree of increases for step-length.
For example, referring to Fig. 5, for the present embodiment with the output channel of phase-locked loop apparatus for 4 tunnels, selector selects 1 selector for 8
(8mux1), 8 phases for selecting 1 selector correspondence that can choose are 0,45,90,135,180,225,270,315, and i=8, j=4 are
Example is illustrated, wherein SDA<2:0>, SDB<2:0>, SDC<2:0>, SDD<2:0>are respectively that 4 road output channels are corresponding
Configuration bit, if certain all the way output channel phase determine, selector directly according to configuration bit select required for export phase
Position, as SDA<2:0>corresponds to the configuration bit of first via output channel, and then, first via output channel needs 81 selector is selected to select
The 4th phase (i.e. 135) is selected, then the configuration bit of SDA<2:0>may be configured as 011, the phase adjusted at this time are as follows: SDA<2:0>/8*
360。
For second of phase adjustment mode, Fig. 5 is referred to, phasing unit further includes phase conversion,
The third input terminal of the output end connection selector of phase conversion, phase conversion are used to obtain second phase, and will
Second phase is transmitted to selector, to carry out phase adjustment to the first clock signal by first phase and second phase, obtains
Second clock signal.
The input terminal of phase conversion is connected to the first output end of phase control module, wherein phase control module
May be implemented to receive in system operation and need to carry out the signal of phase adjustment, and by the signal control corresponding part into
Mobile state phase adjustment, such as when needing to carry out dynamic phasing adjustment to the first clock signal, then phase control module controls phase
Position conversion module output need dynamic adjustment phase size, i.e., phase conversion according to phase control module acquisition need into
The second phase of Mobile state adjustment, which is transmitted to selector by phase conversion, then selector is initial the
The phase that phase size corresponding to second phase is second clock signal, such as first phase are added on the basis of one phase
The corresponding phase size of SDA<2:0>is 135, i.e. SDA<2:0>is 011, and the corresponding phase size of second phase PHA<2:0>is
135, i.e. PHA<2:0>they are 011, then the phase of second clock signal is 270, at this time phase adjustment step-length are as follows: (SDA<2:0>+
PHA<2:0>)/8*360.
It will be appreciated that, the dynamic control bit signal (DYNMAICCONTROL) for controlling phase control module may be from inside
Programmed logical module or external dynamic control interface.
The embodiment of the present invention in order to balance in the case of different application the locking time of phase-locked loop apparatus, output jitter situation,
The relationship of stability, the gain of the bandwidth of the low-pass filter of the phase-locked loop apparatus, the electric current of charge pump, voltage controlled oscillator
Dynamic or static configuration are carried out by the configuration bit of FPGA, wherein configuration bit is to the required numerical values recited in each part, such as
The size of the bandwidth of low-pass filter.
The phaselocked loop analog core circuit of the embodiment of the present invention increases phasing unit, can be according to fpga chip
Different application environment carries out dynamic or static configuration, is wanted with meeting the application of output clock of different frequency, out of phase
It asks.
The phaselocked loop analog core circuit of the embodiment of the present invention is not under the premise of increasing additional charge pump and filter, benefit
With the nesting of low-pass filter, dual loop phase-locked loop structure is realized, has both met wanting for locking time and operating frequency range
It asks, can also significantly reduce output clock jitter, while having saved power consumption and chip area.
The embodiment of the present invention also provides a kind of phaselocked loop, which has phaselocked loop analog core electricity described above
Road.
The above content is a further detailed description of the present invention in conjunction with specific preferred embodiments, and it cannot be said that
Specific implementation of the invention is only limited to these instructions.For those of ordinary skill in the art to which the present invention belongs, exist
Under the premise of not departing from present inventive concept, a number of simple deductions or replacements can also be made, all shall be regarded as belonging to of the invention
Protection scope.
Claims (10)
1. a kind of dual loop phase-locked loop analog core circuit applied to FPGA characterized by comprising
Low-pass filter obtains voltage signal for being integrated and being filtered to current signal, wherein voltage signal packet
Include fine tuning voltage signal and coarse tuning voltage signal；
Voltage controlled oscillator, the low-pass filter connects the voltage controlled oscillator with coarse tuning loop by fine tuning loop, for adjusting
The gain of the whole voltage controlled oscillator, and the fine tuning voltage signal and the coarse tuning voltage signal are carried out at frequency modulation(PFM)
Reason, obtains the first clock signal.
2. analog core circuit according to claim 1, which is characterized in that the low-pass filter includes:
Resistance capacitance module obtains fine tuning voltage signal and feedback voltage signal for being integrated and being filtered to current signal；
Transconductance capacitor module is believed for receiving reference voltage signal and the feedback voltage signal, and according to the feedback voltage
Number and the reference voltage signal obtain the coarse tuning voltage signal.
3. analog core circuit according to claim 2, which is characterized in that the resistance capacitance module includes capacitor C1, electricity
Hold C2With resistance R, wherein the capacitor C1One end be connected to the fine tuning loop, the capacitor C1The other end be connected to and connect
Ground terminal, the capacitor C2And the resistance R is sequentially connected in series between the fine tuning loop and ground terminal.
4. analog core circuit according to claim 3, which is characterized in that the transconductance capacitor module includes operational transconductance
Amplifier and capacitor C3, wherein the first input end of the operational transconductance amplifier is connected to the resistance R and the capacitor C2
Between, the second input terminal of the operational transconductance amplifier is connected to reference voltage signal end, the operational transconductance amplifier
Output end is connected to the coarse tuning loop, the capacitor C3One end be connected to the output end of the operational transconductance amplifier, institute
State capacitor C3The other end be connected to ground terminal.
5. analog core circuit according to claim 1, which is characterized in that further include:
Phasing unit connects the voltage controlled oscillator, for carrying out phase adjustment to first clock signal, obtains the
Two clock signals.
6. analog core circuit according to claim 5, which is characterized in that the phasing unit includes selector,
The voltage controlled oscillator is connected, phase is carried out to first clock signal for obtaining first phase, and according to first phase
Adjustment, obtains second clock signal.
7. analog core circuit according to claim 6, which is characterized in that the phasing unit further includes that phase turns
Block is changed the mold, the selector is connected, is transmitted to the selector for obtaining second phase, and by the second phase, with logical
It crosses first phase and second phase and phase adjustment is carried out to first clock signal, obtain second clock signal.
8. analog core circuit according to claim 1, which is characterized in that further include:
Charge pump connects the low-pass filter, is converted to electric current letter for obtaining signal difference, and by the signal difference
Number.
9. analog core circuit according to claim 8, which is characterized in that further include:
Phase frequency detector connects the charge pump, for obtaining reference clock signal and feedback clock signal, and when detecting reference
Signal difference between clock signal and feedback clock signal.
10. a kind of phaselocked loop, which is characterized in that including double loop locking phase described in claim 1 to claim 9 any one
Ring moulds intend core circuit.
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| CN201811638972.8A CN109547017A (en) | 2018-12-29 | 2018-12-29 | A kind of dual loop phase-locked loop analog core circuit and phaselocked loop applied to FPGA |
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| CN201811638972.8A CN109547017A (en) | 2018-12-29 | 2018-12-29 | A kind of dual loop phase-locked loop analog core circuit and phaselocked loop applied to FPGA |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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| CN112636748B (en) * | 2020-11-30 | 2023-11-07 | 深圳市国微电子有限公司 | Spread spectrum clock circuit and communication chip |
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