CN103178840B - A kind of phase-locked loop circuit and its method of work - Google Patents
A kind of phase-locked loop circuit and its method of work Download PDFInfo
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Abstract
The present invention discloses a kind of phase-locked loop circuit, it includes phaselocked loop core cell and phase lock control unit, when the phase-locked loop circuit is in emission state, the phaselocked loop core cell passes through integral frequency divisioil open loop mode output signal under the control of the phase lock control unit；When the phase-locked loop circuit is in reception state, the phaselocked loop core cell passes through fractional frequency division closed loop mode output signal under the control of the phase lock control unit.There is provided a kind of more perfect phase-locked loop circuit by above technical scheme by the present invention.
Description
Technical Field
The present invention relates to the field of communications, and in particular, to a phase-locked loop circuit and a method for operating the same.
Background
A Phase-Locked Loop (PLL) frequency synthesizer is one of core components of a radio frequency transceiver, and modulates transmission data onto a carrier frequency when the radio frequency transceiver is in a transmission state; in a receiving state, the PLL frequency synthesizer generates a local oscillation signal for mixing with the received signal to obtain a demodulated signal.
At present, a PLL frequency synthesizer can be divided into an integer-N frequency division and a fractional frequency division according to whether the frequency division coefficient of a frequency divider changes dynamically and randomly, the integer-N frequency division PLL frequency synthesizer has a simple structure, and has good open-loop transmission performance but poor reception performance, and the fractional-N frequency division PLL frequency synthesizer has good reception performance but needs to add a complex correction circuit during closed-loop transmission.
Disclosure of Invention
The invention provides a more perfect phase-locked loop circuit and a working method thereof.
A phase-locked loop circuit includes a phase-locked loop core unit and a phase-locked loop control unit; when the phase-locked loop circuit is in a transmitting state, the phase-locked loop core unit outputs signals through an integer frequency division open-loop mode under the control of the phase-locked loop control unit; when the phase-locked loop circuit is in a receiving state, the phase-locked loop core unit outputs signals through a decimal frequency division closed-loop mode under the control of the phase-locked loop control unit.
In an embodiment of the present invention, the phase-locked loop core unit includes an integer frequency division module and a fractional frequency division module, and the phase-locked loop control unit is configured to turn on the integer frequency division module and turn off the fractional frequency division module when the phase-locked loop circuit is in a transmitting state, and turn on the fractional frequency division module and turn off the integer frequency division module when the phase-locked loop circuit is in a receiving state.
In an embodiment of the present invention, the phase-locked loop core unit includes a phase discriminator, a loop filter, a voltage-controlled oscillator, a digital-to-analog converter, and a modulator; the integer frequency division module comprises the phase discriminator, a loop filter, a voltage-controlled oscillator, a frequency divider and a digital-to-analog converter, wherein the phase discriminator, the loop filter, the voltage-controlled oscillator and the frequency divider are sequentially connected to form a loop, the digital-to-analog converter is connected with the voltage-controlled oscillator, the digital-to-analog converter receives transmission data, the frequency divider receives a channel selection signal, the phase discriminator receives a frequency division reference signal, and the voltage-controlled oscillator outputs an output signal of the phase-; the decimal frequency division module is including connecting gradually the formation loop phase discriminator, loop filter, voltage controlled oscillator and frequency divider, and with the modulator that the frequency divider links to each other, wherein the modulator receives the channel selection signal, the phase discriminator receives the frequency division reference signal, voltage controlled oscillator output phase-locked loop circuit's output signal.
In an embodiment of the present invention, the pll control unit includes: the first switch is connected with the input end of the phase discriminator and is used for selecting the frequency division reference frequency; the second switch is connected with the input end of the frequency divider and is used for selecting a channel selection signal; when in a transmitting state, the first switch selects an integer frequency division reference frequency, and the second switch selects an integer channel selection signal; when in a receiving state, the first switch selects a fractional division reference frequency and the second switch selects a fractional channel selection signal.
In an embodiment of the present invention, the pll control unit further includes a third switch connected to the input terminal of the modulator, for selecting whether to input the transmission data; when in a transmitting state, the first switch selects an integer frequency division reference frequency, the second switch selects an integer channel selection signal, or the first switch selects a decimal frequency division reference frequency, the second switch selects a decimal channel selection signal, and the third switch controls transmitting data to be input into the modulator; when in a receiving state, the first switch selects an integer division reference frequency and the second switch selects an integer channel selection signal, or the first switch selects a fractional division reference frequency and the second switch selects a fractional channel selection signal.
When the phase-locked loop circuit is in a transmitting state, the phase-locked loop circuit outputs signals through an integer frequency division open-loop mode; when the receiving state is achieved, the signal is output through the fractional frequency division closed-loop mode, the better transmitting performance of the integer frequency division open-loop mode and the better receiving performance of the fractional frequency division closed-loop mode are fully utilized, and the respective defects are avoided. The phase-locked loop circuit does not simply piece together or superpose two frequency division circuits, but makes full use of phase-locked loop core units (such as a phase discriminator, a loop filter, a voltage-controlled oscillator and a frequency divider) which can be multiplexed, thereby achieving the minimization of the circuit area.
Drawings
FIG. 1 is a diagram illustrating a phase-locked loop circuit according to an embodiment of the present invention;
FIG. 2 is a diagram illustrating a phase-locked loop circuit according to an embodiment of the present invention;
FIG. 3 is a diagram illustrating a phase-locked loop circuit according to an embodiment of the invention.
Detailed Description
Fig. 1 is a schematic diagram of a phase-locked loop circuit according to an embodiment of the invention, please refer to fig. 1:
a phase-locked loop circuit comprises a phase-locked loop core unit 1 and a phase-locked loop control unit 2, wherein the phase-locked loop core unit 1 can comprise an integer frequency division module and a decimal frequency division module, the phase-locked loop control unit 2 can comprise a channel selection module, a frequency division reference frequency selection module and a parameter setting and adjusting module, and when the phase-locked loop circuit is in a transmitting state, the phase-locked loop core unit 1 outputs signals through an integer frequency division open-loop mode under the control of the three modules of the phase-locked loop control unit 2; when the phase-locked loop circuit is in a receiving state, the phase-locked loop core unit 1 outputs signals in a fractional frequency division closed-loop mode under the control of three modules of the phase-locked loop control unit 2.
Taking the PLL frequency synthesizer applied in the rf transceiver as an example, a hybrid PLL frequency synthesizer is proposed. This phase-locked loop circuit includes phase-locked loop core unit 1 and phase-locked loop control unit 2, phase-locked loop core unit 1 includes phase discriminator 11, loop filter 12, voltage controlled oscillator 13, digital-to-analog converter 14, frequency divider 15 and modulator 16, phase-locked loop control unit 2 includes first switch S1 that links to each other with phase discriminator 11 input for select the frequency division reference frequency, second switch S2 that links to each other with frequency divider 15 input for select the channel selection signal, the phase-locked loop circuit structure of this embodiment is shown in FIG. 2: wherein,
an input end of the phase detector 11 is selectively connected with an integer frequency division reference frequency Fref0 or a decimal frequency division reference frequency Fref1 through a first switch S1, an output end of the phase detector 11 is selectively connected with an input end of the loop filter 12 through a fourth switch S4, an output end of the loop filter 12 is connected with an input end of the voltage-controlled oscillator 13, an input end of the digital-to-analog converter 14 is connected with transmitting data, an output end of the digital-to-analog converter 14 is selectively connected with the other input end of the voltage-controlled oscillator 13 through a fifth switch S5, an output end of the voltage-controlled oscillator 13 is connected with the other input end of the phase detector 11 through a frequency divider 15, the frequency divider 15 is further selectively connected with an integer channel selection signal N0 or an output end of the modulator 16 through a second switch S2, an input end of the modulator 16 is connected with a decimal channel selection signal N1+ K, and the decimal channel selection signal N1+ K is processed by the modulator 16.
When the radio frequency transceiver is in a transmitting state, in a frequency locking stage, the fourth switch S4 is closed, the fifth switch S5 is opened, the phase detector 11, the loop filter 12, the voltage-controlled oscillator 13 and the frequency divider 15 are sequentially connected to form a loop, the frequency divider 15 selects an integer channel selection signal N0 through the second switch S2, frequency division is performed on a frequency signal output by the voltage-controlled oscillator 13 according to the integer channel selection signal, an internal feedback signal is output to the phase detector 11, the phase detector 11 selects an integer frequency division reference frequency Fref0 through the first switch S1, a voltage signal is output according to a phase difference between the Fref0 and the internal feedback signal, the voltage signal forms a control voltage of the voltage-controlled oscillator 13 after passing through the loop filter 12, and the voltage-controlled oscillator 13 adjusts the frequency of the output signal according to the control voltage; after the frequency locking is completed, the data is transmitted in the integer frequency division open loop mode, i.e. the fourth switch S4 is opened, the fifth switch S5 is closed, and the transmitted data is modulated by the analog-to-digital converter 14 and the voltage-controlled oscillator 13 and then transmitted.
When the radio frequency transceiver is in a receiving state, in a frequency locking stage, the fourth switch S4 is closed, the fifth switch S5 is opened, the phase detector 11, the loop filter 12, the voltage-controlled oscillator 13 and the frequency divider 15 are sequentially connected to form a loop, the frequency divider 15 selects an N1+ N (t) signal which is accessed to a decimal channel selection signal N1+ K and is output after being processed by the modulator 16 through the second switch S2, the frequency divider 15 divides the frequency signal output by the voltage-controlled oscillator 13 according to the N1+ N (t) signal, outputs an internal feedback signal to the phase detector 11, the phase detector 11 selectively switches in a decimal frequency division reference frequency Fref1 through a first switch S1, outputting a voltage signal according to the phase difference between Fref1 and the internal feedback signal, wherein the voltage signal forms a control voltage of the voltage-controlled oscillator 13 after passing through the loop filter 12, and the voltage-controlled oscillator 13 adjusts the frequency of the output signal according to the control voltage; after the frequency locking is completed, the voltage-controlled oscillator 13 outputs a local oscillation signal, that is, a local oscillation signal for mixing with a reception signal is output in a fractional-n closed-loop mode when the radio frequency transceiver is in a reception state.
In the embodiment, preferably, Fref0 < Fref1, even Fref1 is far greater than Fref0, such as Fref 1-16 MHz, Fref 0-500 KHz; preferably, N0 > N1, N0 is even much larger than N1, N0 and N1 are integer values, N0 is an integer division ratio, a fractional division ratio includes an integer part N1 and a fractional part K, N1+ N (T) may be data with a multiple bit width, where N (T) has randomness and has a long-term average value of K, and assuming that K is 20 bits and the operating clock period T of modulator 16 is 10ns, the value of N (T) modulated by modulator 16 changes at each operating clock, but the period T of the change is 2 ns20Ts, 2 consecutive to n (t)20The values are averaged to a value K, e.g., 0.75-3/4, and K is represented by two bits as K-2' b11, the output of the modulator may be 1, 1, 1, 0 in sequence for 4 consecutive clock cycles, with the value averaged over four cycles being 0.75, equal to K.
The phase-locked loop control unit 2 may further be configured to set or adjust configuration parameters of the phase detector 11, the loop filter 12, the voltage-controlled oscillator 13, the digital-to-analog converter 14, the frequency divider 15, and/or the modulator 16, and in different operation modes, the phase-locked loop control unit 2 may adjust the configuration parameters of the phase detector 11, the loop filter 12, the voltage-controlled oscillator 13, the digital-to-analog converter 14, the frequency divider 15, and/or the modulator 16 to adapt to a current frequency division mode.
With the phase-locked loop circuit structure of the present embodiment, in a receiving state, in addition to outputting a local oscillation signal for mixing with a received signal in a fractional-N closed-loop mode, an integer-N closed-loop mode may be selected to output a local oscillation signal for mixing with a received signal, that is, an integer-N reference frequency Fref0 is selected in S1, an integer channel selection signal N0 is selected in S2, S4 is turned off, S5 is turned off, the phase detector 11, the loop filter 12, the voltage-controlled oscillator 13, and the frequency divider 15 are sequentially connected to form a loop, so as to perform frequency locking, and after the frequency locking is completed, the voltage-controlled oscillator 13 may generate a stable local oscillation signal for signal reception.
Fig. 3 is a schematic diagram of a phase-locked loop circuit according to an embodiment of the invention, please refer to fig. 3:
in this embodiment, a third switch S3 is added to the circuit shown in fig. 2, the transmission data can be selected through S3 whether to send the transmission data to the modulator 16 for modulation, if sending to the modulator 16 for modulation, it is essentially two-point modulation of the transmission data, if sending to the modulator 16 for modulation, it is the N1 '+ N' (t) signal that the modulator 16 outputs to the frequency divider 15 after changing the K value. By adopting the phase-locked loop circuit structure, when in a transmitting state, an integer frequency division open-loop mode can be selected and used, and also two-point modulation output transmitting data can be selected through a decimal frequency division closed-loop mode, namely a decimal frequency division reference frequency Fref1 is selected through S1, a second switch S2 selects an N1 '+ N' (t) signal, a fourth switch S4 is closed, a fifth switch S5 is opened, a third switch S3 is closed, the phase discriminator 11, the loop filter 12, the voltage-controlled oscillator 13 and the frequency divider 15 are sequentially connected to form a loop, and after frequency locking is completed, the voltage-controlled oscillator 13 can output the modulated transmitting data. When the receiving state is in, besides the local oscillator signal output in the fractional-N closed-loop mode, the local oscillator signal output in the integer-N closed-loop mode may also be selected, that is, the integer-N reference frequency Fref0 is selected through the first switch S1, the integer channel selection signal N0 is selected through the second switch S2, the fourth switch S4 is turned off, the fifth switch S5 is turned off, the phase detector 11, the loop filter 12, the voltage-controlled oscillator 13 and the frequency divider 15 are sequentially connected to form a loop, so as to complete frequency locking, and after the frequency locking is completed, the voltage-controlled oscillator 13 may generate a stable local oscillator signal for signal reception.
The frequency divider of the present invention may be a multi-modulus frequency divider; the modulator may be a Sigma-Delta modulator (Sigma Delta modulator); the invention provides a phase-locked loop circuit for realizing integer and decimal frequency division modes, which outputs signals through an integer frequency division open-loop mode when in a transmitting state; when the phase-locked loop is in a receiving state, the integer frequency division open-loop mode and the decimal frequency division closed-loop mode are integrated in the same phase-locked loop circuit through the output signal of the decimal frequency division closed-loop mode, not only the multiplexing of basic components such as a phase discriminator, a loop filter, a voltage-controlled oscillator and a frequency divider is realized, but also the transmitting performance of the integer frequency division open-loop mode and the better receiving performance of the decimal frequency division closed-loop mode are fully utilized, and the respective defects are avoided.
The foregoing is a more detailed description of the present invention that is presented in conjunction with specific embodiments, and the practice of the invention is not to be considered limited to those descriptions. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (5)
1. A phase-locked loop circuit is characterized by comprising a phase-locked loop core unit and a phase-locked loop control unit;
when the phase-locked loop circuit is in a transmitting state, the phase-locked loop core unit outputs signals through an integer frequency division open-loop mode under the control of the phase-locked loop control unit;
when the phase-locked loop circuit is in a receiving state, the phase-locked loop core unit outputs signals in a fractional frequency division closed-loop mode under the control of the phase-locked loop control unit;
the phase-locked loop core unit comprises a phase discriminator, a loop filter, a voltage-controlled oscillator, a digital-to-analog converter, a frequency divider and a modulator;
the integer frequency division module comprises the phase discriminator, a loop filter, a voltage-controlled oscillator and a frequency divider which are sequentially connected to form a loop, the frequency divider selects to receive an integer channel selection signal, the phase discriminator selects to receive an integer frequency division reference frequency, the integer frequency division module further comprises a digital-to-analog converter, the input end of the digital-to-analog converter receives transmission data, and the voltage-controlled oscillator also selects to be connected with the output end of the digital-to-analog converter to output an output signal of the phase-locked loop circuit;
the decimal frequency division module comprises a phase discriminator, a loop filter, a voltage-controlled oscillator and a frequency divider which are sequentially connected to form a loop, and further comprises a modulator, wherein the modulator receives a decimal channel selection signal, the frequency divider selectively receives a signal output by the modulator after processing the decimal channel selection signal, the phase discriminator selectively receives a decimal frequency division reference frequency, and the voltage-controlled oscillator outputs a local oscillation signal used for mixing with the received signal;
the phase-locked loop control unit is used for starting the integer frequency division module and closing the decimal frequency division module when the phase-locked loop circuit is in a transmitting state, and starting the decimal frequency division module and closing the integer frequency division module when the phase-locked loop circuit is in a receiving state.
2. The phase-locked loop circuit of claim 1, wherein the phase-locked loop control unit comprises:
the first switch is connected with the input end of the phase discriminator and is used for selecting the frequency division reference frequency;
and the second switch is connected with the input end of the frequency divider and is used for selecting the channel selection signal.
3. The phase locked loop circuit of claim 2 wherein the phase locked loop control unit further comprises a third switch coupled to the modulator input for selecting whether transmit data is input.
4. A method of operating a phase-locked loop circuit, comprising:
when the phase-locked loop circuit is in a transmitting state, the phase-locked loop circuit outputs signals through an integer frequency division open-loop mode;
when the phase-locked loop circuit is in a receiving state, the phase-locked loop circuit outputs signals through a decimal frequency division closed-loop mode;
the phase-locked loop circuit of claim 1.
5. The method of operating a phase-locked loop circuit as claimed in claim 4, wherein the phase-locked loop circuit is the phase-locked loop circuit of claim 2, the method further comprising:
when in a transmitting state, the first switch selects an integer frequency division reference frequency, and the second switch selects an integer channel selection signal;
when in a receiving state, the first switch selects a fractional division reference frequency and the second switch selects a fractional channel selection signal.
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| CN107968687B (en) * | 2016-10-20 | 2021-08-24 | 国民技术股份有限公司 | Calibration circuit and calibration method for two-point modulation transmitter |
| CN106774364B (en) * | 2016-12-14 | 2023-09-15 | 歌尔科技有限公司 | Unmanned aerial vehicle operation control method and unmanned aerial vehicle |
| CN107294531B (en) * | 2017-06-21 | 2020-09-11 | 上海兆芯集成电路有限公司 | Phase locked loop and frequency divider |
| CN109698697B (en) * | 2018-12-29 | 2023-11-14 | 西安智多晶微电子有限公司 | Phase-locked loop device applied to FPGA chip and FPGA chip |
| CN110324051B (en) * | 2019-06-24 | 2021-11-16 | 成都振芯科技股份有限公司 | Method and device for enhancing adaptability of transmission channel orthogonal correction |
| CN111245472B (en) * | 2020-04-26 | 2020-08-04 | 杭州城芯科技有限公司 | Radio frequency transceiver chip, and synchronization system and method for radio frequency transceiver chip |
| CN113489487B (en) * | 2021-06-22 | 2023-07-07 | 中国电子科技集团公司第二十九研究所 | Integrated VCO type phase discriminator and in-loop mixing type phase-locked loop circuit |
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