CN107968687B - Calibration circuit and calibration method for two-point modulation transmitter - Google Patents
Calibration circuit and calibration method for two-point modulation transmitter Download PDFInfo
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Abstract
The invention relates to a calibration circuit and a calibration method of a two-point modulation transmitter, wherein the circuit comprises the following components: the two-point modulation phase-locked loop system comprises a two-point modulation phase-locked loop system, a signal input circuit, a power amplifier and a gain self-calibration circuit; the method comprises the following steps: after the phase-locked loop is locked at the working frequency, calibration data are transmitted, the gain difference of a high-low path is calculated by using the low-pass branch as a reference through the gain self-calibration circuit, the control word of the low-pass filter is adjusted in a different direction by using a special calibration time sequence, the output amplitude of the digital-to-analog converter is changed to realize the gain matching of the two branches, and the calibration process is completed by configuring a delay control word. The invention can realize the calibration of delay matching, has the function of automatic gain calibration, and solves the problems of large resource consumption, long calibration time and frequency offset caused by temperature great change in the traditional two-point modulation frequency offset calibration.
Description
Technical Field
The invention relates to a transmitter suitable for low power consumption, in particular to a calibration circuit and a calibration method of a two-point modulation transmitter.
Background
There are three main types of commonly used direct transmitters based on phase locked loops: (1) a phase-locked loop based out-of-band transmitter; (2) a phase-locked loop based in-band transmitter; (3) a phase-locked loop based two-point modulation transmitter. The two-point modulation transmitter based on the phase-locked loop overcomes the defect of weak anti-interference capability of an out-of-band transmitter, breaks the limitation of the in-band transmitter by the loop bandwidth of the phase-locked loop, and is more suitable for a wireless communication device with high-quality transmission and low power consumption.
As shown in fig. 7, the two-point modulation phase-locked loop is composed of a low-pass branch (a1) for controlling a sigma-delta Modulator (sigma-delta Modulator) by Digital modulation (Digital Modulator) of a transmission signal, and a high-pass branch (a2) for controlling an input end of a Voltage Controlled Oscillator (VCO) by a Digital-to-analog converter (DAC) and a low-pass filter (LPF), and the two-point modulation phase-locked loop and a Power Amplifier (PA) together constitute the two-point modulation transmitter.
Although the two-point modulation transmitter based on the phase-locked loop breaks the limitation of the loop bandwidth of the phase-locked loop and enhances the out-of-band anti-jamming capability, because signals are transmitted by the high-low-pass branch, the problems of delay and gain matching of the low-pass branch (A1) and the high-pass branch (A2) are caused under the condition of Process, Voltage and Temperature (PVT) variation.
Delay matching problem: the signals pass through the two branches and are uniformly output behind the VCO, so that the two signals are required to be synchronous at the VCO output, and the phase output of the signals of the two branches is asynchronous under the PVT change condition.
The gain matching problem is as follows: the low-pass branch (a1) can be implemented with digital codes (Verilog) for precise design; however, the high-pass branch (a2) controls the VCO by the voltage output by the digital-to-analog converter and the low-pass filter to implement frequency offset, and under the PVT variation condition, the frequency offset of the high-pass branch (a2) is not controllable, which causes the frequency offset mismatch of the two branches, and may seriously deteriorate the communication quality.
In 2009, a calibration transmitter is published in ieee (institute of Electrical and Electronics engineers), as shown in fig. 8, the calibration method quantizes the loop filter voltage through a high-precision ADC, and implements a calibration function through a gain and phase compensation module, and the ADC quantizes the noise signal of the loop filter voltage together without processing the loop filter output voltage, thereby introducing a calibration error.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: when signals are transmitted in the high-low-pass branch, delay and gain matching of the low-pass branch and the high-pass branch are poor due to process, voltage and temperature changes.
To solve the above technical problem, the present invention provides a calibration circuit for a two-point modulation transmitter, the calibration circuit comprising:
the two-point modulation phase-locked loop circuit comprises a two-point modulation phase-locked loop circuit, a signal input circuit, a power amplifier and a gain self-calibration circuit;
the signal input circuit inputs signals to the two-point modulation phase-locked loop circuit; the gain self-calibration circuit adjusts a signal input by the signal input circuit; the two-point modulation phase-locked loop circuit outputs a signal to the power amplifier;
the signal input circuit includes: the Gaussian filter, the delay calibration unit and the digital-to-analog converter are sequentially connected in series to form a high-pass branch; the gain self-calibration circuit controls the output of the high-pass branch circuit to adjust the two-point modulation phase-locked loop circuit; the Gaussian filter and the delay unit are sequentially connected in series to form a low-pass branch; the output signal of the low-pass branch adjusts the two-point modulation phase-locked loop circuit.
The invention has the beneficial effects that: the method can realize the calibration of delay matching, has the function of automatic gain calibration, and also solves the problems of large resource consumption, long calibration time and frequency offset caused by temperature great change in the traditional two-point modulation frequency offset calibration.
Further, the two-point modulation phase-locked loop circuit includes: the device comprises a phase frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, a front-end binary frequency divider, a buffer, a programmable frequency divider, a sigma-delta modulator, a digital/analog automatic frequency controller, a digital-to-analog converter and a low-pass filter; the signal input circuit includes: the device comprises a Gaussian filter, a delay calibration unit and a delay unit; the phase frequency detector, the charge pump, the loop filter, the voltage-controlled oscillator, the front-end two-frequency divider, the buffer and the programmable frequency divider in the two-point modulation phase-locked loop circuit are sequentially connected in series to form a loop; the front-end two-frequency divider is also connected with a power amplifier; the programmable frequency divider also forms a connection loop with the sigma-delta modulator; the buffer is also connected with a digital/analog automatic frequency controller, a voltage-controlled oscillator and a front-end two-frequency divider in series in sequence to form a loop.
Further, the signal input circuit further comprises: the data passes through a first-in first-out (FIFO) memory and then is transferred and buffered through the FIFO memory after passing through a Gaussian filter.
The further beneficial effects are as follows: the problem that data are lost in different clock domains is solved.
Furthermore, the signal input circuit also comprises a first-in first-out memory, and after the data is quantized, the data is transmitted to the low-pass path through the lookup table.
The further beneficial effects are as follows: after the data is quantized through the first-in first-out memory, the data is transmitted to the low-pass path through the lookup table, and the problem of data matching of the two paths is effectively solved.
Further, an Amplifier (Amp), a Comparator (Comp), and a Gain Calibration Controller (GCC) in the Gain self-Calibration circuit are connected in series in sequence;
an amplifier for amplifying the loop filter output voltage; a comparator for comparing a gain difference of a high-pass route phase-locked loop response; and the gain self-calibration controller is used for judging whether the high-low path gain is matched or not, and controlling words to change the output swing of the digital-to-analog converter by adjusting a low-pass filter arranged behind the digital-to-analog converter so as to achieve gain self-calibration.
The further beneficial effects are as follows: the gain difference of the high and low paths is calculated through a gain self-calibration circuit, the control word of the low-pass filter is adjusted in a different direction by using a special calibration time sequence, the output amplitude of the digital-to-analog converter is changed to realize the gain matching of the two paths, and the calibration process is completed by configuring a delay control word.
The invention also relates to a method for calibrating the two-point modulation transmitter, which comprises the following steps:
s1, the transmitter is electrified to enable detection, after the electrification is detected, the transmitter is in a ready-to-transmit state, and the transmitter is calibrated before signal communication;
s2, setting integer frequency dividing ratio and decimal frequency dividing ratio control word corresponding to the working frequency of the phase-locked loop through a transmitting channel, and opening a fast phase-locked loop open-loop path composed of a voltage-controlled oscillator, a front-end binary frequency divider, a buffer and a digital/analog automatic frequency controller to enable the circuit;
s3, when the frequency automatic control process is carried out, the input data passes through the buffer, the digital/analog automatic frequency controller, the voltage-controlled oscillator and the front two-frequency division to be connected in series in sequence to form a loop to roughly adjust the working frequency of the phase-locked loop, so that the phase-locked loop is locked in a certain error range of the working frequency point, and waits for the digital/analog automatic frequency controller to finish the mark; inputting a central control word by the digital-to-analog converter at the moment;
s4, after detecting that an AFC completion flag of the digital/analog automatic frequency controller is effective, enabling a phase frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, a front-end binary frequency divider, a buffer, a programmable frequency divider and a sigma-delta modulator to form a phase-locked loop, carrying out frequency phase locking under the condition, and waiting for a locking detection circuit to output a locking flag;
s5, if the locking mark is detected to be effective, the calibration circuit is started to enable, and circuit gain self-calibration is carried out;
and S6, after the gain self-calibration is completed, the SPI configuration logic respectively carries out time delay processing on a high-pass branch formed by sequentially connecting the Gaussian filter, the delay calibration unit and the digital-to-analog converter in series and a low-pass branch formed by sequentially connecting the Gaussian filter and the delay unit in series, and meanwhile, in the chip communication process, the time delay control words are configured into corresponding registers.
Further, after the end of step S5, if the temperature is changed greatly during normal communication operation, S3-S5 are repeated to complete the gain self-calibration process, and the delay calibration control word is kept unchanged.
Has the advantages that: the implementation of the gain self-calibration method can effectively calibrate the frequency offset error of the transmitted data and realize the all-pass transmission of high-quality data.
Drawings
FIG. 1 is a circuit schematic diagram of a two point modulation transmitter calibration of the present invention;
FIG. 2 is a schematic circuit diagram illustrating calibration of a two-point modulation transmitter according to the present invention;
FIG. 3 is a flow chart of a two point modulation transmitter calibration method of the present invention;
FIG. 4 is a schematic diagram of a gain self-calibration circuit according to an embodiment of the present invention;
FIG. 5 is a timing diagram of control signals of the switch timing control circuit according to the present invention;
FIG. 6 is a timing diagram illustrating a calibration sequence of the gain self-calibration circuit according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a conventional two-point modulation transmitter based on a phase-locked loop;
fig. 8 is a schematic diagram of a two-point modulation calibration transmitter in the prior art.
Detailed Description
The principles and features of this invention are described below in conjunction with the following drawings, which are set forth by way of illustration only and are not intended to limit the scope of the invention.
As shown in fig. 1, a circuit for calibration of a two point modulation transmitter, the circuit comprising: the two-point modulation phase-locked loop system comprises a two-point modulation phase-locked loop system, a signal input circuit, a power amplifier and a gain self-calibration circuit;
the Two-point modulation Phase Locked Loop (TPSDMPLL) system includes: a Phase Frequency Detector (PFD), a Charge Pump (CP), a Loop Filter (LF), a Voltage Controlled Oscillator (VCO), a Pre-Divider (Pre-Divider 2), a Buffer (Buffer), a Programmable Divider (Programmable Divider), a Sigma-Delta Modulator (SDM), a Digital/Analog Automatic Frequency controller (Digital/Analog AFC), a Digital to Analog LPF Converter (DAC), and a Low Pass Filter (Low pad Filter); the signal input circuit includes: gaussian Filter (Gauss Filter), Delay Calibration unit (DLYcal), Delay unit (Delay); the phase frequency detector, the charge pump, the loop filter, the voltage-controlled oscillator, the front-end two-frequency divider, the buffer and the programmable frequency divider in the two-point modulation phase-locked loop system are sequentially connected in series to form a loop; the front-end binary frequency division is also connected with a Power Amplifier (PA); the programmable frequency divider also forms a connection loop with the sigma-delta modulator; the buffer is also connected with a digital/analog automatic frequency controller, a voltage-controlled oscillator and a front-end two-frequency divider in series in sequence to form a loop;
the Gaussian filter, the delay calibration unit and the digital-to-analog converter in the signal input circuit are sequentially connected in series; the Gaussian filter and the delay unit are sequentially connected in series, the output of the series connection is mixed with the input of a transmitting Channel (RF Channel), and the mixed output is input into the sigma-delta modulator;
the input of the transmitting Channel (RF Channel) is also mixed with the output of the sigma-delta modulator, and the mixed input is input into the programmable frequency divider;
and the output of the loop filter is respectively connected with the gain self-calibration circuit and the voltage-controlled oscillator.
The signal input circuit further comprises: the data passes through a first-in first-out (FIFO) memory and then is transferred and buffered through the FIFO memory after passing through a Gaussian filter.
The signal input circuit further comprises: after the data is quantized through the first-in first-out memory, the data is transmitted to the low-pass path through a Look-Up Table (LUT).
An Amplifier (Amplifier, Amp), a Comparator (Comp) and a Gain Calibration Controller (GCC) in the Gain self-Calibration circuit are connected in series in sequence;
an amplifier for amplifying the loop filter output voltage; a comparator for comparing a gain difference of a high-pass route phase-locked loop response; and the gain self-calibration controller is used for judging whether the high-low path gain is matched or not, and controlling words to change the output swing of the digital-to-analog converter by adjusting a low-pass filter arranged behind the digital-to-analog converter so as to achieve gain self-calibration.
A method of calibrating a two-point modulation transmitter as shown in fig. 3, the method comprising the steps of:
s1, the transmitter is electrified to enable detection, after the electrification is detected, the transmitter is in a ready-to-transmit state, and the transmitter is calibrated before signal communication;
s2, setting integer frequency dividing ratio and decimal frequency dividing ratio control words corresponding to the working frequency of the phase-locked loop through an RF Channel, and opening a fast phase-locked loop open-loop path consisting of a voltage-controlled oscillator, a front-end binary frequency divider, a buffer fast and a digital/analog automatic frequency controller for enabling the circuit;
s3, closing S0, opening S1 and simultaneously opening S2, performing an automatic frequency control process, wherein input data are sequentially connected in series through a buffer, a digital/analog automatic frequency controller, a voltage-controlled oscillator and a front-end binary frequency to form a loop to roughly adjust the working frequency of the phase-locked loop, so that the phase-locked loop is locked in a certain error range of a working frequency point, waiting for an AFC (automatic frequency control) completion mark of the digital/analog automatic frequency controller, and inputting a central control word by a digital-to-analog converter at the moment;
s4, after detecting that an AFC completion flag of the digital/analog automatic frequency controller is valid, disconnecting S0, closing S1 and disconnecting S2 to enable the phase frequency detector, the charge pump, the loop filter, the voltage-controlled oscillator, the pre-divide-by-two frequency, the buffer, the programmable frequency divider and the sigma-delta modulator to form a phase-locked loop; performing frequency phase locking under the condition, and waiting for the locking detection circuit to output a locking mark;
s5, if the locking mark is detected to be effective, opening S0, closing S1, closing S2, starting the enabling of the calibration circuit, and carrying out circuit gain self-calibration;
and S6, after the gain self-calibration is completed, the SPI configuration logic realizes the delay processing of the high-pass branch composed of the delay calibration unit, the digital-to-analog converter and the low-pass filter and the low-pass branch formed by the Gaussian filter and the delay unit which are connected in series in sequence, and simultaneously configures the delay control word into the corresponding register in the chip communication process.
And S7, if the temperature is changed greatly in normal communication work, repeating S3-S5 to complete the gain self-calibration process, and keeping the delay calibration control word unchanged.
DETAILED DESCRIPTION OF EMBODIMENT (S) OF INVENTION
Step I: the battery is powered on to enable detection, after the battery is powered on, the transmitter is in a ready-to-transmit state, and before signal communication is carried out, the transmitter needs to be calibrated to ensure the communication quality.
Step II: as shown in fig. 1, an integer division ratio and a fractional division ratio control word corresponding to the operating frequency of the phase-locked loop are set by the RF Channel, and the module enable of the open loop path of the phase-locked loop is opened.
Step III: as shown in fig. 1, S0 is closed, S1 is opened to cut off the pll loop, S2 is also opened at the same time, and an Automatic Frequency Control (AFC) process is performed, at this time, a loop is formed by VCO, Pre-Divider 2, Buffer, and Digital/Analog AFC to realize coarse adjustment of the operating frequency of the pll, so that the pll is locked within a certain error range of the operating frequency point, and waits for an AFC completion flag, and at this time, the Digital-to-Analog converter inputs a central control word, and if 6 bits are taken as an example, the input control word is: 0 d' 32.
Step IV: and after detecting that the AFC completion flag is effective, opening S0, closing S1, and opening S2 to enable the PFD, the CP, the LF, the VCO, the Pre-Divider 2, the Buffer, the Programmable Divider and the sigma-delta Modulator to form a phase-locked loop. Under this condition, frequency phase locking is performed, and a Locked flag is output by a Locked Detector (LD) circuit.
Step V: if the lock flag is detected to be valid, the circuit is opened S0, closed S1, closed S2, the calibration circuit enable is turned on, and the gain self-calibration circuit is obtained, as shown in fig. 4, when the calibration circuit enable is valid, in combination with fig. 4, S0 is closed, S11, S4, S5, S6, S7, S8, S9, and S10, as shown in fig. 5, a clock high level indicates that the switch is turned on, a low level switch is turned off, and both the Clk1 and the Clk2 are non-overlapping control timings, are converted through the calibration timing dagainctrl Clk, and the voltage sampling at the Φ 1 stage and the voltage change direction at the Φ 2 stage are compared.
The calibration timing is detailed as in fig. 6:
DaGainCtrlClk: if the dagainctrl clk is high, no data is sent, the phase-locked loop presents a carrier frequency, at this time, the dac signal control word corresponds to 0d ' 32, if the dagainctrl clk is low, 8 consecutive "0" and 8 "1" signals are sent, the signal level "0" corresponds to the dac minimum control word 0d ' 1, the signal level "1" corresponds to the dac maximum control word 0d ' 63, and the digital signal samples the output result of the comparator at the end of the 7 th 0/1 to update the LPF control word.
GainctrlData: the signal corresponds to data sent by a phase-locked loop, amplitude is mainly concerned in the gain calibration stage, and therefore the data does not pass through a Gauss Filter and directly uses the minimum 0d '1 and the maximum 0 d' 63; during the non-gain calibration phase, the data is from the Gauss Filter output.
DaDAC _ FrqCal: this signal is the LPF resistance control word, i.e. the control word that the calibration algorithm needs to look for. During power-on detection, the calibration algorithm uses a dichotomy mode and is set as a central value 7' b100_0000 during starting; after the first round of sampling comparison, if the adgain ctrl out is high when the transmit data gain ctrl data is 1, which indicates that the LPF control word is to be increased, the control word is set to 7' b110_0000 by using a bisection method; and starting a second round of sampling comparison, in the 2 nd round of comparison, if AdGainCtrlOut is high when GainCtrlData is 1, indicating that the LPF control word needs to be increased, setting the control word to be 7' b111_0000 by utilizing a dichotomy, starting a third round of sampling comparison, and so on until the output of the AdGainCtrlOut is 0, and on the contrary, if the comparison is carried out, the AdGainCtrlOut is high when GainCtrlData is 0, indicating that the LPF control word needs to be decreased, correspondingly decreasing the LPF control word. During temperature great change, the calibration algorithm changes the LPF control word by using a successive approximation method, and the maximum calibration time is 200us and the minimum calibration time is 28 us.
GainctrlFinish: if the AdGainCtrOut is 0 at two sampling points during a certain round of comparison, the LPF control word does not need to be modified, the Finish mark is set high, and the calibration is finished.
Step VI: the two branches are respectively delayed by SPI configuration logic, and then in the chip communication process, the delay control word is configured into the corresponding register, namely the delay is set to be 0-N beat in the SDM low-pass branch, and for the digital-to-analog converter high-pass branch, the delay can be set to be 1-N beat because the register is required to output analog.
Step VII: and if the temperature is changed greatly in normal communication work, repeating the steps III to V to finish the gain self-calibration process, and keeping the delay calibration control word unchanged.
In this specification, the schematic representations of the terms used above are not necessarily intended to be the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (6)
1. A two point modulation transmitter calibration circuit, the circuit comprising:
the two-point modulation phase-locked loop circuit comprises a two-point modulation phase-locked loop circuit, a signal input circuit, a power amplifier and a gain self-calibration circuit;
the two-point modulation phase-locked loop circuit includes: the device comprises a phase frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, a front-end binary frequency divider, a buffer, a programmable frequency divider, a sigma-delta modulator, a digital/analog automatic frequency controller, a digital-to-analog converter and a low-pass filter;
the signal input circuit includes: the device comprises a Gaussian filter, a delay calibration unit and a delay unit;
the phase frequency detector, the charge pump, the loop filter, the voltage-controlled oscillator, the front-end two-frequency divider, the buffer and the programmable frequency divider in the two-point modulation phase-locked loop circuit are sequentially connected in series to form a loop;
the front-end two-frequency divider is also connected with a power amplifier; the programmable frequency divider also forms a connection loop with the sigma-delta modulator;
the buffer is also connected with a digital/analog automatic frequency controller, a voltage-controlled oscillator and a front-end two-frequency divider in series in sequence to form a loop;
the amplifier, the comparator and the gain self-calibration controller in the gain self-calibration circuit are sequentially connected in series;
the signal input circuit inputs signals to the two-point modulation phase-locked loop circuit; the gain self-calibration circuit adjusts a signal input by the signal input circuit; the two-point modulation phase-locked loop circuit outputs a signal to the power amplifier;
the signal input circuit includes: the Gaussian filter, the delay calibration unit and the digital-to-analog converter are sequentially connected in series to form a high-pass branch; the gain self-calibration circuit controls the output of the high-pass branch circuit to adjust the two-point modulation phase-locked loop circuit; the Gaussian filter and the delay unit are sequentially connected in series to form a low-pass branch, and a first-in first-out memory is arranged between the Gaussian filter and the delay unit; the output signal of the low-pass branch adjusts the two-point modulation phase-locked loop circuit.
2. The calibration circuit of claim 1, wherein the signal input circuit further comprises a first-in-first-out memory, and the input signal is buffered by the first-in-first-out memory after passing through the gaussian filter.
3. The two point modulation transmitter calibration circuit of claim 1, wherein the signal input circuit further comprises: after the data is quantized through the first-in first-out memory, the data is transmitted to the low-pass path through the lookup table.
4. The two point modulation transmitter calibration circuit of claim 1, wherein the amplifier is configured to amplify a loop filter output voltage; a comparator for comparing a gain difference of a high-pass route phase-locked loop response; and the gain self-calibration controller is used for judging whether the high-low path gain is matched or not, and controlling words to change the output swing of the digital-to-analog converter by adjusting a low-pass filter arranged behind the digital-to-analog converter so as to achieve gain self-calibration.
5. A calibration method using the calibration circuit for a two point modulation transmitter of any of claims 1 to 4, the method comprising the steps of:
s1, the transmitter is electrified to enable detection, after the electrification is detected, the transmitter is in a ready-to-transmit state, and the transmitter is calibrated before signal communication;
s2, setting integer frequency dividing ratio and decimal frequency dividing ratio control word corresponding to the working frequency of the phase-locked loop through a transmitting channel, and opening a fast phase-locked loop open-loop path composed of a voltage-controlled oscillator, a front-end binary frequency divider, a buffer and a digital/analog automatic frequency controller to enable the circuit;
s3, when the frequency automatic control process is carried out, the input data passes through the buffer, the digital/analog automatic frequency controller, the voltage-controlled oscillator and the front two-frequency division to be connected in series in sequence to form a loop to roughly adjust the working frequency of the phase-locked loop, so that the phase-locked loop is locked in a certain error range of the working frequency point, the AFC completion mark of the digital/analog automatic frequency controller is waited, and the digital-analog converter inputs the central control word;
s4, after detecting that an AFC completion flag of the digital/analog automatic frequency controller is effective, enabling a phase frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, a front-end binary frequency divider, a buffer, a programmable frequency divider and a sigma-delta modulator to form a phase-locked loop, carrying out frequency phase locking under the condition, and waiting for a locking detection circuit to output a locking flag;
s5, if the locking mark is detected to be effective, the enabling of the calibration circuit is started, when the enabling of the calibration circuit is effective, the gain self-calibration of the circuit is carried out, calibration data and a calibration clock are sent, and a mark for finishing the gain self-calibration is waited;
and S6, after the gain self-calibration is completed, the SPI configuration logic respectively carries out time delay processing on a high-pass branch formed by sequentially connecting the Gaussian filter, the delay calibration unit and the digital-to-analog converter in series and a low-pass branch formed by sequentially connecting the Gaussian filter and the delay unit in series, and meanwhile, in the chip communication process, the time delay control words are configured into corresponding registers.
6. The method of claim 5, wherein after the end of step S5, if the temperature is changed greatly during normal communication operation, the steps S3-S5 are repeated to complete the gain self-calibration process, and the delay calibration control word is kept unchanged.
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| PCT/CN2017/086850 WO2018072449A1 (en) | 2016-10-20 | 2017-06-01 | A two-point modulation transmitter calibration circuit and calibration method |
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| WO2018072449A1 (en) | 2018-04-26 |
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