WO2018072449A1

WO2018072449A1 - A two-point modulation transmitter calibration circuit and calibration method

Info

Publication number: WO2018072449A1
Application number: PCT/CN2017/086850
Authority: WO
Inventors: 赵辉; 何国军; 曾军
Original assignee: 国民技术股份有限公司
Priority date: 2016-10-20
Filing date: 2017-06-01
Publication date: 2018-04-26
Also published as: CN107968687B; CN107968687A

Abstract

The present invention relates to a two-point modulation transmitter calibration circuit and a calibration method. The circuit comprises: a two-point modulation phase locked loop system, a signal input circuit, a power amplifier and a gain automatic calibration circuit. The steps of the method comprise: after a phase locked loop is locked at an operating frequency, emitting calibration data, using a low-pass branch as a reference, calculating a gain difference of high-pass and low-pass paths by means of the gain automatic calibration circuit, and using special calibration timing to differentially adjust a control word of a low-pass filter, changing the output amplitude of a digital-to-analog converter to realize gain matching of two branches, and completing a calibration process by configuring a delay control word. In the present invention, a delay-matched calibration can be achieved, a gain automatic calibration function is included, the frequency deviation problem caused by high resource consumption of traditional two-point modulation frequency offset calibration, long calibration time, and a large temperature change is also solved.

Description

Two-point modulation transmitter calibration circuit and calibration method

Technical field

The invention relates to a transmitter suitable for low power consumption, in particular to a two-point modulation transmitter calibration circuit and a calibration method.

Background technique

There are three main types of direct transmitters based on phase-locked loops: (1) out-of-band transmitters based on phase-locked loops; (2) in-band transmitters based on phase-locked loops; and (3) two-point based on phase-locked loops. Modulate the transmitter. The two-point modulation transmitter based on phase-locked loop overcomes the anti-interference ability of the out-of-band transmitter, breaks the limitation of the bandwidth of the in-band transmitter by the phase-locked loop loop, and is more suitable for high-quality transmission and low power consumption. Wireless communication device.

The most common architecture of a two-point modulation transmitter based on a phase-locked loop, as shown in Figure 7, the two-point modulation phase-locked loop is controlled by a digital modulation (Digital Modulator) to control the sigma-delta modulator (∑-Δ Modulator). Low-pass branch (A1), and digital-to-analog converter (DAC) and low-pass filter (LPF) control the high-pass branch (A2) of the input of the voltage-controlled oscillator (VCO), two-point modulation phase-locked loop The power amplifiers (PAs) together form a two-point modulation transmitter.

The two-point modulation transmitter based on the phase-locked loop breaks the bandwidth limitation of the phase-locked loop, and enhances the anti-interference ability of the out-of-band. However, since the signal is transmitted by the high-low-pass branch, the process, voltage, and temperature (Process, Under the condition of change of Voltage, Temperature, PVT, it is bound to cause delay and gain matching of low-pass branch (A1) and high-pass branch (A2).

Delay matching problem: The signal passes through two branches and is uniformly output after the VCO. Therefore, the two signals must be synchronized at the VCO output. However, under the condition of PVT change, the phase outputs of the two branches are not synchronized.

Gain matching problem: The low-pass branch (A1) can be accurately designed by digital code (Verilog); However, the high-pass branch (A2) controls the VCO by the voltage output from the digital-to-analog converter and the low-pass filter to achieve the frequency offset. Under the PVT variation condition, the frequency offset of the high-pass branch (A2) is not controllable. As a result, the two-way frequency mismatch will seriously deteriorate the communication quality.

The calibration transmitter published in the IEEE (Institute of Electrical and Electronics Engineers) in 2009, as shown in Figure 8, is a calibration method that quantifies the loop filter voltage through a high-precision ADC and implements a calibration function through a gain and phase compensation module. This calibration scheme does not process the loop filter output voltage and directly quantizes it with the ADC. The ADC also quantizes the noise signal of the loop filter voltage to introduce a calibration error.

Summary of the invention

The technical problem to be solved by the present invention is that when the signal is transmitted in the high-low-pass branch, the delay of the low-pass branch and the high-pass branch and the gain matching are not good due to the process, voltage, and temperature changes.

To solve the above technical problem, the present invention provides a two-point modulation transmitter calibration circuit, the circuit comprising:

Two-point modulation phase-locked loop circuit, signal input circuit, power amplifier and gain self-calibration circuit;

The signal input circuit input signal to the two-point modulation phase-locked loop circuit; the gain self-calibration circuit adjusts the signal input by the signal input circuit; the two-point modulation phase-locked loop circuit outputs the signal to the power amplifier;

The signal input circuit comprises: a Gaussian filter, a delay calibration unit, and a delay unit; the two-point modulation phase-locked loop circuit comprises a digital-to-analog converter; the Gaussian filter, the delay calibration unit, and the digital-to-analog converter are sequentially connected in series to form a high-pass branch; The calibration circuit controls the output of the high-pass branch to adjust the two-point modulation phase-locked loop circuit; the Gaussian filter and the delay unit are sequentially connected in series to form a low-pass branch; and the output signal of the low-pass branch adjusts the two-point modulation phase-locked loop circuit.

The invention has the beneficial effects that the delay matching calibration and the gain automatic calibration function can be realized, and the problem that the traditional two-point modulation frequency offset calibration resource consumption is large, the calibration time is long, and the temperature change causes frequency offset is solved.

Further, the two-point modulation phase-locked loop circuit further includes: a phase frequency phase detector, a charge pump, a loop filter, a voltage controlled oscillator, a prescaler, a buffer, a programmable frequency divider, and a sigma-delta modulation. , number / Analog automatic frequency controller, low-pass filter; phase frequency phase detector, charge pump, loop filter, voltage controlled oscillator, pre-divider, buffer in the two-point modulation phase-locked loop circuit The programmable frequency divider sequentially forms a loop in series; the digital-to-analog converter, the low-pass filter and the voltage-controlled oscillator are connected in series in sequence; the pre-divider frequency is also connected to the power amplifier; the programmable frequency divider is further The connection loop is formed with the sigma-delta modulator; the buffer is also connected in series with the digital/analog automatic frequency controller, the voltage controlled oscillator, and the preamplifier to form a loop.

Further, the signal input circuit further includes: a first-in first-out memory (FIFO), and the data passes through the Gaussian filter and is buffered by the first-in first-out memory.

The above further beneficial effects: solve the problem that data is lost in different clock domains.

Further, the signal input circuit further includes a lookup table: after the data is passed through the first in first out memory and quantized, the data is transmitted to the low pass path through the lookup table.

The above further beneficial effects: after the data is passed through the first-in first-out memory and quantized, the data is transmitted to the low-pass path through the look-up table, thereby effectively solving the data matching problem of the two branches.

Further, the gain self-calibration circuit includes an amplifier (Amplifier, Amp), a comparator (Comparator, Comp), and a Gain Calibration Controller (GCC), which are sequentially connected in series;

An amplifier for amplifying the output voltage of the loop filter; a comparator for comparing the gain difference of the high-low path response by the phase-locked loop; a gain self-calibration controller for determining whether the high and low path gains match, and adjusting the digital-to-analog conversion The low-pass filter control word at the rear of the device changes the digital-to-analog converter output swing to achieve gain self-calibration.

The above further beneficial effects: the gain difference of the high and low paths is calculated by the gain self-calibration circuit, and the control word of the low-pass filter is adjusted by using the special calibration timing, and the output amplitude of the digital-to-analog converter is changed to realize the two-path gain matching. And complete the calibration process by configuring the delay control word.

The invention further relates to a method of two-point modulation transmitter calibration, the method steps comprising:

S1, the transmitter is powered on and enabled to detect. After detecting the power-on, the transmitter should be in a ready-to-transmit state, and the transmitter is calibrated before the signal communication is performed;

S2, setting an integer division ratio and a fractional ratio control word corresponding to the operating frequency of the phase locked loop through the transmission channel, and opening the voltage controlled oscillator, the preamplifier, the buffer, and the digital/analog automatic frequency controller Fast phase-locked loop open-loop path for circuit enablement;

S3, when the frequency automatic control process is performed, the input data is coarsely adjusted by the buffer, the digital/analog automatic frequency controller, the voltage controlled oscillator, and the front two-way serially connected loops to form a loop of the phase locked loop. , so that the phase-locked loop is locked within a certain error range of the working frequency point, waiting for the digital/analog automatic frequency controller to complete the flag; at this time, the digital-to-analog converter inputs the central control word;

S4, after detecting that the digital/analog automatic frequency controller AFC completion flag is valid, the phase frequency detector, the charge pump, the loop filter, the voltage controlled oscillator, the preamplifier, the buffer, and the programmable frequency division are enabled. The ∑-Δ modulator forms a phase-locked loop loop, and performs frequency phase locking under this condition, waiting for the lock detection circuit to output a lock flag;

S5, if it is detected that the lock flag is valid, the calibration circuit is enabled to perform circuit gain self-calibration;

S6, after the gain self-calibration is completed, the high-pass branch formed by the Gaussian filter, the delay calibration unit, and the digital-to-analog converter in series and the low-pass branch formed by the Gaussian filter and the delay unit in series are realized by the SPI configuration logic. The two branches of the road are respectively processed for delay, and the delay control word is configured into the corresponding register during the chip communication process.

Further, after the end of the step S5, if the temperature changes greatly during the normal communication operation, the S3-S5 is repeated to complete the gain self-calibration process, and the delay calibration control word is kept unchanged.

The beneficial effects: the implementation of the gain self-calibration method can effectively calibrate the frequency offset error of the transmitted data, and realize high-quality all-pass transmission of data.

DRAWINGS

1 is a circuit diagram of a two-point modulation transmitter calibration according to the present invention;

2 is a schematic diagram of a circuit for calibrating a two-point modulation transmitter according to the present invention;

3 is a flow chart of a method for calibrating a two-point modulation transmitter according to the present invention;

4 is a schematic diagram of a gain self-calibration circuit according to an embodiment of the present invention;

5 is a timing diagram of control signals of a switch timing control circuit of the present invention;

6 is a calibration timing of a gain self-calibration circuit according to an embodiment of the present invention;

7 is a schematic diagram of a conventional two-point modulation transmitter based on a phase locked loop;

FIG. 8 is a schematic diagram of a two-point modulation calibration transmitter in the prior art.

detailed description

The principles and features of the present invention are described in the following with reference to the accompanying drawings.

As shown in FIG. 2, a two-point modulation transmitter calibration circuit includes: a two-point modulation phase-locked loop system, a signal input circuit, a power amplifier, and a gain self-calibration circuit;

As shown in Figure 1, the two-point Sigma-Delta Modulator Phase Locked Loop (TPSDMPLL) includes: Phase Frequency Detector (PFD) and Charge Pump (CP). , Loop Filter (LF), Voltage Control Oscillator (VCO), Pre-divider 2, Buffer, Programmable Divider ), Sigma-Delta Modulator (SDM), Digital/Analog Automatic Frequency Control (Digital/Analog AFC), Digital to Analog Converter (DAC), Low pass filter (LPF); signal input circuit includes: Gauss filter, Delay Calibration (DLYcal), delay unit (Delay); the two-point modulation phase-locked loop The phase frequency detector, the charge pump, the loop filter, the voltage controlled oscillator, the preamplifier, the buffer, and the programmable frequency divider in the system are sequentially connected in series to form a loop; the digital to analog converter, low Pass filter The voltage controlled oscillators are connected in series in series; the preamplifier is also connected to a power amplifier (PA); the programmable frequency divider also forms a connection loop with the sigma-delta modulator; the buffer is also integrated with digital/analog The frequency controller, the voltage controlled oscillator, and the front two-way frequency are sequentially connected in series to form a loop;

The Gaussian filter, the delay calibration unit and the digital-to-analog converter of the two-point modulation phase-locked loop system are sequentially connected in series to form a high-pass branch; the Gaussian filter and the delay unit are sequentially connected in series to form a low-pass branch. The output of the series is mixed with the input of the RF Channel input, and then mixed and input to the sigma-delta modulator;

The transmit channel (RF Channel) input is also mixed with the output of the sigma-delta modulator, and mixed into a programmable frequency divider;

The output of the loop filter is respectively connected to a gain self-calibration circuit and a voltage controlled oscillator.

The signal input circuit also includes: a first-in first-out memory (FIFO), and the data passes through the Gaussian filter and is buffered by the first-in first-out memory.

The signal input circuit further includes: after the data passes through the first-in first-out memory and is quantized, the data is transmitted to the low-pass path through a lookup table (LUT).

The gain self-calibration circuit includes an amplifier (Amplifier, Amp), a comparator (Comparator, Comp), and a Gain Calibration Controller (GCC), which are sequentially connected in series;

A method for calibration of a two-point modulation transmitter as shown in FIG. 3, the method steps comprising:

S2, setting the integer division ratio and the fractional ratio control word corresponding to the operating frequency of the phase locked loop through the RF Channel, and turning on the voltage controlled oscillator, the front two-way, the buffer fast, the digital/analog automatic frequency controller The fast phase-locked loop open loop path is configured to enable the circuit;

S3, close S0, disconnect S1, and also disconnect S2, and perform frequency automatic control process. At this time, the input data is connected in series through buffer, digital/analog automatic frequency controller, voltage controlled oscillator, and pre-divide frequency. Forming a loop will coarsely adjust the operating frequency of the phase-locked loop, so that the phase-locked loop is locked at the working frequency Within the fixed error range, wait for the digital/analog automatic frequency controller AFC to complete the flag, and the digital-to-analog converter at this time inputs the central control word;

After S4 detects that the digital/analog automatic frequency controller AFC completion flag is valid, it disconnects S0, closes S1, and disconnects S2, so that the phase frequency detector, charge pump, loop filter, voltage controlled oscillator, front two The frequency division, the buffer, the programmable frequency divider, and the sigma-delta modulator form a phase-locked loop loop; under this condition, the frequency phase is locked, and the lock detection circuit outputs a lock flag;

S5, if it is detected that the lock flag is valid, open S0, close S1, close S2, turn on the calibration circuit to enable circuit gain self-calibration;

S6, after the gain self-calibration is completed, the high-pass branch composed of the delay calibration unit, the digital-to-analog converter and the low-pass filter, and the low-pass branch formed by the Gaussian filter and the delay unit in series are realized by the SPI configuration logic. The two branches are separately processed for delay, and the delay control word is configured into the corresponding register during the chip communication process.

S7. If the temperature changes greatly during normal communication, repeat S3-S5 to complete the gain self-calibration process and keep the delay calibration control word unchanged.

Specific embodiment

Step I: The battery is powered on and enabled. After the power is detected, the transmitter should be in the ready to transmit state. Before the signal communication, the transmitter needs to be calibrated to ensure the communication quality.

Step II: As shown in FIG. 1, the integer division ratio and the fractional ratio control word corresponding to the operating frequency of the phase locked loop are set by the RF Channel, and the module for opening the open loop path of the phase locked loop is enabled.

Step III: As shown in Figure 1, close S0, disconnect S1 to cut off the phase-locked loop, and also disconnect S2 to perform automatic frequency control (AFC) process. At this time, pass VCO, Pre-Divider 2, Buffer, Digital/Analog AFC forms a loop to realize the coarse adjustment of the operating frequency of the phase-locked loop, so that the phase-locked loop is locked within a certain error range of the working frequency, waiting for the AFC completion flag. At this time, the digital-to-analog converter inputs the central control word, if 6bit As an example, the input control word is: 0d'32.

Step IV: After detecting that the AFC completion flag is valid, disconnect S0, close S1, disconnect S2, and make PFD, CP, LF, VCO, Pre-Divider 2, Buffer, Programmable Divider, ∑-Δ The Modulator forms a phase-locked loop. Perform frequency phase lock under this condition and wait for the Locked Detector (LD) circuit to output the lock flag.

Step V: If it is detected that the lock flag is valid, open S0, close S1, close S2, turn on the calibration circuit enable, gain self-calibration circuit, as shown in Figure 4, when the calibration circuit is enabled, in combination with Figure 4, S0 is closed, and the control timings of S11, S4, S5, S6, S7, S8, S9, and S10 are as shown in FIG. 5. In FIG. 5, the clock high level indicates that the switch is turned on, and the low level switch is turned off, Clk1. The non-overlapping control timing with Clk2 is converted by the calibration timing DaGainCtrlClk, voltage sampling in the Φ1 phase, and voltage direction comparison in the Φ2 phase.

The calibration sequence is detailed in Figure 6:

DaGainCtrlClk: If DaGainCtrlClk is high and no data is sent, the phase-locked loop presents the carrier frequency. At this time, the digital-to-analog converter signal control word corresponds to 0d'32. If DaGainCtrlClk is low, then consecutive 8 "0"s and 8 are transmitted. "1" signal, signal level "0" corresponds to digital-to-analog converter minimum control word 0d'1, signal level "1" corresponds to digital-to-analog converter maximum control word 0d'63, number ends at 7th 0/1 The sample comparator output is used to update the LPF control word.

GainCtrlData: This signal corresponds to the data sent through the phase-locked loop. The gain calibration phase mainly focuses on the amplitude. Therefore, the data does not pass the Gauss Filter and directly uses the smallest 0d'1 and the largest 0d'63. In the non-gain calibration stage, The data comes from the Gauss Filter output.

DaDAC_FrqCal: This signal is the LPF resistance control word, which is the control word that the calibration algorithm needs to find. In the power-on detection, the calibration algorithm uses the dichotomy method and is set to the center value 7'b100_0000 at startup. After the first round of sampling comparison, if AdGainCtrlOut is high when the transmission data GainCtrlData=1, it means to increase the LPF control. Word, use the dichotomy to set the control word to 7'b110_0000; and start the second round of sampling comparison. In the second round comparison, if GainCtrlData=1, AdGainCtrlOut is high, indicating that the LPF control word is to be increased, then use The dichotomy sets the control word to 7'b111_0000 and starts the third round of sample comparison, and so on, until the AdGainCtrlOut output ends at 0. Conversely, if GainCtrlData=0, AdGainCtrlOut is high, indicating that the LPF control is to be reduced. Word, then reduce the LPF control word accordingly. In When the temperature changes greatly, the calibration algorithm uses the successive approximation method to change the LPF control word. The calibration time is up to 200us and the minimum is 28us.

GainCtrlFinish: If AdGainCtrlOut is 0 at both sampling points during a round of comparison, it means that the LPF control word does not need to be modified, the Finish flag is set high, and the calibration ends.

Step VI: The delay processing is performed on the two branches by the SPI configuration logic. In the process of chip communication, the delay control word is configured into the corresponding register, that is, the SDM low-pass branch delay is set to 0~N. Beat, for the digital-to-analog converter high-pass branch, the delay can be set to 1 ~ N beats because the register output is required to simulate.

Step VII: If the temperature changes greatly during normal communication, repeat steps III through V to complete the gain self-calibration process, and keep the delay calibration control word unchanged.

In the present specification, the schematic representation of the above terms is not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. In addition, various embodiments or examples described in the specification, as well as features of various embodiments or examples, may be combined and combined.

The above are only the preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalents, improvements, etc., which are within the spirit and scope of the present invention, should be included in the protection of the present invention. Within the scope.

Claims

A two-point modulation transmitter calibration circuit, characterized in that the circuit comprises:

Two-point modulation phase-locked loop circuit, signal input circuit, power amplifier and gain self-calibration circuit;

The signal input circuit inputs a signal to the two-point modulation phase-locked loop circuit; the gain self-calibration circuit adjusts a signal input by the signal input circuit; and the two-point modulation phase-locked loop circuit outputs a signal to the power amplifier ;

The signal input circuit includes: a Gaussian filter, a delay calibration unit, and a delay unit; the two-point modulation phase-locked loop circuit includes a digital-to-analog converter; the Gaussian filter, the delay calibration unit, and the digital-to-analog converter are sequentially connected in series a high-pass branch; the gain self-calibration circuit controls the output of the high-pass branch to adjust the two-point modulation phase-locked loop circuit; the Gaussian filter and the delay unit are sequentially connected in series to form a low-pass branch; the low-pass branch The output signal of the path adjusts the two-point modulation phase locked loop circuit.
The two-point modulation transmitter calibration circuit according to claim 1, wherein the two-point modulation phase-locked loop circuit further comprises: a phase frequency phase detector, a charge pump, a loop filter, a voltage controlled oscillator, Pre-divide frequency divider, buffer, programmable frequency divider, sigma-delta modulator, digital/analog automatic frequency controller, low-pass filter; phase frequency phase detector in the two-point modulation phase-locked loop circuit a charge pump, a loop filter, a voltage controlled oscillator, a prescaler, a buffer, and a programmable frequency divider are sequentially connected in series to form a loop; the digital to analog converter, the low pass filter, and the voltage controlled oscillator Connected in series; the preamplifier is also coupled to the power amplifier; the programmable frequency divider also forms a connection loop with the sigma-delta modulator; the buffer is also associated with the digital/ The analog automatic frequency controller, the voltage controlled oscillator, and the front two-way frequency are sequentially connected in series to form a loop.
The two-point modulation transmitter calibration circuit according to claim 1, wherein the signal input circuit further comprises a FIFO memory, and the input signal passes through the FIFO filter and passes through the FIFO memory. Save buffer.
The two-point modulation transmitter calibration circuit according to claim 3, wherein the signal input circuit further comprises a lookup table: the data passes through the FIFO memory and is quantized Data is transmitted to the low pass branch through the lookup table.
The two-point modulation transmitter calibration circuit according to claim 2, wherein the gain self-calibration circuit comprises an amplifier, a comparator, and a gain self-calibration controller, which are sequentially connected in series;

An amplifier for amplifying the loop filter output voltage; a comparator for comparing the gain difference of the high-low path response by the phase-locked loop; a gain self-calibration controller for determining whether the high and low path gains match, and adjusting the number The low pass filter control word after the analog converter changes the output of the digital to analog converter to achieve gain self-calibration.
A calibration method for a two-point modulation transmitter calibration circuit according to any one of claims 1 to 5, characterized in that the method comprises the following steps:

S1, the transmitter is powered on and enabled to detect. After detecting the power-on, the transmitter should be in a ready-to-transmit state, and the transmitter is calibrated before the signal communication is performed;

S2, setting an integer division ratio and a fractional ratio control word corresponding to the operating frequency of the phase locked loop through the transmission channel, and opening the voltage controlled oscillator, the preamplifier, the buffer, and the digital/analog automatic frequency controller Fast phase-locked loop open-loop path for circuit enablement;

S3, when the frequency automatic control process is performed, the input data is coarsely adjusted by the buffer, the digital/analog automatic frequency controller, the voltage controlled oscillator, and the front two-way serially connected loops to form a loop of the phase locked loop. , so that the phase-locked loop is locked within a certain error range of the working frequency point, waiting for the digital/analog automatic frequency controller AFC to complete the flag, and the digital-to-analog converter at this time inputs the central control word;

S4, after detecting that the digital/analog automatic frequency controller AFC completion flag is valid, the phase frequency detector, the charge pump, the loop filter, the voltage controlled oscillator, the preamplifier, the buffer, and the programmable frequency division are enabled. The ∑-Δ modulator forms a phase-locked loop loop, and performs frequency phase locking under this condition, waiting for the lock detection circuit to output a lock flag;

S5, if it is detected that the lock flag is valid, the calibration circuit is enabled, when the calibration circuit is enabled, the circuit gain self-calibration is performed, the calibration data and the calibration clock are sent, and the gain self-calibration completion flag is awaited;

S6, when the gain self-calibration is completed, the SPI configuration logic implements the Gaussian filter, delay The high-pass branch formed by the calibration unit and the digital-to-analog converter in series and the low-pass branch formed by the Gaussian filter and the delay unit are respectively subjected to delay processing, and the delay control is performed during the chip communication process. The word is configured into the corresponding register.
The calibration method of the two-point modulation transmitter calibration circuit according to claim 6, wherein after the end of step S5, it is determined that if the temperature changes greatly during the normal communication operation, the S3-S5 is repeated to complete the gain self-calibration process, and the process remains. The delay calibration control word does not change.