CN107968687A - A kind of two points modulation transmitter calibration circuit and calibration method - Google Patents
A kind of two points modulation transmitter calibration circuit and calibration method Download PDFInfo
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- CN107968687A CN107968687A CN201610921101.1A CN201610921101A CN107968687A CN 107968687 A CN107968687 A CN 107968687A CN 201610921101 A CN201610921101 A CN 201610921101A CN 107968687 A CN107968687 A CN 107968687A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
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- H04B17/00—Monitoring; Testing
- H04B17/10—Monitoring; Testing of transmitters
- H04B17/11—Monitoring; Testing of transmitters for calibration
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Abstract
The present invention relates to a kind of two points modulation transmitter calibration circuit and calibration method, circuit to include：Two points modulation phase-locked loop systems, signal input circuit, power amplifier and gain self-calibration circuit；The method and step includes：After phase lock loop locks after working frequency, transmitting calibration data, on the basis of low pass branch, the gain inequality of height path is calculated by gain self-calibration circuit, and utilize the incorgruous control word for adjusting low-pass filter of special calibration sequential, the output amplitude for changing digital analog converter realizes that two branch gains match, and by reconfiguration latency control word, completes calibration process.The function of calibration and the Gain Automatic calibration of delay matching can be realized by the present invention, also solves the problem of traditional two points modulation frequency offset correction resource consumption is big, and prover time is grown, and temperature great change brings frequency deviation.
Description
Technical field
The present invention relates to a kind of transmitter suitable for low-power consumption, more particularly to a kind of two points modulation transmitter calibration electricity
Road and calibration method.
Background technology
The common direct transmitter based on phaselocked loop mainly has three kinds：(1) the out-of-band emission machine based on phaselocked loop；(2)
The interior transmitter of band based on phaselocked loop；(3) the two points modulation transmitter based on phaselocked loop.And the two points modulation hair based on phaselocked loop
It is weak due to overcoming out-of-band emission machine antijamming capability to penetrate machine, has abolished and has been limited with interior transmitter by PLL loop bandwidth,
It is more suitable for the radio communication device of high quality transmitting and low-power consumption.
The most common framework of two points modulation transmitter based on phaselocked loop, as shown in fig. 7, two points modulation phaselocked loop is by launching
Signal controls the low pass of sigma-delta modulator (sigma-delta Modulator) by digital modulation (Digital Modulator) respectively
Branch (A1), and the height of the input terminal of digital analog converter (DAC) and low-pass filter (LPF) control voltage controlled oscillator (VCO)
Logical branch (A2) is formed, and two points modulation phaselocked loop together form two points modulation transmitter with power amplifier (PA).
Although two points modulation transmitter based on phaselocked loop has abolished the limitation of PLL loop bandwidth, enhance with outer anti-
Interference performance, but since signal is transmitted by high low pass branch, technique, voltage, temperature (Process, Voltage,
Temperature, PVT) change under conditions of, the delay and gain of low pass branch (A1), high pass branch (A2) certainly will be caused
With problem.
Delay matching problem：Signal is by two branches, and unified output, then necessarily require two signals defeated in VCO after VCO
Go out synchronization, but under PVT change conditions, two tributary signal phase outputs can be caused asynchronous.
Gain match problem：Low pass branch (A1) can be realized by digital code (Verilog) and accurately designed；But high pass
Branch (A2), then be to control VCO by digital analog converter and the voltage of low-pass filter output to realize frequency deviation, change in PVT
Under the conditions of, the frequency deviation of high pass branch (A2) is simultaneously uncontrollable, causes two branch frequency deviation mismatches, can severe exacerbation communication quality.
It is published within 2009 IEEE's (Institute of Electrical and Electronics Engineers)
Calibration transmitter, as shown in figure 8, this calibration method is to quantify loop filter voltage by high-precision ADC, by gain and
Phase compensation block realizes calibration function, this calibration program to loop filter output voltage handle directly using ADC
Quantify, then ADC can also quantify the noise signal of loop filter voltage in the lump, so as to introduce calibration error.
The content of the invention
The technical problems to be solved by the invention are：Signal when high low pass branch is transmitted, due to technique, voltage,
Temperature change, so as to cause low pass branch, the delay of high pass branch and gain match bad.
To solve technical problem above, the present invention provides a kind of two points modulation transmitter calibration circuit, the circuit bag
Include：
Two points modulation phase-locked loop circuit, signal input circuit, power amplifier and gain self-calibration circuit；
Signal input circuit input signal is to two points modulation phase-locked loop circuit；Gain self-calibration circuit Regulate signal input electricity
The signal of road input；Two points modulation phase-locked loop circuit outputs signal to power amplifier；
Signal input circuit includes：Gaussian filter, delay alignment unit, digital analog converter are sequentially connected in series to form high pass branch
Road；The output of gain self-calibration circuit control high pass branch adjusts two points modulation phase-locked loop circuit；Gaussian filter, delay cell
It is sequentially connected in series to form low pass branch；The output Signal Regulation two points modulation phase-locked loop circuit of low pass branch.
Beneficial effects of the present invention：It can realize the function of calibration and the Gain Automatic calibration of delay matching, also solve
The problem of traditional two points modulation frequency offset correction resource consumption of having determined is big, prover time length, temperature great change brings frequency deviation.
Further, two points modulation phase-locked loop circuit includes：Phase frequency detector, charge pump, loop filter, voltage controlled oscillation
Device, preposition two divided-frequency, buffer, programmable frequency divider, sigma-delta modulator, digital-to-analog automatic frequency controller, digital-to-analogue turn
Parallel operation, low-pass filter；Signal input circuit includes：Gaussian filter, delay alignment unit, delay cell；Described 2 points
Modulate phase-locked loop circuit in phase frequency detector, charge pump, loop filter, voltage controlled oscillator, preposition two divided-frequency, buffer,
Programmable frequency divider is sequentially connected in series to form loop；Preposition two divided-frequency is also connected with power amplifier；Programmable frequency divider also with Σ-
Delta modulator forms linkloop；Buffer also with digital-to-analog automatic frequency controller, voltage controlled oscillator, preposition two divided-frequency
It is sequentially connected in series to form loop.
Further, further included in signal input circuit：Push-up storage (FIFO), after data are by Gaussian filter
Buffered by push-up storage unloading.
Above-mentioned further beneficial effect：Solve the problems, such as that data are lost in different clock-domains.
Further, data are further included in signal input circuit after push-up storage and quantization, by searching for table
Data are transmitted to low pass path.
Above-mentioned further beneficial effect：Data are after push-up storage and quantization, by searching for table to low pass
Tunnel data, effectively solve the problems, such as the Data Matching of two branches.
Further, the amplifier (Amplifier, Amp) in the gain self-calibration circuit, comparator
(Comparator, Comp), gain self-correcting collimator controller (Gain Calibration Controller, GCC) are sequentially connected in series；
Amplifier, for amplifying loop filter output voltage；Comparator, is responded for comparing height path by phaselocked loop
Gain inequality；Gain self-correcting collimator controller, for judging whether height path gain matches, and by adjusting digital analog converter after
The low-pass filter control word put changes digital analog converter output voltage swing, reaches gain self calibration.
Above-mentioned further beneficial effect：The gain inequality of height path is calculated by gain self-calibration circuit, and is utilized
The incorgruous control word for adjusting low-pass filter of special calibration sequential, the output amplitude for changing digital analog converter realize that two branches increase
Benefit matching, and by reconfiguration latency control word, complete calibration process.
The invention further relates to a kind of method of two points modulation transmitter calibration, this method step includes：
S1, transmitter power on enabled detection, detect that after the power is turned on, then transmitter should be at launch standby, are carrying out
Before signal communication, transmitter is calibrated；
S2, the corresponding integer frequency ratio of phase-locked loop operation frequency and fractional frequency division ratio control word are set by launch channel,
And open the fast lock phase being made of voltage controlled oscillator, preposition two divided-frequency, buffer, digital-to-analog automatic frequency controller
Ring open loop path carries out circuit and enables；
S3, when carrying out Automatic Frequency Control process, the data inputted at this time pass through buffer, the automatic frequency of digital-to-analog
Rate controller, voltage controlled oscillator, preposition two divided-frequency are followed in series to form loop by phase-locked loop operation frequency coarse adjustment so that phaselocked loop
Working frequency points within a certain error range is locked in, waits digital-to-analog automatic frequency controller complement mark；Digital-to-analogue at this time turns
Parallel operation input center control word；
S4, after detecting that digital-to-analog automatic frequency controller AFC complement marks are effective, makes phase frequency detector, electric charge
Pump, loop filter, voltage controlled oscillator, preposition two divided-frequency, buffer, programmable frequency divider, sigma-delta modulator form phaselocked loop
Loop, carries out Frequency Phase Lock on this condition, waits lock detecting circuit output lock flag；
S5, if after detecting that lock flag is effective, opening calibration circuit and enabling, carry out circuit gain self calibration；
S6, after the completion of gain self calibration, logic realization is configured to by Gaussian filter, delay alignment unit, number by SPI
Mode converter is sequentially connected in series the high pass branch to be formed and the low pass branch two formed is sequentially connected in series by Gaussian filter, delay cell
Branch does delay process respectively, while during chip communication, delays time to control word is configured in corresponding registers.
Further, after in step s 5, if temperature great change in normal communication operation, repeatedly S3-S5 completes gain
Self-calibration process, keeps delay calibration control word constant.
Beneficial effect：The implementation of gain method for self-calibrating, can realize data effectively to transmitting data frequency offset error calibration
The all-pass transmission of high quality.
Brief description of the drawings
Fig. 1 is a kind of circuit diagram of two points modulation transmitter calibration of the present invention；
Fig. 2 is a kind of circuit schematic diagram of two points modulation transmitter calibration of the present invention；
Fig. 3 is a kind of flow chart of two points modulation transmitter calibration method of the present invention；
Fig. 4 is gain self-calibration circuit schematic diagram in the embodiment of the present invention；
Fig. 5 is the control signal time diagram of switching sequence control circuit of the present invention；
Fig. 6 calibrates sequential for gain of embodiment of the present invention self-calibration circuit；
Fig. 7 is the existing two points modulation transmitter schematic diagram based on phaselocked loop；
Fig. 8 is two points modulation calibration transmitter schematic diagram of the prior art.
Embodiment
The principle and features of the present invention will be described below with reference to the accompanying drawings, and the given examples are served only to explain the present invention, and
It is non-to be used to limit the scope of the present invention.
As shown in Figure 1, a kind of circuit of two points modulation transmitter calibration, the circuit include：Two points modulation phaselocked loop
System, signal input circuit, power amplifier and gain self-calibration circuit；
Two points modulation phase-locked loop systems (Two-point Sigma-Delta Modulator Phase Locked Loop,
TPSDMPLL) include：Phase frequency detector (Phase Frequency Detector, PFD), charge pump (Charge Pump,
CP), loop filter (Loop Filter, LF), voltage controlled oscillator (Voltage Control Oscillator, VCO), preceding
Put two divided-frequency (Pre-divider 2), buffer (Buffer), programmable frequency divider (Programmable Divider), Σ-
Delta modulator (Sigma-Delta Modulator, SDM), digital-to-analog automatic frequency controller (Digital/Analog
Automatic Frequency Control, Digital/Analog AFC), digital analog converter (Digital to Analog
Converter, DAC), low-pass filter (Low Pass Filter, LPF)；Signal input circuit includes：Gaussian filter
(Gauss Filter), delay alignment unit (Delay Calibration, DLYcal), delay cell (Delay)；Described
Phase frequency detector, charge pump, loop filter in two points modulation phase-locked loop systems, voltage controlled oscillator, preposition two divided-frequency, buffering
Device, programmable frequency divider are sequentially connected in series to form loop；Preposition two divided-frequency also with power amplifier (Power Amplifier, PA)
Connection；Programmable frequency divider also forms linkloop with sigma-delta modulator；Buffer is also controlled with digital-to-analog automatic frequency
Device, voltage controlled oscillator, preposition two divided-frequency are sequentially connected in series to form loop；
Gaussian filter, delay alignment unit and digital analog converter in the signal input circuit are sequentially connected in series；Institute
The Gaussian filter stated, delay cell are sequentially connected in series, and the output after series connection mix with launch channel (RF Channel) input, mixed
Sigma-delta modulator is inputted after conjunction；
Launch channel (RF Channel) input is also mixed with the output of sigma-delta modulator, and input can after mixing
Programming frequency division device；
The output of the loop filter is connected with gain self-calibration circuit, voltage controlled oscillator respectively.
Further included in signal input circuit：Push-up storage (FIFO), data by after Gaussian filter by elder generation
Buffered into memory unloading is first gone out.
Further included in signal input circuit：Data are after push-up storage and quantization, by searching for table (Look
Up Table, LUT) to low pass path transmit data.
In the gain self-calibration circuit amplifier (Amplifier, Amp), comparator (Comparator,
Comp), gain self-correcting collimator controller (Gain Calibration Controller, GCC) is sequentially connected in series；
Amplifier, for amplifying loop filter output voltage；Comparator, is responded for comparing height path by phaselocked loop
Gain inequality；Gain self-correcting collimator controller, for judging whether height path gain matches, and by adjusting digital analog converter after
The low-pass filter control word put changes digital analog converter output voltage swing, reaches gain self calibration.
A kind of method of two points modulation transmitter calibration as shown in Figure 3, this method step include：
S1, transmitter power on enabled detection, detect that after the power is turned on, then transmitter should be at launch standby, are carrying out
Before signal communication, transmitter is calibrated；
S2, sets the corresponding integer frequency ratio of phase-locked loop operation frequency and fractional frequency division ratio to control by RF Channel
Word, and open by voltage controlled oscillator, preposition two divided-frequency, buffer are quick, digital-to-analog automatic frequency controller form it is fast
Fast phaselocked loop open loop path carries out circuit and enables；
S3, closes S0, disconnects S1, while also disconnects S2, carries out Automatic Frequency Control process, and the data inputted at this time pass through
Buffer, digital-to-analog automatic frequency controller, voltage controlled oscillator, preposition two divided-frequency are followed in series to form loop by phaselocked loop
Working frequency coarse adjustment so that phase lock loop locks are in working frequency points within a certain error range, the automatic frequency control of wait digital-to-analog
Device AFC complement marks, digital analog converter input center control word at this time；
S4, after detecting that digital-to-analog automatic frequency controller AFC complement marks are effective, disconnects S0, closes S1, disconnect
S2, make phase frequency detector, charge pump, loop filter, voltage controlled oscillator, preposition two divided-frequency, buffer, programmable frequency divider,
Sigma-delta modulator forms cycle of phase-locked loop；Frequency Phase Lock is carried out on this condition, waits lock detecting circuit output locking
Mark；
S5, if after detecting that lock flag is effective, disconnecting S0, closes S1, closes S2, opens calibration circuit and enables, carries out
Circuit gain self calibration；
S6, after the completion of gain self calibration, by SPI configure logic realization to by delay alignment unit, digital analog converter with
The high pass branch and low pass branch two branch point formed is sequentially connected in series by Gaussian filter, delay cell that low-pass filter forms
Delay process is not done, while during chip communication, delays time to control word is configured in corresponding registers.
S7, if temperature great change in normal communication operation, repeatedly S3-S5 completes gain self-calibration process, keeps delay school
Quasi- control word is constant.
Specific embodiment
Step I：Battery powers on enabled detection, detects that after the power is turned on, then transmitter should be at launch standby, is carrying out
, it is necessary to be calibrated to transmitter before signal communication, to ensure communication quality.
Step II：As shown in Figure 1, the corresponding integer frequency ratio of phase-locked loop operation frequency and small is set by RF Channel
Number frequency dividing ratio control word, and the module for opening phaselocked loop open loop path enables.
Step III：As shown in Figure 1, closure S0, disconnects S1 and cut off cycle of phase-locked loop, while S2 is also disconnected, into line frequency
(AFC) process is automatically controlled, loop is formed by VCO, Pre-Divider 2, Buffer, Digital/Analog AFC at this time
Realize phase-locked loop operation frequency coarse adjustment so that phase lock loop locks complete mark in working frequency points within a certain error range, wait AFC
Will, digital analog converter input center control word at this time, if by taking 6bit as an example, Input Control Word is：0d’32.
Step IV：After detecting that AFC complement marks are effective, disconnect S0, close S1, disconnect S2, make PFD, CP, LF, VCO,
Pre-Divider 2, Buffer, Programmable Divider, sigma-delta Modulator form cycle of phase-locked loop.At this
Frequency Phase Lock is carried out under part, waits lock-in detection (Locked Detector, LD) circuit output lock flag.
Step V：If after detecting that lock flag is effective, disconnecting S0, S1 is closed, closes S2, calibration circuit is opened and enables,
Gain self-calibration circuit, as shown in figure 4, when calibrate circuit enable effective when, with reference to Fig. 4, S0 close, S11, S4, S5, S6, S7,
The control sequential of S8, S9, S10, as shown in figure 5, in Figure 5, clock high level represents switch conduction, low level switches off,
Clk1 and Clk2 is non-overlapping control sequential, is converted by calibrating sequential DaGainCtrlClk, in 1 stages of Φ electricity
Pressure sampling, 2 stage voltage change directions of Φ compare.
As calibration sequential is described in detail in Fig. 6：
DaGainCtrlClk：If DaGainCtrlClk is height, data are not sent, carrier frequency is presented in phaselocked loop, at this time
Digital analog converter signal control word corresponds to 0d ' 32, if DaGainCtrlClk is low, sends continuous 8 " 0 " and 8
" 1 " signal, the corresponding digital analog converter minimum control word 0d ' 1 of signal level " 0 ", the corresponding digital analog converter of signal level " 1 " are maximum
Control word 0d ' 63, numeral sample comparator output as a result, for updating LPF control words at the end of the 7th 0/1.
GainCtrlData：The signal corresponds to the pass the data of phaselocked loop transmission, and the gain calibration stage is primarily upon width
Value, therefore data directly use minimum 0d ' 1 and maximum 0d ' 63 without Gauss Filter；In non-gain calibration rank
Section, the data are exported from Gauss Filter.
DaDAC_FrqCal：The signal is LPF resistance control words, i.e., the control word that calibration algorithm requires to look up.Powering on
During detection, calibration algorithm uses the mode of dichotomy, 7 ' b100_0000 centered on setting on startup；The first round samples ratio
It is if AdGainCtrlOut will increase LPF control words when sending data GainCtrlData=1 for height, expression, then sharp after relatively
Control word is arranged to 7 ' b110_0000 with dichotomy；And start the second wheel sampling and compare, when the 2nd wheel compares, if
AdGainCtrlOut is height during GainCtrlData=1, and expression will increase LPF control words, then be set control word using dichotomy
7 ' b111_0000 are set to, and starts third round sampling and compares, and so on, until AdGainCtrlOut outputs terminate for 0, instead
It, if compare, AdGainCtrlOut is height during GainCtrlData=0, and expression will reduce LPF control words, then corresponding to reduce
LPF control words.In temperature great change, calibration algorithm changes LPF control words using successive approximation method, and prover time is up to
200us, minimum 28us.
GainCtrlFinish：If when a certain wheel compares, AdGainCtrlOut is 0 in two sample points, then table
LPF control words need not be changed by showing, Finish marks put height, and calibration terminates.
Step VI：Delay process is done respectively to two branches by SPI configurations logic realization, then, will during chip communication
Delays time to control word is configured in corresponding registers, i.e., being arranged to 0~N in the delay of SDM low passes branch claps, for digital analog converter height
Logical branch, due to needing register to be output to simulation, then delay may be configured as 1~N bats.
Step VII：If temperature great change in normal communication operation, repeat step III to step V completes gain self calibration mistake
Journey, keeps delay calibration control word constant.
In the present specification, nonessential be directed to of schematic expression of the above terms is identical embodiment or example.And
And particular features, structures, materials, or characteristics described can be in any one or more of the embodiments or examples with suitable side
Formula combines.In addition, without conflicting with each other, those skilled in the art can be real by the difference described in this specification
Apply example or example and different embodiments or exemplary feature is combined and combines.
The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the invention, it is all the present invention spirit and
Within principle, any modification, equivalent replacement, improvement and so on, should all be included in the protection scope of the present invention.
Claims (7)
1. a kind of two points modulation transmitter calibration circuit, it is characterised in that the circuit includes：
Two points modulation phase-locked loop circuit, signal input circuit, power amplifier and gain self-calibration circuit；
Signal input circuit input signal is to two points modulation phase-locked loop circuit；Gain self-calibration circuit Regulate signal input circuit is defeated
The signal entered；Two points modulation phase-locked loop circuit outputs signal to power amplifier；
Signal input circuit includes：Gaussian filter, delay alignment unit, digital analog converter are sequentially connected in series to form high pass branch；
The output of gain self-calibration circuit control high pass branch adjusts two points modulation phase-locked loop circuit；Gaussian filter, delay cell according to
Secondary series connection forms low pass branch；The output Signal Regulation two points modulation phase-locked loop circuit of low pass branch.
2. the circuit of a kind of two points modulation transmitter calibration according to claim 1, it is characterised in that two points modulation locks phase
Loop circuit includes：Phase frequency detector, charge pump, loop filter, voltage controlled oscillator, preposition two divided-frequency, buffer, programmable point
Frequency device, sigma-delta modulator, digital-to-analog automatic frequency controller, digital analog converter, low-pass filter；Signal input circuit bag
Include：Gaussian filter, delay alignment unit, delay cell；Phase frequency detector, electricity in the two points modulation phase-locked loop circuit
Lotus pump, loop filter, voltage controlled oscillator, preposition two divided-frequency, buffer, programmable frequency divider are sequentially connected in series to form loop；Before
Two divided-frequency is put also to be connected with power amplifier；Programmable frequency divider also forms linkloop with sigma-delta modulator；Buffer also with
Digital-to-analog automatic frequency controller, voltage controlled oscillator, preposition two divided-frequency are sequentially connected in series to form loop.
3. a kind of two points modulation transmitter calibration circuit according to claim 1, it is characterised in that in signal input circuit
Push-up storage is further included, the signal of input after Gaussian filter by push-up storage unloading by buffering.
4. a kind of two points modulation transmitter calibration circuit according to claim 1, it is characterised in that in signal input circuit
Further include：Data transmit data after push-up storage and quantization, by searching for table to low pass path.
5. the circuit of a kind of two points modulation transmitter calibration according to claim 1, it is characterised in that the gain is certainly
Amplifier, comparator, gain self-correcting collimator controller in calibration circuit are sequentially connected in series；
Amplifier, for amplifying loop filter output voltage；Comparator, the increasing responded for comparing height path by phaselocked loop
Benefit is poor；Gain self-correcting collimator controller, for judging whether height path gain matches, and by adjusting digital analog converter postposition
Low-pass filter control word changes digital analog converter output voltage swing, reaches gain self calibration.
A kind of 6. calibration side of two points modulation transmitter calibration circuit using described in any claim in claim 1 to 5
Method, it is characterised in that this method comprises the following steps：
S1, transmitter power on enabled detection, detect that after the power is turned on, then transmitter should be at launch standby, are carrying out signal
Before communication, transmitter is calibrated；
S2, the corresponding integer frequency ratio of phase-locked loop operation frequency and fractional frequency division ratio control word are set by launch channel, and
The quick phaselocked loop being made of voltage controlled oscillator, preposition two divided-frequency, buffer, digital-to-analog automatic frequency controller is opened to open
Endless path carries out circuit and enables；
S3, when carrying out Automatic Frequency Control process, the data inputted at this time pass through buffer, digital-to-analog automatic frequency control
Device processed, voltage controlled oscillator, preposition two divided-frequency are followed in series to form loop by phase-locked loop operation frequency coarse adjustment so that phase lock loop locks
In working frequency points within a certain error range, digital-to-analog automatic frequency controller AFC complement marks are waited, digital-to-analogue at this time turns
Parallel operation input center control word；
S4, after detecting that digital-to-analog automatic frequency controller AFC complement marks are effective, makes phase frequency detector, charge pump, ring
Path filter, voltage controlled oscillator, preposition two divided-frequency, buffer, programmable frequency divider, sigma-delta modulator form cycle of phase-locked loop,
Frequency Phase Lock is carried out on this condition, waits lock detecting circuit output lock flag；
S5, if after detecting that lock flag is effective, opens calibration circuit and enables, and when calibration circuit enables effective, carries out circuit
Gain self calibration, sends calibration data and calibration clock, waits gain self calibration complement mark；
S6, after the completion of gain self calibration, logic realization is configured to being turned by Gaussian filter, delay alignment unit, digital-to-analogue by SPI
Parallel operation is sequentially connected in series the high pass branch to be formed and two branch of low pass branch formed is sequentially connected in series by Gaussian filter, delay cell
Delay process is done respectively, while during chip communication, delays time to control word is configured in corresponding registers.
7. the calibration method of a kind of two points modulation transmitter calibration circuit according to claim 6, it is characterised in that in step
After in rapid S5, if judging temperature great change in normal communication operation, repeatedly S3-S5 completes gain self-calibration process, keeps
Delay calibration control word is constant.
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| CN201610921101.1A CN107968687B (en) | 2016-10-20 | 2016-10-20 | Calibration circuit and calibration method for two-point modulation transmitter |
| PCT/CN2017/086850 WO2018072449A1 (en) | 2016-10-20 | 2017-06-01 | A two-point modulation transmitter calibration circuit and calibration method |
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| CN201610921101.1A CN107968687B (en) | 2016-10-20 | 2016-10-20 | Calibration circuit and calibration method for two-point modulation transmitter |
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| CN111049599A (en) * | 2019-12-09 | 2020-04-21 | 物格微电子(珠海)有限公司 | Calibration method of two-point modulation wireless communication transmitter |
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| CN113556187B (en) * | 2021-06-11 | 2023-02-17 | 苏州磐启微电子有限公司 | Frequency deviation calibration system of two-point modulation transmitter |
| CN113810048A (en) * | 2021-11-18 | 2021-12-17 | 深圳百瑞互联技术有限公司 | Phase-locked loop two-point modulation circuit with gain correction, transmitter and correction method |
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| CN107968687B (en) | 2021-08-24 |
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