CN110690899A - Gain calibration method and module of high-pass path in two-point modulation phase-locked loop - Google Patents
Gain calibration method and module of high-pass path in two-point modulation phase-locked loop Download PDFInfo
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Abstract
The invention provides a gain calibration method and a module of a high-pass path in a two-point modulation phase-locked loop, wherein the minimum high-pass path gain control word Gh1 is selected, and under the gain control word, the frequency variation on a VCO is converted into a counting difference delta K1 by a counting method; selecting a maximum high-pass path gain control word Gh2, and converting the frequency variation on the VCO into a counting difference delta K2 by using a counting method under the gain control word; based on the two sets of values (Gh1, Δ K1) and (Gh2, Δ K2), a binary linear equation between the gain and the count difference on the high-pass path is constructed, and the gain calibration value of the high-pass path can be directly calculated by combining the expected value of the count difference calculated in advance based on the low-pass path. The invention does not need extra analog circuit and lookup table occupying memory capacity, and because the invention adopts direct calculation method, the calibration time is greatly reduced compared with the traditional traversal method and dichotomy.
Description
Technical Field
The invention relates to the field of radio frequency integrated circuits, in particular to a gain calibration method and a gain calibration module of a high-pass path applied to a two-point modulation phase-locked loop.
Background
Compared with the transmitter with a direct frequency conversion structure, the transmitter with a polar coordinate structure can adopt a high-efficiency switch power amplifier, so that the efficiency of the whole transmitting system can be effectively improved. The phase-locked loop is a preferred structure for realizing the phase data part of the polar coordinate transmitter due to the excellent phase tracking characteristic and the low phase noise. Considering the requirements of quantization noise filtering and locking time, the loop bandwidth of the phase-locked loop is designed to be narrow, but the signal bandwidth of transmitter phase data is often greater than the loop bandwidth of the phase-locked loop, and if nothing is done, after the transmitter phase data is modulated by the phase-locked loop, signals of the transmitter phase data falling outside the loop bandwidth of the phase-locked loop are filtered out, resulting in intolerable errors. The two-point modulation phase-locked loop structure is proposed to solve the contradiction between the signal bandwidth of phase data of a transmitter and the loop bandwidth of a phase-locked loop.
A typical two-point modulation phase-locked loop structure in the prior art, as shown in fig. 1, refers to a manner of modulating transmission data by using two different modulation paths, respectively. In a first path, transmit data is injected into a phase locked loop through a Delta-Sigma modulator (DSM) and a multi-modulus divider by varying a division ratio in a feedback loop of the phase locked loop and varying a voltage (V) at a first input of a Voltage Controlled Oscillator (VCO) through a phase detector, a charge pump, and a loop filterTUNE) Thereby modulating the output frequency (F) of the phase locked loopVCO) At this time FVCOThe transmission function between the data and the transmitting data has a low-pass characteristic, and is also called a low-pass path; a second path for transmitting data, converting the digital signal into an analog signal by a digital-to-analog converter (DAC), and injecting the analog signal into a phase-locked loop, which changes the voltage (V) on the second input terminal of the VCO by the DACDAC) Thereby modulating the output frequency of the phase locked loop, at which time FVCOAnd the transmission function between the transmitted data exhibits a high-pass characteristic, and is therefore also referred to as a high-pass path;
ideally, the gain of the low-pass path and the gain of the high-pass path should be equal, so that the transfer function of the phase-locked loop in the whole frequency domain is equal to a constant, that is, the transfer function between the transmission data and the output frequency is in an all-pass characteristic, and thus the transmission data is not limited by the loop bandwidth of the phase-locked loop after being modulated by the phase-locked loop. Wherein, the gain of the low-pass path is determined by the gain of DSM and multi-modulus frequency divider, and the gain of the high-pass path is determined by the gain of DAC and VCO. In practical situations, because both the DSM and the multi-modulus divider adopt digital logic design, and according to the characteristics of the phase-locked loop, the gain of the low-pass path is only related to the reference frequency (Fref) and the quantization base number, and is a known quantity which can be obtained in advance, and is not affected by factors such as production process, voltage and temperature; the gains of the DAC and VCO are affected by semiconductor process, voltage, and temperature, and cannot be predicted in advance, and the gain of the high pass path must be calibrated in order to match the gains on the two paths. In the prior art, the gain of the high-pass path is mostly realized on the DAC, and the gain control word (Gh) of the DAC is changed through the gain calibration module, so that the gain of the high-pass path is equal to the gain of the low-pass path.
Chinese patent application publication No. CN103427839A entitled "calibration method for digital-to-analog converter for two-point modulation and two-point modulation circuit" adopts a dichotomy method to obtain the calibration value of DAC gain control word, however, dichotomy approaches the calibration value of the gain control word bit by bit according to the comparison result, and as the gain control precision increases, that is, as the bit number of the gain control word increases, the calibration time also increases proportionally.
The chinese patent application with publication No. CN107005244A and entitled "gain calibration of direct modulation synthesizer using lookup table search by counting down of overflow counter" obtains the final calibration value of DAC gain control word by means of lookup table, and then as the gain control precision increases, that is, as the bit number of the gain control word increases, the capacity of the lookup table also increases, and it needs to add extra memory space and implementation area on the chip.
The chinese patent application, publication No. CN104767575A, entitled "gain calibration method for high-pass channel digital-to-analog converter in two-point modulation transmitter", needs to perform frequency measurement by down-mixing a high-frequency signal to be measured to a low-frequency signal with the aid of an additional receiver channel and a local oscillator signal, and is only applicable to an integrated circuit system in which a transmitter and a receiver coexist and a plurality of local oscillator signals exist. In addition, due to the self frequency jitter and error of the local oscillation signal, extra frequency measurement error is introduced, so that the accuracy of the calibration result is influenced.
As described above, in most of the prior art, the minimum and maximum digital signals are loaded on the input terminal of the DAC of the high-pass path, and the variation range of the output frequency of the VCO is measured, so as to determine the relationship between the gain and the variation range of the frequency of the current high-pass path, and obtain the final gain calibration value by using a method of traversal, bisection or table lookup. However, the gain control word is a digital quantity, the bit number of the gain control word corresponds to the accuracy of gain control, the smaller the bit number, the lower the gain control accuracy, the larger the bit number, the higher the gain control accuracy, so that the bit number of the gain control word must be correspondingly increased in order to obtain higher transmission quality, i.e., higher gain control accuracy, but as the bit number of the gain control word increases, the calibration time of the traversal method and the bisection method and the lookup table capacity of the lookup table method need to be increased in equal proportion, which will undoubtedly increase the application cost and area cost of the chip.
Disclosure of Invention
In view of the above, in order to solve the above technical problems, an object of the present invention is to provide a method and a module for calibrating a gain of a high-pass path in a two-point modulation phase-locked loop.
The invention is realized by the following technical scheme:
a gain calibration method of a high-pass path in a two-point modulation phase-locked loop comprises the following steps:
step 1, constructing a counting period with fixed duration;
step 2, obtaining a first counting value, a second counting value, a third counting value and a fourth counting value by using a fixed duration counter;
step 3, a first subtracter is used for carrying out subtraction operation on the first counting value and the second counting value to obtain a first counting difference (delta K1);
step 4, a second subtracter is used for carrying out subtraction operation on the third counting value and the fourth counting value to obtain a second counting difference (delta K2);
and 5, inputting the first counting difference, the second counting difference, the minimum gain control word Gh1 of the high-pass path, the maximum gain control word Gh2 of the high-pass path and the expected value delta Kexp of the counting difference into a linear calculation module, and directly calculating to obtain the gain calibration value of the high-pass path according to a binary linear equation in the linear calculation module.
Preferably, step 3 and step 4 are two parallel steps, and the sequence is not limited.
Preferably, the method for acquiring the first count value and the second count value is as follows:
when the gain control word of the high-pass path is minimum, firstly inputting a minimum value at the data input end of the digital-to-analog converter, and counting the frequency division signal of the high-frequency signal output by the voltage-controlled oscillator by using a fixed time length counter in the counting period of the fixed time length to obtain a first counting value; and then inputting a maximum value at the data input end of the digital-to-analog converter, and counting the frequency division signal of the high-frequency signal output by the voltage-controlled oscillator by using a fixed time length counter in the counting period of the fixed time length to obtain a second counting value.
Preferably, the third count value and the fourth count value are obtained by the following method: when the gain control word of the high-pass path is maximum, firstly, inputting a minimum value at the data input end of the digital-to-analog converter, and counting the frequency division signal of the high-frequency signal output by the voltage-controlled oscillator by using a fixed time length counter in the counting period of the fixed time length to obtain a third counting value; and then inputting a maximum value at the data input end of the digital-to-analog converter, and counting the frequency division signal of the high-frequency signal output by the voltage-controlled oscillator by using a fixed time length counter in the counting period of the fixed time length to obtain a fourth counting value.
Preferably, the counting period of the fixed duration is obtained by multiplying the period of the reference frequency of the two-point modulation phase-locked loop by an integer greater than or equal to 1.
Preferably, the binary linear equation is Ghexp ═ [ (Gh2-Gh1) × Δ Kexp- Δ K1]/(Δ K2- Δ K1) + Gh 1.
Preferably, the expected count difference value Δ Kexp is a count difference that is introduced into a voltage-controlled oscillator of the two-point modulation phase-locked loop when the transmission data changes from a minimum value to a maximum value through a low-pass path, and the count difference corresponding to the predictable frequency change is recorded as an expected count difference.
Preferably, the transmission data is simultaneously input to a low pass path and a high pass path to the two-point modulation phase-locked loop, and when the gains of the high pass path and the low pass path are equal, the transmission data changes from a minimum value to a maximum value, and the frequency change amounts on the voltage-controlled oscillators introduced through the low pass path and the high pass path are equal.
Preferably, the frequency-divided signal is obtained by dividing the high-frequency signal by an integer greater than or equal to 1.
A gain calibration module of a high-pass path in a two-point modulation phase-locked loop comprises a fixed duration counter, a first subtracter, a second subtracter and a linear calculation module; the frequency division signal of the high-frequency signal output by the voltage-controlled oscillator is sent to the input end of the fixed duration counter; the fixed duration counter outputs a first count value, a second count value, a third count value and a fourth count value, wherein the first count value and the second count value are input to the first subtracter, and the third count value and the fourth count value are input to the second subtracter; the first subtracter performs subtraction operation on the first counting value and the second counting value to obtain a first counting difference, the second subtracter performs subtraction operation on the third counting value and the fourth counting value to obtain a second counting difference, the first counting difference, the second counting difference, the minimum gain control word Gh1 of the high-pass path, the maximum gain control word Gh2 of the high-pass path and the expected value delta Kexp of the counting difference are input into the linear calculation module, the gain calibration value of the high-pass path is calculated according to a calculation formula set in the linear calculation module, and the gain calibration value is input into the digital-to-analog converter of the high-pass path, so that the gain of the high-pass path is equal to the gain of the low-pass path.
Preferably, the frequency-divided signal is obtained by dividing the high-frequency signal by an integer greater than or equal to 1.
The invention has the beneficial effects that: a high-pass path gain calibration module is directly integrated in the two-point modulation phase-locked loop without participation of an additional analog circuit; a two-point measurement method is adopted to construct a binary linear equation between a gain control word and a counting difference reflecting VCO frequency variation, the required gain control word can be directly calculated without approaching bit by bit and occupying a lookup table of memory capacity, the calibration time length is not only greatly shortened, but also is relatively fixed and is not increased along with the increase of gain control precision.
Drawings
FIG. 1 is a block diagram of a typical two-point modulation phase-locked loop of the prior art;
FIG. 2 is a block diagram of a gain calibration method for a high pass path in a two-point modulation phase-locked loop according to the present invention;
FIG. 3 is a schematic block diagram of a gain calibration module of a high pass path in a two-point modulation phase-locked loop according to the present invention;
FIG. 4 is a graph illustrating the relationship between the high pass path gain control word and the VCO output frequency in accordance with the present invention;
FIG. 5 is a diagram illustrating the relationship between a high pass path gain control word and a count value according to the present invention;
FIG. 6 is a diagram illustrating a linear relationship between a high pass path gain control word and a count difference according to the present invention.
Detailed Description
The present invention will be further explained with reference to the drawings and the embodiments, it should be understood that the embodiments described herein are only for explaining and explaining the present invention and are not to be construed as limiting the present invention.
As can be seen from fig. 1, the transmit DATA TX _ DATA is simultaneously loaded to the low pass path and the high pass path, the low pass path adjusting the division ratio of the multi-modulus divider through the DSM, thereby modulating the output frequency of the VCO when the phase locked loop PLL is closed. The TX _ DATA passes through a low-pass path, and the frequency variation introduced on the VCO is counted as delta fL; while the high pass path starts from TX _ DATA and is converted to a voltage by the DAC to directly modulate the output frequency of the VCO. The TX _ DATA passes through a high-pass path, and the frequency variation introduced on the VCO is counted as delta fH; obviously, when the gains of the high-pass path and the low-pass path are equal, the frequency variation introduced by the TX _ DATA modulating VCO through the two paths should be equal, that is, Δ fH ═ Δ fL; but in practice Δ fH is an unknown quantity whose magnitude is directly related to the gain of the high-pass path.
The gain of the high-pass path is realized on the DAC, so that the gain control word Gh of the high-pass path actually determines the output voltage swing of the DAC, and the output voltage swing of the DAC is gradually increased along with the change of the Gh from small to large, and the output voltage swing actually corresponds to the difference between the output voltages of the DAC when the input of the DAC is the minimum value (DAC _ IN is MAX) and the maximum value (DAC _ IN is MAX); the output voltage of the DAC is directly applied to the VCO (assuming that the output voltage of the DAC is in a proportional relationship with the output frequency of the VCO, i.e. the higher the output voltage of the DAC, the higher the output frequency of the VCO, and vice versa; depending on different designs, it may be in an inverse proportional relationship), so as Gh changes from small to large, the frequency variation Δ fH introduced to the VCO gradually increases due to the gradually larger output voltage swing of the DAC, as shown in fig. 4. It is clear that the aim of the calibration is to obtain a suitable high pass path gain control word Gh such that the TX _ DATA goes from a minimum value (MIN) to a maximum value (MAX), i.e. the input to the DAC goes from a minimum value to a maximum value as well, the amount of frequency variation it introduces by the two path modulation VCO is equal.
Based on the above thought, the present invention provides a gain calibration method for a high-pass path in a two-point modulation phase-locked loop, as shown in fig. 2, including the following steps:
step 1, constructing a counting period with fixed duration;
step 2, obtaining a first counting value, a second counting value, a third counting value and a fourth counting value by using a fixed duration counter;
step 3, a first subtracter is used for carrying out subtraction operation on the first counting value and the second counting value to obtain a first counting difference (delta K)1)；
Step 4, a second subtracter is used for carrying out subtraction operation on the third counting value and the fourth counting value to obtain a second counting difference (delta K)2)；
And 5, inputting the first counting difference, the second counting difference, the minimum gain control word Gh1 of the high-pass path, the maximum gain control word Gh2 of the high-pass path and the expected value delta Kexp of the counting difference into a linear calculation module, and directly calculating to obtain the gain calibration value of the high-pass path according to a binary linear equation in the linear calculation module.
The invention discloses a gain calibration module of a high-pass path in a two-point modulation phase-locked loop, which comprises a fixed duration counter, two subtracters and a gain calibration value linear calculation module.
Selecting a minimum high-pass path gain control word Gh1, and converting the frequency variation on the VCO into a counting difference delta K1 by using a counting method under the gain control word; selecting a maximum high-pass path gain control word Gh2, and converting the frequency variation on the VCO into a counting difference delta K2 by a counting method under the gain control; based on the two groups of values (Gh1, delta K1) and (Gh2, delta K2), a binary linear equation between the gain and the count difference on the high-pass path is constructed, and the gain calibration value of the high-pass path is directly calculated by combining the expected value of the count difference calculated in advance based on the low-pass path.
The functional block diagram of the gain calibration module of the present invention is shown in fig. 3, and in order to reduce the implementation difficulty and power consumption of the digital circuit, the high frequency signal Fvco is divided by M to obtain a low frequency division signal (T) with a period of M × TvcoVCO＝1/FVCO) The counting period is typically constructed based on a period (TREF) of a phase-locked loop reference frequency FREF, such as N × TREF. Inputting the count value into a fixed-duration counter for counting, the count value K can be expressed by equation (1) in a fixed-duration counting period N × Tref:
K＝(N*Tref)/(M*TVCO) Formula (1)
M and N are integers greater than or equal to 1.
According to TVCO＝1/FVCOAnd Tref 1/Fref, equation (1) can be transformed into:
K＝(N/(M*Fref))*FVCOformula (2)
As can be seen from the equation (2), the sum F of the count value KVCOIn direct proportion, the size of K directly reflects FVCOThe magnitude of (3) and, correspondingly, the amount of change in K also directly reflect FVCOLet the change in K be Δ K and F beVCOIf the variation of (d) is denoted as Δ fH, then:
Δ K ═ (N/(M · Fref)). DELTA.fH formula (3)
It can be measured by the change Δ K of the count value KQuantity FVCOThe amount of change Δ fH.
As shown in FIG. 5, the smallest high pass path gain control word Gh is selected1IN the gain control word, a minimum value (DAC _ IN ═ MIN) is first input to the DAC data input terminal, and the frequency-divided signal (F) of the VCO is divided IN the count period of the fixed time periodVCO/M) to obtain a count value K11(ii) a Then, a maximum value (DAC _ IN ═ MAX) is input to the DAC data input terminal, and the VCO frequency-divided signal is counted again IN the count period of the fixed length to obtain a count value K12(ii) a Thereby obtaining a current gain control word Gh1Corresponding count difference Δ K1＝K12-K11. Selecting the largest high-pass path gain control word Gh2Under the gain control word, firstly, inputting the minimum value at the DAC data input end, counting the VCO frequency division signal in the counting period of the fixed time length, and obtaining the counting value K21(ii) a Then inputting the maximum value at the DAC data input end, counting the VCO frequency division signal again in the counting period of the fixed time length to obtain a counting value K22(ii) a Thereby obtaining a current gain control word Gh2Corresponding count difference Δ K2＝K22–K21. The input of the DAC is a digital quantity, such as a 5-bit DAC, and the input minimum value is that 5 bits are all 0; the input maximum is 5 bits and all 1's.
Is prepared from (Gh)1，ΔK1) And (Gh)2，ΔK2) These two sets of values can result in a linear relationship between the variables Gh and Δ K, which can be expressed as a linear equation of two dimensions, as shown in fig. 6, as shown in equation (4):
ΔK＝(ΔK2-ΔK1)/(Gh2-Gh1)*(Gh-Gh1)+ΔK1formula (4)
By shifting Gh to the left of the equal sign, formula (4) can be re-expressed as formula (5):
Gh＝[(Gh2-Gh1)*ΔK-ΔK1]/(ΔK2-ΔK1)+Gh1formula (5)
As can be seen from the above, when TX _ DATA goes through the low-pass path from a minimum value (MIN) to a maximum, the amount of frequency change introduced on the VCO is given by Δ fL; as is known from the principle of phase-locked loops PLL,
ΔfL＝Fref*(MAX-MIN)/Q，
where Q is the quantization base number, when the gains of the high-pass path and the low-pass path are equal, Δ fH ═ Δ fL, and the count difference when the gains are equal is defined as the desired count difference Δ Kexp, according to equation (3), the desired count difference Δ Kexp should be obtained
ΔKexp＝(N*ΔfL)/(M*FREF)＝(N/M)*((MAX-MIN)/Q)
In the formula, the minimum and maximum values of N, M, TX _ DATA and the quantization base number Q are known quantities, so Δ Kexp can be calculated in advance; based on the binary linear equation of Gh and Δ K in equation (5), let Δ K equal to Δ Kexp, the desired high-pass gain control word Ghexp can be directly calculated, i.e. the calibration value of the gain control word is obtained, as shown in equation (6).
Ghexp＝[(Gh2-Gh1)*ΔKexp-ΔK1]/(ΔK2-ΔK1)+Gh1Formula (6)
The solving process can be as shown by the arrow in fig. 6, that is, according to the linear relationship between Gh and Δ K, as long as Δ Kexp in the ordinate is determined, the corresponding Ghexp in the abscissa can be obtained.
The above description is for the purpose of illustrating embodiments of the invention and is not intended to limit the invention, and it will be understood by those skilled in the art that any modification, equivalent replacement, or improvement made without departing from the spirit and principle of the present invention shall fall within the protection scope of the present invention.
Claims (10)
1. A gain calibration method of a high-pass path in a two-point modulation phase-locked loop comprises the following steps:
step 1, constructing a counting period with fixed duration;
step 2, obtaining a first counting value, a second counting value, a third counting value and a fourth counting value by using a fixed duration counter;
step 3, a first subtracter is used for carrying out subtraction operation on the first counting value and the second counting value to obtain a first counting difference (delta K)1)；
Step 4, a second subtracter is used for carrying out subtraction operation on the third counting value and the fourth counting value to obtain a second counting difference (delta K)2)；
Step 5, calculating the first counting difference (delta K)1) Second count difference (Δ K)2) And inputting the minimum gain control word (Gh1) of the high-pass path, the maximum gain control word (Gh2) of the high-pass path and the expected value (delta Kexp) of the counting difference into a linear calculation module, and directly calculating the gain calibration value of the high-pass path according to a binary linear equation in the linear calculation module.
2. The gain calibration method according to claim 1, wherein: the step 3 and the step 4 are two parallel steps without limiting the sequence.
3. The gain calibration method according to claim 2, wherein: the method for acquiring the first count value and the second count value comprises the following steps:
when the gain control word of the high-pass path is minimum, firstly inputting a minimum value at the data input end of the digital-to-analog converter, and counting the frequency division signal of the high-frequency signal output by the voltage-controlled oscillator by using a fixed time length counter in the counting period of the fixed time length to obtain a first counting value; and then inputting a maximum value at the data input end of the digital-to-analog converter, and counting the frequency division signal of the high-frequency signal output by the voltage-controlled oscillator by using a fixed time length counter in the counting period of the fixed time length to obtain a second counting value.
4. The gain calibration method according to claim 2, wherein: the third count value and the fourth count value are obtained by the following method: when the gain control word of the high-pass path is maximum, firstly, inputting a minimum value at the data input end of the digital-to-analog converter, and counting the frequency division signal of the high-frequency signal output by the voltage-controlled oscillator by using a fixed time length counter in the counting period of the fixed time length to obtain a third counting value; and then inputting a maximum value at the data input end of the digital-to-analog converter, and counting the frequency division signal of the high-frequency signal output by the voltage-controlled oscillator by using a fixed time length counter in the counting period of the fixed time length to obtain a fourth counting value.
5. The gain calibration method according to any one of claims 1 to 4, wherein: the counting period of the fixed duration is obtained by multiplying the period of the reference frequency of the phase-locked loop by an integer which is more than or equal to 1.
6. The gain calibration method according to claim 1, wherein: the binary linear equation is Ghexp ═ Gh [ ("Gh")2-Gh1)*ΔKexp-ΔK1]/(ΔK2-ΔK1)+Gh1。
7. The gain calibration method according to claim 6, wherein: the expected count difference value (Δ Kexp) is obtained by introducing a predictable frequency variation to a voltage-controlled oscillator of the phase-locked loop when the transmission data changes from a minimum value to a maximum value through a low-pass path in the two-point modulation phase-locked loop, and recording the count difference corresponding to the predictable frequency variation as the expected count difference.
8. The gain calibration method according to claim 7, wherein: the transmission data is simultaneously input to a low-pass path and a high-pass path to a two-point modulation phase-locked loop, and when the gains of the high-pass path and the low-pass path are equal, the transmission data changes from a minimum value to a maximum value, and the frequency change amounts on the voltage-controlled oscillators introduced through the low-pass path and the high-pass path are equal.
9. The gain calibration method according to claim 3, wherein: the frequency-divided signal is obtained by dividing the high-frequency signal by an integer which is greater than or equal to 1.
10. A gain calibration module of a high-pass path in a two-point modulation phase-locked loop is characterized in that: the device comprises a fixed duration counter, a first subtracter, a second subtracter and a linear calculation module; the frequency division signal of the high-frequency signal output by the voltage-controlled oscillator is sent to the input end of the fixed duration counter; the fixed duration counter outputs a first count value, a second count value, a third count value and a fourth count value, wherein the first count value and the second count value are input to the first subtracter, and the third count value and the fourth count value are input to the second subtracter; the first subtracter subtracts the first counting value and the second counting value to obtain a first counting difference, the second subtracter subtracts the third counting value and the fourth counting value to obtain a second counting difference, the first counting difference, the second counting difference, the minimum gain control word (Gh1) of the high-pass path, the maximum gain control word (Gh2) of the high-pass path and the expected value (delta Kexp) of the counting difference are input to the linear calculation module, the gain calibration value of the high-pass path is calculated according to a calculation formula set in the linear calculation module, and the gain calibration value is input to the digital-to-analog converter of the high-pass path, so that the gain of the high-pass path is equal to the gain of the low-pass path.
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE602004011937D1 (en) * | 2004-09-15 | 2008-04-03 | St Microelectronics Srl | Method for calibrating the frequency of an oscillator in a phase locked loop |
| US20100066459A1 (en) * | 2008-09-16 | 2010-03-18 | Samsung Electronics Co., Ltd. | Two-point phase modulator and method of calibrating conversion gain of the same |
| US20130015892A1 (en) * | 2011-07-13 | 2013-01-17 | Stmicroelectronics (Grenoble 2) Sas | Double-point modulator with accurate and fast gain calibration |
| CN103427839A (en) * | 2013-08-28 | 2013-12-04 | 贵州中科汉天下电子有限公司 | Calibrating method for digital/analog conventer used for two-point modulation and two-point modulation circuit |
| CN104734696A (en) * | 2013-12-24 | 2015-06-24 | 上海海尔集成电路有限公司 | Phase-locked loop frequency calibration circuit and method |
| CN104767575A (en) * | 2015-04-22 | 2015-07-08 | 清华大学 | Gain calibration method for high-pass closed circuit digital-to-analog converter in two-point modulation transmitter |
| CN107846222A (en) * | 2017-11-16 | 2018-03-27 | 上海华虹集成电路有限责任公司 | A kind of digital analog converter gain self-calibration circuit |
| CN107968687A (en) * | 2016-10-20 | 2018-04-27 | 国民技术股份有限公司 | A kind of two points modulation transmitter calibration circuit and calibration method |
-
2019
- 2019-09-18 CN CN201910879540.4A patent/CN110690899B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE602004011937D1 (en) * | 2004-09-15 | 2008-04-03 | St Microelectronics Srl | Method for calibrating the frequency of an oscillator in a phase locked loop |
| US20100066459A1 (en) * | 2008-09-16 | 2010-03-18 | Samsung Electronics Co., Ltd. | Two-point phase modulator and method of calibrating conversion gain of the same |
| US20130015892A1 (en) * | 2011-07-13 | 2013-01-17 | Stmicroelectronics (Grenoble 2) Sas | Double-point modulator with accurate and fast gain calibration |
| CN103427839A (en) * | 2013-08-28 | 2013-12-04 | 贵州中科汉天下电子有限公司 | Calibrating method for digital/analog conventer used for two-point modulation and two-point modulation circuit |
| CN104734696A (en) * | 2013-12-24 | 2015-06-24 | 上海海尔集成电路有限公司 | Phase-locked loop frequency calibration circuit and method |
| CN104767575A (en) * | 2015-04-22 | 2015-07-08 | 清华大学 | Gain calibration method for high-pass closed circuit digital-to-analog converter in two-point modulation transmitter |
| CN107968687A (en) * | 2016-10-20 | 2018-04-27 | 国民技术股份有限公司 | A kind of two points modulation transmitter calibration circuit and calibration method |
| CN107846222A (en) * | 2017-11-16 | 2018-03-27 | 上海华虹集成电路有限责任公司 | A kind of digital analog converter gain self-calibration circuit |
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