CN111800127A - Phase-locked loop circuit - Google Patents

Abstract

The invention discloses a phase-locked loop circuit. The core of the circuit includes an analog proportional path and a digital integral path. The integral path includes two digital integrators, which can jointly or separately control the VCO circuit. The present invention overcomes the shortcomings of pure analog phase-locked loop or pure digital phase-locked loop circuit, and can be used not only in ordinary output fixed frequency phase-locked loop occasions, but also in FMCW, SSC and other specific occasions.

Description

Phase Locked Loop Circuit

technical field

The present invention relates to the technical field of phase-locked loop circuits, in particular to a phase-locked loop circuit with a hybrid double integral architecture.

Background technique

In modern electronic systems, phase-locked loops have a wide range of applications. For example, in high-speed IO interfaces, PLLs (PhaseLockedLoop) are used to generate transmit and receive clocks. In wireless communication systems, PLLs are used to generate various FM tones. phase signal. In the millimeter wave radar system, PLL is used to generate FMCW (FrequencyModulatedContinuousWave, frequency modulated continuous wave) signal.

The phase locked loop can be implemented by traditional analog methods, including a PFD (phase frequency detector), CP (charge pump), LPF (analog low pass filter), VCO (voltage controlled oscillator), frequency divider, etc. part. Corresponding to the analog implementation, the all-digital phase-locked loop ADPLL has become more and more common in recent years. In the ADPLL, the LPF, VCO and CP are all implemented in a digital way. Compared with the analog phase-locked loop, ADPLL has the characteristics of easy transfer to other processes and more suitable for low-voltage advanced processes.

Although ADPLL no longer needs an analog circuit, the PFD circuit based on TDC (time-to-digital conversion) requires high precision to reduce in-band noise. The circuit is generally very complex. Although BBPFD has no precision requirements, it is due to its nonlinear problem. It also introduces problems such as finite loops and small signal transfer functions that are seriously affected by noise.

The hybrid PLL of the hybrid structure combines the advantages of the two PLLs. Usually the hybrid PLL contains two paths, an analog proportional path and a digital integral path. This kind of PLL not only retains the characteristics that digital PLL is easy to transplant and is very easy to implement for CMOS circuits, but also retains the characteristics of linear phase response in analog PLL, so it is more and more popular in use.

In addition, in some specific applications, such as FMCW or SSC, the PLL is required to generate a modulated signal whose frequency changes over time. For general PLLs (including the above-mentioned analog, digital or mixed architecture PLLs), it is necessary to A phase difference will be generated at the input of the phase detector (PFD), which will not only increase the noise of the system, but also increase the design difficulty of circuits such as charge pumps.

Therefore, in view of the above technical problems, it is necessary to provide a new phase-locked loop circuit.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a phase-locked loop circuit to solve the problems of easy noise and high cost when applied in a specific field in the prior art.

In order to achieve the above purpose, the technical solution provided by an embodiment of the present invention is as follows:

In one embodiment, a phase-locked loop circuit includes:

a frequency discriminator, receiving an input signal and a feedback signal, and generating a plurality of control signals based on a phase comparison of the input signal and the feedback signal;

an analog proportional path that receives the control signal from the frequency and phase detector and generates a first control signal of a voltage controlled oscillator based on the control signal;

Digital integration paths, including:

TDC/BB, the input of which is coupled to the input or output of the frequency and phase detector;

a first integrator, the input of which is connected to the output of the TDC/BB;

a second integrator, the input of which is connected to the output end of the first integrator, the output signal of the first integrator and the output signal of the second integrator are added to generate the second control signal of the voltage-controlled oscillator, Or the output signal of the first integrator and the output signal of the second integrator are directly used as the second control signal of the voltage-controlled oscillator;

a voltage controlled oscillator that receives the first control signal and the second control signal as input and generates an output signal having a frequency based on the first control signal and the second control signal;

A feedback path is coupled to the voltage controlled oscillator to receive the output signal and generate the feedback signal.

Preferably, in the above-mentioned phase-locked loop circuit, the first integrator includes a first adder and a first register, an input end of the first register is connected to an output end of the first adder, and the first adder is connected to the output end of the first adder. The output of a register is connected to the input of the first adder.

Preferably, in the above-mentioned phase-locked loop circuit, the second integrator includes a second adder and a second register, the input end of the second register is connected to the output end of the second adder, and the second adder is connected to the output end of the second adder. The output of the two registers is connected to the input of the second adder.

Preferably, in the above-mentioned phase-locked loop circuit, the second integrator further includes a third adder and a gain module,

The output signal of the first integrator is subtracted by the third adder and a constant, and the output is sent to the second adder after passing through the gain module.

Preferably, in the above-mentioned phase-locked loop circuit, the digital integration path further includes a gain adjustment module,

The gain adjustment module is configured to gain the output signal from the TDC/BB and then send it to the first integrator.

Preferably, in the above-mentioned phase-locked loop circuit, the analog proportional path includes:

a charge pump that receives the control signal from the frequency and phase detector and generates an initial voltage-controlled oscillator control signal based on the control signal;

a loop filter to generate the first control signal based on the initial voltage controlled oscillator control signal.

Preferably, in the above-mentioned phase-locked loop circuit, the loop filter includes a resistor and a capacitor connected in series between the output terminal of the charge pump and the ground.

Preferably, in the above-mentioned phase-locked loop circuit, the feedback path includes a frequency divider, an input end of the frequency divider is connected to the output end of the voltage-controlled oscillator, and the other end of the frequency divider is connected to the output end of the voltage-controlled oscillator. The input terminal is connected to the frequency control word, and the output terminal of the frequency divider is connected to the input terminal of the frequency and phase detector.

In one embodiment, a phase-locked loop circuit includes:

TDC/BB;

a first integrator, the input of which is connected to the output of the TDC/BB;

a second integrator whose input is connected to an output of the first integrator;

an adder, two input ends of which are respectively coupled to the other output end of the first integrator and the output end of the second integrator.

In one embodiment, a phase-locked loop circuit includes:

a first integrator, comprising a first adder and a first register, the input end of the first register is connected to the output end of the first adder, and the output end of the first register is connected to the first adder the input terminal;

The second integrator includes a second adder, a second register, a third adder and a gain module, the input end of the second register is connected to the output end of the second adder, and the output end of the second register connected to the input of the second adder, the output signal of the first integrator is subtracted by the third adder and a constant, and the output is sent to the second adder after passing through the gain module;

A gain adjustment module, the gain adjustment module is configured to gain a control signal and then send it to the first integrator.

Compared with the prior art, the present invention provides a new hybridPLL architecture, which not only retains the characteristics that digital PLLs are easy to transplant and is very easy to implement for CMOS circuits, but also retains the characteristics of linear phase response in analog PLLs. It is also suitable for use in specific occasions such as FMCW or SSC.

Description of drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the accompanying drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only These are some embodiments described in this application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings without any creative effort.

1 is a schematic diagram of a phase-locked loop circuit in the first embodiment of the present application;

FIG. 2 is a schematic diagram of a double integrator circuit in an embodiment of the present application;

3 is a schematic diagram of a phase-locked loop circuit in a second embodiment of the present application;

FIG. 4 is a schematic diagram of a phase-locked loop circuit in a third embodiment of the present application.

Detailed ways

The present invention will be described in detail below with reference to the various embodiments shown in the accompanying drawings. However, these embodiments do not limit the present invention, and the structural, method, or functional transformations made by those of ordinary skill in the art based on these embodiments are all included in the protection scope of the present invention.

Referring to FIG. 1, a first embodiment of the present invention provides a phase-locked loop circuit. The phase-locked loop includes a phase frequency detector (PFD) 101, and the phase frequency detector 101 receives an input reference clock refclk and a feedback clock fbclk.

The frequency discriminator 101 has a plurality of output terminals coupled to the charge pump 102 for outputting UP and DN signals. The charge pump 102 in turn has an output coupled to a loop filter, which in turn is coupled to a voltage controlled oscillator (VCO) 103 . The output terminal of the VCO 103 is coupled to the input terminal of the frequency and phase detector 101 via the frequency divider 111 .

The loop filter may use any type of filter, however as an example the filter includes a resistor 104 and a capacitor 105 in series between the output terminal of the charge pump 102 and ground. Resistor 104 and capacitor 105 form a parallel RC filter.

The output signal Fout is fed back to the input of the system through the frequency divider 111 as the feedback signal fbclk to generate a negative feedback loop.

The phase-locked loop circuit also includes a digital integration path, which includes a time-to-digital converter circuit 106 and a double integration circuit 109 .

The UP, DN signals are supplied to the charge pump 102 and the time-to-digital converter circuit 106, respectively. Charge pump 102 generates a current output that flows through resistor 104 and capacitor 105 to generate control voltage vprop, which is used as an analog control voltage for VCO 103. The other end of resistor 104 is connected to a DC bias level. Charge pump 102, resistor 104 and capacitor 105 constitute the analog proportional path of the hybrid PLL. The output tdc of the time-to-digital converter circuit 106 is sent to the double integrator circuit 109. The double integrator circuit 109 includes a first integrator 107 and a second integrator 108. The outputs int1 and int2 of the first integrator 107 and the second integrator 108 are phase-phased. After adding, the digital control word sent to VCO103 is used to adjust the frequency of VCO. The time-to-digital converter circuit 106 and the double integration circuit 109 constitute the digital integration path of the hybrid PLL. The output fout of the VCO103 is also input to the feedback frequency divider 111. Another input of the frequency divider 111 is the frequency control word FCW, and its output is the feedback clock fbclk, which is input to the PFD to form a loop.

Referring to FIG. 2 , which is an implementation of the double integrator circuit in this embodiment, the input signal tdc first passes through the gain adjustment module 201 to perform appropriate gain control on the input signal and then sends it to the first integrator, the first integrator 107 It is composed of an adder 202 and a register 203, and its output int1 is sent to both the adder 209 and the second integrator. The second integrator is composed of the adder 205, the gain module 206, the adder 207, and the register 208. The int1 passes through The adder 205 performs subtraction with a constant C, and the output of the adder 205 is sent to the integrator composed of the adder 207 and the register 208 after passing through the gain control module 206 . The outputs int2 and int1 of the second integrator are added together by the adder 209 to generate a digital control signal as a digital control word to control the frequency of the VCO.

In this embodiment, because the dual-channel structure is adopted, for a PLL with a fixed frequency output, when the locked state is in the state, the control voltage of the analog channel will be stable near the common-mode bias voltage, which greatly simplifies the design requirements for the charge pump. At the same time, the int1 of the double integral loop will be stable at the preset constant C. When we perform frequency adjustment such as FMCW, the int1 of the double integral loop will have a fixed deviation from the preset constant C, so that int2 will rise or fall with time to change the frequency of the VCO. Because int1 is a fixed value, this must require the output of TDC to be a value with an average value of 0. Therefore, when we use a double-integrated PLL for frequency scanning, the clocks of refclk and fbclk are still aligned, which greatly reduces the circuit noise while keeping the charge pump requirements low.

Another advantage of using dual paths is that, for the quantization noise with TDC, because only the integration path affects the loop, there is no need to use TDC with high quantization accuracy, which greatly reduces the requirements for TDC design.

Referring to FIG. 3, a second embodiment of the present invention provides a phase-locked loop circuit. The phase-locked loop includes a phase frequency detector (PFD) 301, which receives an input reference clock refclk and a feedback clock fbclk.

The frequency discriminator 301 has a plurality of output terminals coupled to the charge pump 302 for outputting UP and DN signals. The charge pump 302 in turn has an output coupled to a loop filter, which in turn is coupled to a voltage controlled oscillator (VCO) 303 . The output terminal of the VCO 303 is coupled to the input terminal of the frequency and phase detector 301 via the frequency divider 311 .

The loop filter may use any type of filter, however as an example the filter includes a resistor 304 and a capacitor 305 in series between the output terminal of the charge pump 302 and ground. Resistor 304 and capacitor 305 form a parallel RC filter.

The output signal Fout is fed back to the input of the system through the frequency divider 311 as the feedback signal fbclk to generate a negative feedback loop.

The phase-locked loop circuit also includes a digital integration path, which includes a time-to-digital converter circuit 306 and a double integration circuit 309 . The double integrator circuit 309 includes a first integrator 307 and a second integrator 308. The outputs int1 and int2 of the first integrator 307 and the second integrator 308 are added and then sent to the digital control word of the VCO 303 for adjusting the frequency of the VCO.

The difference between this embodiment and the first embodiment is that the digital phase detector based on TDC directly compares the phase difference between refclk and fbclk instead of using the updn signal to obtain the phase difference.

Referring to FIG. 4, a third embodiment of the present invention provides a phase-locked loop circuit. The phase locked loop includes a phase frequency detector (PFD) 401, which receives an input reference clock refclk and a feedback clock fbclk.

The frequency discriminator 401 has a plurality of output terminals coupled to the charge pump 402 for outputting UP and DN signals. The charge pump 402 in turn has an output coupled to a loop filter, which in turn is coupled to a voltage controlled oscillator (VCO) 403 . The output terminal of the VCO 403 is coupled to the input terminal of the frequency and phase detector 401 via the frequency divider 411 .

The loop filter may use any type of filter, however as an example the filter includes a resistor 404 and a capacitor 405 in series between the output terminal of the charge pump 402 and ground. Resistor 404 and capacitor 405 form a parallel RC filter.

The output signal Fout is fed back to the input of the system through the frequency divider 411 as the feedback signal fbclk to generate a negative feedback loop.

The phase-locked loop circuit also includes a digital integration path, which includes a time-to-digital converter circuit 406 and a double integration circuit 409 . The double integrator circuit 409 includes a first integrator 407 and a second integrator 408. The outputs int1 and int2 of the first integrator 407 and the second integrator 408 are added and then sent to the digital control word of the VCO 403 to adjust the frequency of the VCO.

The difference between this embodiment and the first embodiment is that the outputs of the two integrators are not added to control the VCO, but are directly controlled to the VCO respectively, and the addition is performed inside the VCO.

Both the first integrator and the second integrator need certain gain control to ensure system stability. Optionally, the time-to-digital converter circuit TDC106 can also be a bangbang structure.

It will be apparent to those skilled in the art that the present invention is not limited to the details of the above-described exemplary embodiments, but that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments are to be regarded in all respects as illustrative and not restrictive, and the scope of the invention is defined by the appended claims rather than the foregoing description, which are therefore intended to fall within the scope of the appended claims. All changes within the meaning and range of the equivalents of , are included in the present invention. Any reference signs in the claims shall not be construed as limiting the involved claim.

In addition, it should be understood that although this specification is described according to embodiments, not every embodiment only includes an independent technical solution, and this description in the specification is only for the sake of clarity, and those skilled in the art should take the specification as a whole , the technical solutions in each embodiment can also be appropriately combined to form other implementations that can be understood by those skilled in the art.

Claims (10)

1. A phase-locked loop circuit, comprising:

a phase frequency detector receiving an input signal and a feedback signal and generating a plurality of control signals based on a phase comparison of the input signal and the feedback signal;

an analog proportional path receiving the control signal from the phase frequency detector and generating a first control signal for a voltage controlled oscillator based on the control signal;

a digital integration path comprising:

a TDC/BB with its input coupled to the phase frequency detector input or output;

a first integrator having an input connected to an output of the TDC/BB;

the input of the second integrator is connected to the output end of the first integrator, and the output signal of the first integrator and the output signal of the second integrator are added to generate a second control signal of the voltage-controlled oscillator, or the output signal of the first integrator and the output signal of the second integrator are directly used as the second control signal of the voltage-controlled oscillator;

a voltage controlled oscillator receiving the first control signal and the second control signal as inputs and generating an output signal having a frequency based on the first control signal and the second control signal;

a feedback path coupled to the voltage controlled oscillator to receive the output signal and generate the feedback signal.

2. The phase-locked loop circuit of claim 1, wherein the first integrator comprises a first adder and a first register having an input coupled to an output of the first adder, and an output of the first register coupled to an input of the first adder.

3. The phase-locked loop circuit of claim 1, wherein the second integrator comprises a second adder and a second register, an input of the second register being coupled to an output of the second adder, an output of the second register being coupled to an input of the second adder.

4. The phase-locked loop circuit of claim 3, wherein the second integrator further comprises a third summer and a gain module,

the output signal of the first integrator is subtracted by the third adder and a constant, and the output of the first integrator is sent to the second adder after passing through the gain module.

5. The phase locked loop circuit of any of claims 1 to 3, wherein the digital integration path further comprises a gain adjustment module,

the gain adjustment module is configured to gain the output signal from TDC/BB before feeding into the first integrator.

6. The phase-locked loop circuit of claim 1, wherein the analog proportional path comprises:

a charge pump receiving the control signal from the phase frequency detector and generating an initial voltage controlled oscillator control signal based on the control signal;

a loop filter that generates the first control signal based on the initial voltage controlled oscillator control signal.

7. The phase-locked loop circuit of claim 6, wherein the loop filter comprises a resistor and a capacitor connected in series between the output terminal of the charge pump and ground.

8. The phase-locked loop circuit of claim 1, wherein the feedback path comprises a frequency divider, one input of the frequency divider is connected to the output of the voltage-controlled oscillator, another input of the frequency divider is connected to the frequency control word, and an output of the frequency divider is connected to the input of the phase frequency detector.

9. A phase-locked loop circuit, comprising:

TDC/BB；

a first integrator having an input connected to an output of the TDC/BB;

a second integrator, the input of which is connected to an output end of the first integrator;

an adder having two inputs coupled to the other output of the first integrator and the output of the second integrator, respectively.

10. A phase-locked loop circuit, comprising:

a first integrator comprising a first adder and a first register having an input coupled to an output of the first adder and an output coupled to an input of the first adder;

the second integrator comprises a second adder, a second register, a third adder and a gain module, wherein the input end of the second register is connected to the output end of the second adder, the output end of the second register is connected to the input end of the second adder, the output signal of the first integrator is subtracted through the third adder and a constant, and the output of the first integrator is sent to the second adder after passing through the gain module;

a gain adjustment module configured to gain a control signal prior to being fed into the first integrator.

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