CN111800127A - Phase-locked loop circuit - Google Patents
Phase-locked loop circuit Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
- H03L7/113—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using frequency discriminator
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Abstract
The invention discloses a phase-locked loop circuit, which comprises an analog proportional path and a digital integral path, wherein the integral path comprises two digital integrators which can jointly or respectively control a VCO circuit. The invention overcomes the defects of a pure analog phase-locked loop or a pure digital phase-locked loop circuit, can be used in the occasions of common phase-locked loops outputting fixed frequency, and can also be used in specific occasions such as FMCW, SSC and the like.
Description
Technical Field
The invention relates to the technical field of phase-locked loop circuits, in particular to a phase-locked loop circuit with a hybrid double-integration framework.
Background
Phase Locked Loops (PLLs) are widely used in modern electronic systems, such as high-speed IO interfaces for generating transmit and receive clocks, and wireless communication systems for generating various frequency modulated phase modulated signals. In the millimeter wave radar system, a PLL is used to generate an FMCW (frequency modulated continuous wave) signal.
The phase-locked loop may be implemented in a conventional analog manner, and includes a PFD (phase frequency detector), a CP (charge pump), an LPF (analog low-pass filter), a VCO (voltage controlled oscillator), a frequency divider, and so on. In response to analog implementation, the ADPLL, in which LPF, VCO, and CP are implemented in digital form, has become more popular in recent years. Compared with an analog phase-locked loop, the ADPLL has the characteristics of being easy to transfer to other processes, being more suitable for low-voltage advanced processes and the like.
Although the ADPLL no longer needs an analog circuit, the TDC (time to digital conversion) -based PFD circuit needs high precision to reduce in-band noise, the circuit is generally very complex, and the BBPFD has no precision requirement, but also introduces problems of a finite loop and a small signal transfer function, which are seriously affected by noise due to the nonlinear problem of the BBPFD.
Hybrid-architecture hybrid PLLs combine the advantages of both PLLs, typically a hybrid PLL comprising two paths, an analog proportional path and a digital integral path. Such a PLL retains the characteristics of a digital PLL that is easy to transplant and very easy to implement in CMOS circuits, as well as the characteristics of a linear phase response in an analog PLL, and is therefore increasingly popular in use.
In addition, in some specific applications, such as FMCW or SSC, a PLL is required to generate a modulation signal with a frequency changing with time, and for a general PLL (including the above-mentioned PLL with analog, digital or hybrid architecture), a phase difference is inevitably generated at an input terminal of a phase detector (PFD), which increases noise of the system and design difficulty of circuits such as a charge pump.
Therefore, in view of the above technical problems, it is necessary to provide a new phase-locked loop circuit.
Disclosure of Invention
The invention aims to provide a phase-locked loop circuit to solve the problems that noise is easy to generate and cost is high when the phase-locked loop circuit is applied in a specific field in the prior art.
In order to achieve the above object, an embodiment of the present invention provides the following technical solutions:
in one embodiment, a phase-locked loop circuit includes:
a phase frequency detector receiving an input signal and a feedback signal and generating a plurality of control signals based on a phase comparison of the input signal and the feedback signal;
an analog proportional path receiving the control signal from the phase frequency detector and generating a first control signal for a voltage controlled oscillator based on the control signal;
a digital integration path comprising:
a TDC/BB with its input coupled to the phase frequency detector input or output;
a first integrator having an input connected to an output of the TDC/BB;
the input of the second integrator is connected to the output end of the first integrator, and the output signal of the first integrator and the output signal of the second integrator are added to generate a second control signal of the voltage-controlled oscillator, or the output signal of the first integrator and the output signal of the second integrator are directly used as the second control signal of the voltage-controlled oscillator;
a voltage controlled oscillator receiving the first control signal and the second control signal as inputs and generating an output signal having a frequency based on the first control signal and the second control signal;
a feedback path coupled to the voltage controlled oscillator to receive the output signal and generate the feedback signal.
Preferably, in the phase-locked loop circuit described above, the first integrator includes a first adder and a first register, an input terminal of the first register is connected to an output terminal of the first adder, and an output terminal of the first register is connected to an input terminal of the first adder.
Preferably, in the phase-locked loop circuit described above, the second integrator includes a second adder and a second register, an input terminal of the second register is connected to an output terminal of the second adder, and an output terminal of the second register is connected to an input terminal of the second adder.
Preferably, in the phase-locked loop circuit described above, the second integrator further includes a third adder and a gain block,
the output signal of the first integrator is subtracted by the third adder and a constant, and the output of the first integrator is sent to the second adder after passing through the gain module.
Preferably, in the phase-locked loop circuit, the digital integration path further comprises a gain adjustment module,
the gain adjustment module is configured to gain the output signal from TDC/BB before feeding into the first integrator.
Preferably, in the phase-locked loop circuit described above, the analog proportional path includes:
a charge pump receiving the control signal from the phase frequency detector and generating an initial voltage controlled oscillator control signal based on the control signal;
a loop filter that generates the first control signal based on the initial voltage controlled oscillator control signal.
Preferably, in the phase-locked loop circuit described above, the loop filter includes a resistor and a capacitor connected in series between the output terminal of the charge pump and ground.
Preferably, in the phase-locked loop circuit described above, the feedback path includes a frequency divider, one input terminal of the frequency divider is connected to the output terminal of the voltage-controlled oscillator, the other input terminal of the frequency divider is connected to the frequency control word, and the output terminal of the frequency divider is connected to the input terminal of the phase frequency detector.
In one embodiment, a phase-locked loop circuit includes:
TDC/BB；
a first integrator having an input connected to an output of the TDC/BB;
a second integrator, the input of which is connected to an output end of the first integrator;
an adder having two inputs coupled to the other output of the first integrator and the output of the second integrator, respectively.
In one embodiment, a phase-locked loop circuit includes:
a first integrator comprising a first adder and a first register having an input coupled to an output of the first adder and an output coupled to an input of the first adder;
the second integrator comprises a second adder, a second register, a third adder and a gain module, wherein the input end of the second register is connected to the output end of the second adder, the output end of the second register is connected to the input end of the second adder, the output signal of the first integrator is subtracted through the third adder and a constant, and the output of the first integrator is sent to the second adder after passing through the gain module;
a gain adjustment module configured to gain a control signal prior to being fed into the first integrator.
Compared with the prior art, the invention provides a novel hybrid PLL architecture, which not only keeps the characteristics that a digital PLL is easy to transplant and is very easy to realize for a CMOS circuit, but also keeps the characteristic of linear phase response in an analog PLL, and is also suitable for being used in specific occasions such as FMCW or SSC.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a schematic diagram of a phase-locked loop circuit according to a first embodiment of the present application;
FIG. 2 is a schematic diagram of a dual integrator circuit in an embodiment of the present application;
FIG. 3 is a schematic diagram of a phase-locked loop circuit according to a second embodiment of the present application;
fig. 4 is a schematic diagram of a phase-locked loop circuit according to a third embodiment of the present application.
Detailed Description
The present invention will be described in detail below with reference to embodiments shown in the drawings. The embodiments are not intended to limit the present invention, and structural, methodological, or functional changes made by those skilled in the art according to the embodiments are included in the scope of the present invention.
Referring to fig. 1, a phase-locked loop circuit is provided in a first embodiment of the present invention. The phase locked loop includes a Phase Frequency Detector (PFD)101, the phase frequency detector 101 receiving an input reference clock refclk and a feedback clock fbclk.
The phase frequency detector 101 has a plurality of output terminals coupled to the charge pump 102 for outputting UP and DN signals. The charge pump 102 in turn has an output coupled to a loop filter, which in turn is coupled to a Voltage Controlled Oscillator (VCO) 103. The output of the VCO103 is coupled to the input of the phase frequency detector 101 via a frequency divider 111.
The loop filter may use any type of filter, however, by way of example, the filter includes a resistor 104 and a capacitor 105 connected in series between the output terminal of the charge pump 102 and ground. Resistor 104 and capacitor 105 form a parallel RC filter.
The output signal Fout is fed back to the input of the system as a feedback signal fbclk through a frequency divider 111 to create a negative feedback loop.
The phase locked loop circuit also includes a digital integration path that includes a time-to-digital converter circuit 106 and a double integration circuit 109.
The UP and DN signals are fed to the charge pump 102 and the time-to-digital converter circuit 106, respectively. The charge pump 102 generates a current flow through a resistor 104 and a capacitor 105, generating a control voltage vprop as an analog control voltage for the VCO103, the other end of the resistor 104 terminating a dc bias level. The charge pump 102, resistor 104 and capacitor 105 make up the analog proportional path of the hybrid PLL. The output tdc of the time-to-digital converter circuit 106 is sent to a double integration circuit 109, the double integration circuit 109 includes a first integrator 107 and a second integrator 108, and the outputs int1 and int2 of the first integrator 107 and the second integrator 108 are added and then sent to the digital control word of the VCO103 to adjust the frequency of the VCO. Time-to-digital converter circuit 106 and double integrating circuit 109 form the digital integration path of the hybrid PLL. The output fout of the VCO103 is also input to the feedback frequency divider 111, and the other input of the frequency divider 111 is the frequency control word FCW, and its output is the feedback clock fbclk, which is input to the PFD to form a loop.
Referring to fig. 2, which is an implementation manner of the double-integration circuit in this embodiment, an input signal tdc passes through a gain adjustment module 201, performs appropriate gain control on the input signal, and then sends the input signal to a first integrator, where the first integrator 107 is composed of an adder 202 and a register 203, an output int1 of the first integrator is sent to both the adder 209 and a second integrator, the second integrator is composed of an adder 205, a gain module 206, an adder 207, and a register 208, an int1 performs subtraction by using the adder 205 and a constant C, and an output of the int1 is sent to an integrator composed of the adder 207 and the register 208 after passing through the gain control module 206. The outputs int2 and int1 of the second integrator are summed together by the summer 209 to produce a digital control signal that is used as a digital control word to control the frequency of the VCO.
In this embodiment, because a dual-channel structure is adopted, for a PLL outputting a fixed frequency, when the PLL is in a locked state, the control voltage of the analog channel is stabilized near the common-mode bias voltage, which greatly simplifies the design requirements for the charge pump. While int1 for the double integration loop species settles at a preset constant C. When frequency adjustment such as FMCW is performed, int1 of the double integration loop generates a fixed deviation from a preset constant C, so that int2 increases or decreases with time to change the frequency of the VCO. Since int1 is a fixed value, which necessarily requires that the TDC output be a value with an average value of 0, when we use a double-integrated PLL for frequency sweeping, the clocks of refclk and fbclk remain aligned, which greatly reduces the noise of the circuit while keeping the low requirements on the charge pump.
Another benefit of using a dual path is the quantization noise to the TDC, since the loop is only affected by the integration path, and there is no need to use a TDC with very high quantization accuracy, which greatly reduces the requirements for TDC design.
Referring to fig. 3, a phase-locked loop circuit is provided in a second embodiment of the present invention. The phase locked loop includes a Phase Frequency Detector (PFD)301, which phase frequency detector 301 receives an input reference clock refclk and a feedback clock fbclk.
The phase frequency detector 301 has a plurality of output terminals coupled to the charge pump 302 for outputting UP and DN signals. The charge pump 302 in turn has an output coupled to a loop filter, which in turn is coupled to a Voltage Controlled Oscillator (VCO) 303. The output of VCO303 is coupled to the input of phase frequency detector 301 via frequency divider 311.
The loop filter may use any type of filter, however, by way of example, the filter includes a resistor 304 and a capacitor 305 in series between the output terminal of the charge pump 302 and ground. Resistor 304 and capacitor 305 form a parallel RC filter.
The output signal Fout is fed back to the input of the system as a feedback signal fbclk through a frequency divider 311 to create a negative feedback loop.
The phase locked loop circuit also includes a digital integration path that includes a time-to-digital converter circuit 306 and a double integration circuit 309. The double integrator 309 comprises a first integrator 307 and a second integrator 308, and the outputs int1 and int2 of the first integrator 307 and the second integrator 308 are added and then sent to the digital control word of the VCO303 to adjust the frequency of the VCO.
This embodiment differs from the first embodiment in that the TDC-based digital phase detector directly compares the phase difference of refclk and fbclk rather than using the updn signal to derive the phase difference.
Referring to fig. 4, a phase-locked loop circuit is provided in a third embodiment of the present invention. The phase locked loop includes a Phase Frequency Detector (PFD)401, which phase frequency detector 401 receives an input reference clock refclk and a feedback clock fbclk.
The phase frequency detector 401 has a plurality of output terminals coupled to the charge pump 402 for outputting UP and DN signals. The charge pump 402 in turn has an output coupled to a loop filter, which in turn is coupled to a Voltage Controlled Oscillator (VCO) 403. The output of VCO403 is coupled to the input of phase frequency detector 401 via frequency divider 411.
The loop filter may use any type of filter, however, by way of example, the filter includes a resistor 404 and a capacitor 405 in series between the output terminal of the charge pump 402 and ground. Resistor 404 and capacitor 405 form a parallel RC filter.
The output signal Fout is fed back to the input of the system as a feedback signal fbclk through a frequency divider 411 to create a negative feedback loop.
The phase locked loop circuit also includes a digital integration path that includes a time-to-digital converter circuit 406 and a double integration circuit 409. The double integrator circuit 409 comprises a first integrator 407 and a second integrator 408, and the outputs int1 and int2 of the first integrator 407 and the second integrator 408 are added and then sent to the digital control word of the VCO403 to adjust the frequency of the VCO.
The difference between this embodiment and the first embodiment is that the outputs of the two integrators are not added and then used to control the VCO, but are directly used to control the VCO and added inside the VCO.
Both the first integrator and the second integrator require a certain gain control to ensure the system stability, and optionally, the TDC106 may also be a bangbang structure.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.
Claims (10)
1. A phase-locked loop circuit, comprising:
a phase frequency detector receiving an input signal and a feedback signal and generating a plurality of control signals based on a phase comparison of the input signal and the feedback signal;
an analog proportional path receiving the control signal from the phase frequency detector and generating a first control signal for a voltage controlled oscillator based on the control signal;
a digital integration path comprising:
a TDC/BB with its input coupled to the phase frequency detector input or output;
a first integrator having an input connected to an output of the TDC/BB;
the input of the second integrator is connected to the output end of the first integrator, and the output signal of the first integrator and the output signal of the second integrator are added to generate a second control signal of the voltage-controlled oscillator, or the output signal of the first integrator and the output signal of the second integrator are directly used as the second control signal of the voltage-controlled oscillator;
a voltage controlled oscillator receiving the first control signal and the second control signal as inputs and generating an output signal having a frequency based on the first control signal and the second control signal;
a feedback path coupled to the voltage controlled oscillator to receive the output signal and generate the feedback signal.
2. The phase-locked loop circuit of claim 1, wherein the first integrator comprises a first adder and a first register having an input coupled to an output of the first adder, and an output of the first register coupled to an input of the first adder.
3. The phase-locked loop circuit of claim 1, wherein the second integrator comprises a second adder and a second register, an input of the second register being coupled to an output of the second adder, an output of the second register being coupled to an input of the second adder.
4. The phase-locked loop circuit of claim 3, wherein the second integrator further comprises a third summer and a gain module,
the output signal of the first integrator is subtracted by the third adder and a constant, and the output of the first integrator is sent to the second adder after passing through the gain module.
5. The phase locked loop circuit of any of claims 1 to 3, wherein the digital integration path further comprises a gain adjustment module,
the gain adjustment module is configured to gain the output signal from TDC/BB before feeding into the first integrator.
6. The phase-locked loop circuit of claim 1, wherein the analog proportional path comprises:
a charge pump receiving the control signal from the phase frequency detector and generating an initial voltage controlled oscillator control signal based on the control signal;
a loop filter that generates the first control signal based on the initial voltage controlled oscillator control signal.
7. The phase-locked loop circuit of claim 6, wherein the loop filter comprises a resistor and a capacitor connected in series between the output terminal of the charge pump and ground.
8. The phase-locked loop circuit of claim 1, wherein the feedback path comprises a frequency divider, one input of the frequency divider is connected to the output of the voltage-controlled oscillator, another input of the frequency divider is connected to the frequency control word, and an output of the frequency divider is connected to the input of the phase frequency detector.
9. A phase-locked loop circuit, comprising:
TDC/BB；
a first integrator having an input connected to an output of the TDC/BB;
a second integrator, the input of which is connected to an output end of the first integrator;
an adder having two inputs coupled to the other output of the first integrator and the output of the second integrator, respectively.
10. A phase-locked loop circuit, comprising:
a first integrator comprising a first adder and a first register having an input coupled to an output of the first adder and an output coupled to an input of the first adder;
the second integrator comprises a second adder, a second register, a third adder and a gain module, wherein the input end of the second register is connected to the output end of the second adder, the output end of the second register is connected to the input end of the second adder, the output signal of the first integrator is subtracted through the third adder and a constant, and the output of the first integrator is sent to the second adder after passing through the gain module;
a gain adjustment module configured to gain a control signal prior to being fed into the first integrator.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112305515A (en) * | 2020-10-22 | 2021-02-02 | 南京矽典微系统有限公司 | Signal processing method, signal processing system and millimeter wave sensor chip |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110148488A1 (en) * | 2009-12-23 | 2011-06-23 | Hyung-Jin Lee | Digital phase locked loop with closed loop linearization technique |
| CN102648581A (en) * | 2009-12-07 | 2012-08-22 | 高通股份有限公司 | Configurable digital-analog phase locked loop |
| CN103684436A (en) * | 2012-09-10 | 2014-03-26 | 国际商业机器公司 | Phase locked loop circuit and method of generating clock signals using the phase locked loop |
| CN212413138U (en) * | 2020-08-11 | 2021-01-26 | 南京矽典微系统有限公司 | Phase-locked loop circuit |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102648581A (en) * | 2009-12-07 | 2012-08-22 | 高通股份有限公司 | Configurable digital-analog phase locked loop |
| US20110148488A1 (en) * | 2009-12-23 | 2011-06-23 | Hyung-Jin Lee | Digital phase locked loop with closed loop linearization technique |
| CN103684436A (en) * | 2012-09-10 | 2014-03-26 | 国际商业机器公司 | Phase locked loop circuit and method of generating clock signals using the phase locked loop |
| CN212413138U (en) * | 2020-08-11 | 2021-01-26 | 南京矽典微系统有限公司 | Phase-locked loop circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112305515A (en) * | 2020-10-22 | 2021-02-02 | 南京矽典微系统有限公司 | Signal processing method, signal processing system and millimeter wave sensor chip |
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