CN102035994A - Circuit and method for changing output video format without causing destruction - Google Patents
Circuit and method for changing output video format without causing destruction Download PDFInfo
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- CN102035994A CN102035994A CN2009101964427A CN200910196442A CN102035994A CN 102035994 A CN102035994 A CN 102035994A CN 2009101964427 A CN2009101964427 A CN 2009101964427A CN 200910196442 A CN200910196442 A CN 200910196442A CN 102035994 A CN102035994 A CN 102035994A
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Abstract
The invention relates to a circuit and a method for changing the output video format without causing destruction, in particular to a circuit and a method for processing the video signals in a channel with limited pixel frequency bandwidth by way of incompressible video signals. The circuit comprises a programmable clock synchronization generating circuit, an output video format generating circuit connected with the output end of the programmable clock synchronization generating circuit and an input and output format configuration module respectively connected with the programmable clock synchronization generating circuit and the output video format generating circuit. The invention can realize the change of black-out period of the video signals and compensate output video signal non-standardization or pixel lose caused by bandwidth limitation under the condition that valid pixels of video are completely nondestructive.
Description
Technical field
The present invention relates to a kind of circuit and method of harmless change output video form, specifically be meant the circuit and the method for non-compression video signal processing vision signal in the passage that limits the dot frequency bandwidth.
Background technology
In the non-compression video transmission, the valid pixel part and the blanking signal that need transmission video signal, the input pixel clock was not identical with output pixel clock when the non-compression video signal did not lose the valid pixel transmission in by traditional processing system for video, non-compressed word vision signal can be subjected to the restriction of digital visual interface bandwidth by video interface transmission with when receiving or in order to reduce the bandwidth requirement in transmission and the processing procedure, the digital video pixel clock frequency can not surpass certain upper limit, such as in order to satisfy in a binary channels DVI signal the non-compressed word vision signal of accepting three road 1680x1050@60Hz resolution, the pixel clock frequency that requires every road signal to take is lower than 110Mhz.But the dot frequency of the digital video signal of the 1680x1050@60Hz resolution of a standard is 119Mhz, therefore the digital signal of the 1680x1050 resolution that this system originally can't transmission process three road 60Hz, can only be by reducing refresh rate or losing valid pixel and reduce the method for blanking time and come processing signals, reducing refresh rate can directly cause the output video quality to descend, a lot of video display apparatus (display etc.) can't be worked, cause video quality to descend between the meeting of loss valid pixel, reduce the blanking time of input signal because the vision signal that causes exporting is non-standard, make final output signal can't on video display apparatus, show or cause the picture skew.Therefore these methods all can't solve input video clock frequency harmless problem that realizes video output when limited.
In sum, be necessary to design a kind of circuit of harmless change output video form and method to address the above problem.
Summary of the invention
Technical problem to be solved by this invention is to provide circuit and the method that the present invention relates to a kind of harmless change output video form, be used for and keeping the video valid pixel not have fully under the prerequisite of loss, realize the conversion in black-out of video signal cycle, compensation is owing to outputting video signal nonstandardized technique or pixel that bandwidth constraints causes are lost.
For addressing the above problem, the present invention adopts following technical scheme: a kind of circuit of harmless change output video form, this circuit comprise that programmable clock produces circuit synchronously, produces output video form that circuit output end is connected synchronously with programmable clock and produce circuit and produce circuit synchronously with programmable clock and produce the input/output format configuration module that circuit links to each other with the output video form;
Described input/output format configuration module is used to obtain the configuration parameter of incoming video signal and required output signal, and this configuration parameter is input to programmable clock synchronization after by code conversion produces circuit;
Described programmable clock produces circuit synchronously and is used for producing specific clock signal according to the form of the form of incoming video signal and required output signal;
Described output video form produces circuit and produces the required output signal that specific clock signal produces and the incoming video signal maintenance is synchronous that circuit produces synchronously according to described programmable clock.
The present invention further comprises a kind of method of harmless change output video form, and this method may further comprise the steps:
1) programmable clock produces circuit synchronously and obtains the output video sampling clock by the input and output frequency ratio that the input and output configuration module provides; Described input and output frequency ratio is obtained by the ratio of input video head office pixel and required output video head office pixel;
2) output video form generation circuit utilizes programmable clock to produce the output video sampling clock generation outputting video signal of circuit synchronously;
3) valid pixel of the valid pixel of described outputting video signal part and incoming video signal partly keeps synchronously, and the blanking pixel portion of outputting video signal is adjusted by the input and output configuration module;
4) the input and output configuration module is input to programmable clock with the format information of newly-generated outputting video signal as feedback information and produces circuit synchronously;
5) corresponding output video data useful signal, output video field sync signal and output video line synchronizing signal produce circuit by the output video form and regenerate.
The present invention can can't harm under input video dot frequency confined condition and change the output video form, realizes the conversion in black-out of video signal cycle, and compensation is owing to outputting video signal nonstandardized technique or pixel that bandwidth constraints causes are lost.
The present invention relates to a kind of non-compression video signal and in the passage that limits the dot frequency bandwidth, handle the method for vision signal, this method can keep the video valid pixel not have fully under the prerequisite of loss, realize the conversion in black-out of video signal cycle, compensation is owing to outputting video signal nonstandardized technique or pixel that bandwidth constraints causes are lost.
Description of drawings:
Fig. 1 is a block diagram of the present invention.
Embodiment
Referring now to accompanying drawing 1 one embodiment of the present of invention are described.
A kind of circuit of harmless change output video form, this circuit comprise that programmable clock produces circuit synchronously, produces output video form that circuit output end is connected synchronously with programmable clock and produce circuit and produce circuit synchronously with programmable clock and produce the input/output format configuration module that circuit links to each other respectively with the output video form.
The input/output format configuration module is used to produce configuration information, and it is the input and output frequency ratio that the input/output format configuration module offers the configuration information that programmable clock produces circuit synchronously; The configuration information that the input/output format configuration module provides the output video form to produce circuit is the output video format parameter.
Described programmable clock produces the input video clock that circuit utilizes incoming video signal synchronously, the form (being the input and output frequency ratios) of the form of the incoming video signal that provides according to the input/output format configuration module and required output signal produces specific clock signal, produces the output video sampling clock on the basis of its input video clock in incoming video signal.
Incoming video signal comprises inputting video data, inputting video data useful signal, input video field sync signal, input video line synchronizing signal and input video clock, the output video form produces circuit, it utilizes programmable clock to produce the output video sampling clock of circuit output synchronously, produce the field synchronization of outputting video signal according to incoming video signal, row synchronously, data useful signal and output video clock, valid pixel and incoming video signal that the output video form produces the outputting video signal that circuit produces keep synchronous in time.
Described programmable clock produces circuit synchronously and adopts Direct Digital Frequency Synthesizers or phase-locked loop to cooperate the programmable configuration circuit to realize, this programmable clock produces circuit synchronously and draws configuration parameter according to clock frequency, head office's pixel count of the input and the form of required outputting video signal, the phase-locked loop of configuration Direct Digital Frequency Synthesizers or configurable input and output, incoming video signal is input to the phase-locked loop of this Direct Digital Frequency Synthesizers or configurable input and output branch frequency multiplication ratio, then can export required output video clock according to configuration parameter.The output video form produces circuit and utilizes this output video clock as clock signal, valid pixel with this clock signal sampling incoming video signal, because this output frequency clock is to produce according to required output video form, though therefore export clock and input clock different (generally export clock and be higher than input clock), but because the also proportional relation of the total pixel of corresponding output (comprising blanking cycle) (the total pixel of output video is generally greater than the total pixel of input video), the time of a vision signal is identical in the time and output of a vision signal of input, therefore input and output still keep can not losing any valid pixel synchronously.
Incoming video signal is divided into valid pixel part and blanking signal part, and passing through among the present invention reduces the blanking signal cycle, thereby reduces the input video clock frequency of incoming video signal, keeps input valid pixel part.
Concrete, incoming video signal comprises inputting video data, inputting video data useful signal, input video field sync signal, input video line synchronizing signal and input video clock, wherein, the incoming video signal frequency is f1, the total pixel of the every row of input video is N, wherein the valid pixel number is N1, and the horizontal blanking pixel count is N2 (N=N1+N2); The restriction that incoming video signal frequency f 1 is subjected to the video interface bandwidth must be lower than fmax, if at this moment can be by reducing the blanking pixel in this interface otherwise reduce refresh rate and reduce valid pixel, be that N2 satisfies bandwidth constraints, if adopt also identical output format to cause to output to that display device can't show or problem such as video skew but reduce under the situation of standard value that N2 is lower than the standard video format defined output format, therefore adopting as shown in Figure 1, the output video form produces the video format that processing of circuit enters.
The input and output configuration module provides the parameter information of the form of output signal, it is constant that described output video form generation circuit still keeps the every capable valid pixel of video to count N1, but the horizontal blanking pixel count increases to M2, therefore the increase of head office's pixel count is M (M=N1+M2), at this moment the frequency f 2 of output video clock also must increase accordingly in proportion, just the frequency f 2=f1* of output video clock (M/N).
Therefore, adopt a programmable clock to produce circuit synchronously, it obtains the configuration parameter of input and output frequency dividing ratio by the input and output configuration module, this configuration parameter is input to Direct Digital Frequency Synthesizers or configurable phase-locked loop (the clock synchronization circuit the inside) after by code conversion, thereby on the basis of input video clock, produce synchronous output video sampling clock, at this moment the output video form produces circuit and utilizes this synchronised clock sampling incoming video signal, generate outputting video signal, because clock generates synchronously in the ratio that increases, therefore the effective video data of output and input still keep synchronously, do not lose any valid pixel, and the blanking pixel of output can reach the requirement of video standard signal form or be increased to the quantity that needs arbitrarily by increase, only need that newly-generated output video format information (the total pixel of output row) is configured to clock synchronization as feedback information and produce circuit, corresponding data useful signal, field sync signal and line synchronizing signal also can produce circuit by video format and produce the signal that meets the video standard sequential, and the video format in output has not only satisfied the standard display requirement of various display devices but also do not lost the valid pixel of any input like this.
To sum up, the method for a kind of harmless change output video form of the present invention may further comprise the steps:
1) programmable clock produces circuit synchronously and obtains the output video sampling clock by the input and output frequency ratio that the input and output configuration module provides; Described input and output frequency ratio is obtained by the ratio of input video head office pixel and required output video head office pixel;
2) output video form generation circuit utilizes programmable clock to produce the output video sampling clock generation outputting video signal of circuit synchronously;
3) valid pixel of the valid pixel of described outputting video signal part and incoming video signal partly keeps synchronously, and the blanking pixel portion of outputting video signal is adjusted by the input and output configuration module;
4) the input and output configuration module is input to programmable clock with the format information of newly-generated outputting video signal as feedback information and produces circuit synchronously;
5) corresponding output video data useful signal, output video field sync signal and output video line synchronizing signal produce circuit by the output video form and regenerate.
The foregoing description just lists expressivity principle of the present invention and effect is described, but not is used to limit the present invention.Any personnel that are familiar with this technology all can make amendment to the foregoing description under spirit of the present invention and scope.Therefore, the scope of the present invention should be listed as claims.
Claims (4)
1. harmless circuit that changes the output video form is characterized in that: this circuit comprises that programmable clock produces circuit synchronously, produces the output video form that circuit output end is connected synchronously with programmable clock and produce circuit and produce the input/output format configuration module that circuit links to each other with output video form generation circuit synchronously with programmable clock;
Described input/output format configuration module is used to obtain the configuration parameter of incoming video signal and required output signal, and this configuration parameter is input to programmable clock synchronization after by code conversion produces circuit;
Described programmable clock produces circuit synchronously and is used for producing specific clock signal according to the form of the form of incoming video signal and required output signal;
Described output video form produces circuit and produces the required output signal that specific clock signal produces and the incoming video signal maintenance is synchronous that circuit produces synchronously according to described programmable clock.
2. the circuit of a kind of harmless change output video form as claimed in claim 1 is characterized in that: described configuration parameter comprises clock frequency, head office's pixel count of incoming video signal and required output signal.
3. the circuit of a kind of harmless change output video form as claimed in claim 1 is characterized in that: described input/output format configuration module is digital frequency synthesizer or phase-locked loop.
4. the method for a kind of harmless change output video form as claimed in claim 1 is characterized in that: this method may further comprise the steps:
1) programmable clock produces circuit synchronously and obtains the output video sampling clock by the input and output frequency ratio that the input and output configuration module provides; Described input and output frequency ratio is obtained by the ratio of input video head office pixel and required output video head office pixel;
2) output video form generation circuit utilizes programmable clock to produce the output video sampling clock generation outputting video signal of circuit synchronously;
3) valid pixel of the valid pixel of described outputting video signal part and incoming video signal partly keeps synchronously, and the blanking pixel portion of outputting video signal is adjusted by the input and output configuration module;
4) the input and output configuration module is input to programmable clock with the format information of newly-generated outputting video signal as feedback information and produces circuit synchronously;
5) corresponding output video data useful signal, output video field sync signal and output video line synchronizing signal produce circuit by the output video form and regenerate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101964427A CN102035994A (en) | 2009-09-25 | 2009-09-25 | Circuit and method for changing output video format without causing destruction |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101964427A CN102035994A (en) | 2009-09-25 | 2009-09-25 | Circuit and method for changing output video format without causing destruction |
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| CN102035994A true CN102035994A (en) | 2011-04-27 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2009101964427A Pending CN102035994A (en) | 2009-09-25 | 2009-09-25 | Circuit and method for changing output video format without causing destruction |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103873802A (en) * | 2012-12-18 | 2014-06-18 | 深圳市广平正科技有限责任公司 | High-definition video signal generator and signal generating method thereof |
| CN108010476A (en) * | 2017-11-29 | 2018-05-08 | 武汉精立电子技术有限公司 | A kind of video signal transmission clock generating device and method |
-
2009
- 2009-09-25 CN CN2009101964427A patent/CN102035994A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103873802A (en) * | 2012-12-18 | 2014-06-18 | 深圳市广平正科技有限责任公司 | High-definition video signal generator and signal generating method thereof |
| CN108010476A (en) * | 2017-11-29 | 2018-05-08 | 武汉精立电子技术有限公司 | A kind of video signal transmission clock generating device and method |
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Application publication date: 20110427 |