CN102103826A - Light emitting diode (LED) display screen splicing control system and LED display screen - Google Patents
Light emitting diode (LED) display screen splicing control system and LED display screen Download PDFInfo
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Abstract
The invention is applied in the field of display screens, and provides a light emitting diode (LED) display screen splicing control system and an LED display screen. The LED display screen splicing control system comprises a video processing and transmission controller, a video receiving and splitting amplifier and an LED screen body controller array, wherein the video processing and transmission controller comprises an input output interface, a first audio and video processor and a signal conversion and optical transmitter which are sequentially connected; the video receiving and splitting amplifier comprises an optical receiving and signal converter, a second audio and video processor, a video output module and an audio output interface which are sequentially connected; the optical receiving and signal converter is connected with the signal conversion and optical transmitter; and the LED screen body controller array comprises more than one shunt-wound single LED screen body controller. The LED display screen splicing control system and the LED display screen provided by the embodiment of the invention can realize the high-resolution display of the LED display screen by the video processing and transmission controller, the video receiving and splitting amplifier and the LED screen body controller array, and have simple designs and low cost.
Description
Technical field
The invention belongs to the display screen field, relate in particular to a kind of LED display splicing control system and LED display.
Background technology
At present, LED display has become the sign of modernization, internationalized city, and it can play Word message, animated advertising, video image, day by day in advertisement, physical culture, traffic, finance, communication, commerce, all trades and professions such as perform in a radio or TV programme and be widely used.The core technology of LED display is a LED display splicing control system, existing high-resolution LED display splicing Control System Design complexity, and the cost height costs an arm and a leg.
Summary of the invention
The purpose of the embodiment of the invention is to provide a kind of LED display splicing control system, is intended to solve LED display splicing Control System Design complexity common in the prior art, the problem that cost is high.
The embodiment of the invention is achieved in that a kind of LED display splicing control system, and described system comprises:
The Video processing transfer control comprises the IO interface, first audio video processor and conversion of signals and the optical transmitter that connect successively;
Video reception is cut apart amplifier, comprises the light-receiving and signal converter, second audio video processor, video output module and the audio output interface that connect successively, and described light-receiving and signal converter are connected with described conversion of signals and optical transmitter;
LED screen body controller array, comprise the more than one LED screen body controller monomer of connection arranged side by side, described LED screen body controller monomer comprises video signal input interface, DVI demoder, video secondary amplification processor and conversion of signals and the synchro control timing sequencer that is connected successively with described video output module; LED video data driving output module and output interface that described conversion of signals and synchro control timing sequencer also are connected with three grades of buffers and connect successively; Described LED screen body controller monomer also comprises and is used for shielding the two-way hardware external synchronization signal Peripheral Interface that the body controller monomer is connected and is connected with described conversion of signals and synchro control timing sequencer with adjacent LED.
The embodiment of the invention also provides a kind of LED display, and described LED display comprises described LED display splicing control system.
The embodiment of the invention compared with prior art, beneficial effect is: cut apart amplifier and LED screen body controller array by Video processing transfer control, video reception, can realize the demonstration of the LED display of ultrahigh resolution, and simplicity of design, cost is low.
Description of drawings
Fig. 1 is that the LED display that the embodiment of the invention provides is spliced the block diagram of control system;
Fig. 2 is that the LED display that the embodiment of the invention provides is spliced the logical design synoptic diagram of first audio video processor of control system;
Fig. 3 is that the LED display that the embodiment of the invention provides is spliced the conversion of signals of control system and the logical design synoptic diagram of optical transmitter;
Fig. 4 is the logical design synoptic diagram that the video reception of the LED display splicing control system that provides of the embodiment of the invention is cut apart amplifier;
Fig. 5 is the logical design synoptic diagram of the LED screen body controller monomer of the LED display splicing control system that provides of the embodiment of the invention.
Among the figure: 1. Video processing transfer control, 2. video reception is cut apart amplifier, 3.LED screen body controller array, 4.LED display screen, 5. power amplifier, 6. audio amplifier, 11. IO interface, 12. first audio video processor, 13. conversion of signals and optical transmitter, 14. computing machine, 21. light-receiving and signal converter, 22. second audio video processor, 23. video output modules, 24. audio output interface, 31-34. signal input interface, four LED screens of 41-44. body subregion, handover module is handled in the input of 121. videos, 122. audio processing modules, 123. the video format modular converter, 124.SDRAM, 125. high clear video image processing modules, 126.DDR, 127.FLASH, 128.DVI/RGB converter, 131.FPGA, 132. one-level frame memory, 133.serdes chip, 134. optic modules, 211. optic modules, 212.serdes chip, 221.FPGA, 222. secondary frame memories, 223. clock synchronization generators, 224. audio conversion processing module, 231.DVI conversion chip, 232.DVI output interface, 233. audio output interfaces, 310. two-way hardware external synchronization signal Peripheral Interface, 311. video signal interface, 312.DVI demoder, 313. video secondary amplification processors, 314. conversion of signals and synchro control timing sequencer, 315. three grades of buffers, the 316.LED video data drives output module, 317. output interfaces, 318.VGA conversion chip, the 319.VGA interface.
Embodiment
In order to make purpose of the present invention, technical scheme and advantage clearer,, the present invention is further elaborated below in conjunction with drawings and Examples.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.
See also Fig. 1 to Fig. 5, the LED display splicing control system that the embodiment of the invention provides, described system comprises:
Video processing transfer control 1, the video reception of Lian Jieing cut apart amplifier 2 and LED screen body controller array 3 successively, and described Video processing transfer control 1 comprises IO interface 11, first audio video processor 12 and conversion of signals and the optical transmitter 13 that connects successively.
IO interface 11 specifically comprises DVI/RGB input interface A, UART/USB serial ports B, infrared remote control mouth C, double-tone video input SDI/HD-SDI interface D, YpbPr interface E, YcbCr interface F, AV interface G, Svideo interface H, DVI interface I, HDMI interface J, audio frequency and video loop output SDI/HD-SDI interface K, video output DVI/RGB interface L and headphone monitor output interface M.
See also Fig. 2, first audio video processor 12 comprises audio frequency and video input processing handover module 121, audio processing modules 122, video format modular converter 123, SDRAM 124, high clear video image processing module 125, DDR 126, FLASH127 and DVI/RGB converter 128.Handling handover module 121 and the computing machine 14 that is connected with described IO interface 11 or button/Infrared remote controller by the audio frequency and video input can realize the switching of audio frequency and video input signal is selected; When the audio frequency and video input signal of user's needs is chosen in switching, send to video format modular converter 123 after the analog video input signal process AD conversion with needs, digital video input signal sends to high clear video image processing module 125, and sound signal sends to audio processing modules 122.The analog video input signal that described digital video modular converter 123 cooperates 124 couples of SDRAM to receive carries out the digital format conversion and delivers to high clear video image processing module 125 after the processing line by line, 125 pairs of described high clear video image processing modules receive 1 or 2 road video input signals and cooperate DDR 126 to carry out image optimization and after one-level is amplified and the OSD menu handles, it is (red to generate 30bit RGB, green, indigo plant) 1920 * 1080P high-definition digital video picture signal is divided into two-way output, one tunnel process DVI/RGB converter 128 is sent to the LCD monitor that is connected with described video output DVI/RGB interface L, described LCD monitor is used for LED display monitored in real time and shows to finish relevant parameters with the OSD menu and to regulate, input source selections etc., another road is then by being sent to conversion of signals and the optical transmitter 13 that is connected with described first audio video processor 12.Behind 122 pairs of selected audio frequency input carrying out audio decoders and multichannel A/D conversion of described audio processing modules, be divided into two-way, one tunnel simulating signal is sent to headphone monitor output interface M, and conversion of signals and the optical transmitter 13 that is connected with described first audio video processor 12 then is sent to serial digital audio signal on another road.Described FLASH127 also is connected with computing machine 14 by described UART/USB serial ports B, is used for storage control and initiation parameter.
At different video input signals, first audio video processor 12 can be carried out different processing, as AD conversion, system conversion, colour decoding, γ proofread and correct, interlacing is changeed line by line, storage, convergent-divergent, Motion Adaptive, picture-in-picture, picture out picture, edge treated etc.The optional VPC3230D of master chip, the optional MSP20G of master chip of audio processing modules 122, the optional FLI2310 of master chip of video format modular converter 123, the optional GM1601H of master chip of high clear video image processing module 125 of handover module 121 handled in described audio frequency and video input.
See also Fig. 3, conversion of signals and optical transmitter 13 comprise FPGA131, and described FPGA131 is connected with two one-level frame memories 132, and described FPGA131 is connected with serdes chip 133 and the optic module 134 that two-way connects successively.
FPGA131 is used for the high-definition digital video picture signal of input is sent to the one-level frame memory 132 that is used to carry out level cache, also be used for 30 RGB high-definition digital video picture signals are carried out the frequency multiplication conversion, after mixing, the parallel data stream of the two-way 16bit that generating rate doubles and digital audio and video signals, control signal be input to the serdes chip 133 in the two-way.
Concrete, because in the two-way 16bit parallel data stream after the frequency multiplication, a pixel is occupied 64bit, therefore deduct the also surplus 4bit of RGB data of 30 * 2bit, wherein 1bit is used for the embedding of low frequency digital sound signal, three embeddings that are used for control signal or other signal in addition.The parallel data stream that embeds low frequency digital sound signal and control signal or other signal is divided into two-way and is sent to serdes chip 133, serial data stream behind process and string conversion and the 8bit/10bit coding divides two-way to be sent to optic module 134 with the clock rate of 3.125G, is transferred to video reception through optic module 134 again and cuts apart amplifier 2.
See also Fig. 4, video reception is cut apart amplifier 2 and is comprised light-receiving and signal converter 21, second audio video processor 22, video output module 23 and the audio output interface 24 that connects successively.
Described light-receiving and signal converter 21 specifically comprise: the optic module 211 that is used to receive described two-way serial data stream is gone here and there to described two-way serial data stream with being used for of being connected with described optic module 211 and the serdes chip 212 of conversion, 8bit/10bit decoding and clock recovery; Wherein said two-way serial data stream is specially two-way 3.125G audio frequency and video serial data stream;
Described second audio video processor 22 specifically comprises: the FPGA221 that is connected with described serdes chip 212, two secondary frame memories 222 that are connected with described FPGA221, the clock synchronization generator 223 that is connected with described FPGA221 and audio conversion processing module 224;
Described video output module 23 specifically comprises: four road DVI conversion chips 231 that are connected with described FPGA221 and four DVI output interfaces 232.
Concrete, after optic module 211 receives serial data stream, through serdes chip 212 go here and there and conversion, 8bit/10bit decoding and clock recovery after generate the parallel data stream of two-way 16bit, be sent to FPGA221, FPGA221 parallel data stream to two-way 16bit under the control of clock synchronization generator 223 carries out sampling processing, solve voiceband data signal, video data signal and LED large-size screen monitors control signal, and deposit the video data signal of 30bit in secondary frame memory 222 and carry out buffer memory.Wherein FPGA221 is according to the area dividing parameter that comprises in the LED large-size screen monitors control signal, the data cutout that to read from secondary frame memory 222 is divided into four paths video datas and delivers to video output module 23, simultaneously in data cutout, adopted the intercepting zone redundancy more bigger than actual area, and circuit is adjusted, the problem of marginal existence difference when amplifying to solve the subregion video data in matched edges.
The voiceband data signal that 224 couples of FPGA221 of audio conversion processing module solve carries out DA conversion reduction and synchronous processing, delivers to power amplifier amplifier 5 and audio amplifier 6 by audio output interface 24 again.
Wherein, because each subregion edge flare appears in ultrahigh resolution LED display easily when debugging at the scene, tangible separatrix is arranged, had a strong impact on viewing effect, this causes owing to the high frequency sampling clock is asynchronous with video data, therefore, design clock synchronization generator 223 and be connected to FPGA221.
See also Fig. 1, LED screen body controller array 3 comprises four LED screen body controller monomer 31-34 of connection arranged side by side, and wherein the inside formation of LED screen body controller monomer sees also Fig. 5, comprising:
With corresponding video signal input interface 311, DVI demoder 312, video secondary amplification processor 313 and a conversion of signals and a synchro control timing sequencer 314 that connects successively of DVI output in 23 4 DVI outputs of described video output module.
Described conversion of signals and synchro control timing sequencer 314 also are connected with six tunnel LED video datas that connect successively and drive output module 316 and output interface 317, described conversion of signals and synchro control timing sequencer 314 also are connected with VGA converter 318 and the VGA interface 319 that is used for the subregion video monitor, and described conversion of signals and synchro control timing sequencer 314 also are connected with two three grades of buffers 315.
Described LED screen body controller monomer also comprises and is used for shielding the two-way hardware external synchronization signal Peripheral Interface 310 that the body controller monomer is connected and is connected with described conversion of signals and synchro control timing sequencer 314 with adjacent LED.
Concrete, DVI demoder 312 solves the video data signal of local area to video secondary amplification processor 313, the optional high-grade video image zooming chip of the master chip that video secondary processing and amplifying 313 adopts makes up, as support the high-grade 10bit video scaling chip ABT1030 of 24/30/36-bit RGB input and output, being used for that the video data signal that local area distributes is carried out the adjustable secondary of multiplying power amplifies in real time, the further optimization process of software inter-sync and image, generate video signal with the LED display opposite position, and send described conversion of signals and synchro control timing sequencer 314 to, described conversion of signals and the synchro control timing sequencer 314 concrete FPGA that adopt, after video data signal after conversion of signals and synchro control timing sequencer 314 will amplify deposits three grades of buffers 315 in, under the control of hardware external synchronization signal, remove unnecessary margin signal, and circuit is adjusted in matched edges, convert the video data signal of local area to meet the LED display form video data signal, and demultiplexing outputs to LED video data driving output module 316 simultaneously, the LED video data drives output module 316 and is made of multichannel kilomega network PHY or multichannel LVDS serdes chip, its every road output signal is sent to the LED scan control plate array that the LED subregion display screen body inside of appointed area is connected in series successively by output interface 317, demonstration by a LED module of each LED scan control plate control, thereby the amplification of video signal on the ultrahigh resolution full-color LED display screen of finishing from the varying input signal source shows that the LED scan control plate that it adopts is identical with general LED scan control plate.
In concrete the application, the chip model that replaceable first audio video processor 12 adopts, or change the multicore sheet scheme that first audio video processor 12 adopts into twin-core sheet scheme etc. that (for example SiI9251/9261), an audio frequency and video Flame Image Process (for example GF9452) are handled in an audio frequency and video input.
The embodiment of the invention also provides a kind of LED display, and described display screen comprises described LED display splicing control system.
Concrete, see also Fig. 1, in application, LED display 4 comprises four subregion display screen 41-44, four identical LED screen body controller 31-34 control four subregion display screen 41-44 work of LED display 4 respectively, LED screen body controller 31-34 also is serially connected with shared two-way hardware external synchronization signal each other successively simultaneously, can control LED screen body controller array 3 synchronous workings as the master control synchronizer by any LED screen body controller, with the synchronous demonstration of further assurance LED display 4.
In concrete the application, the quantity of subregion display screen can be selected as required, can be more than one.
LED display splicing control system and LED display that the embodiment of the invention provides, cut apart amplifier and LED screen body controller array by Video processing transfer control, video reception, can realize the demonstration of the LED display of ultrahigh resolution, and simplicity of design, cost is low.
The above only is preferred embodiment of the present invention, not in order to restriction the present invention, all any modifications of being done within the spirit and principles in the present invention, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. a LED display is spliced control system, it is characterized in that described system comprises:
The Video processing transfer control comprises the IO interface, first audio video processor and conversion of signals and the optical transmitter that connect successively;
Video reception is cut apart amplifier, comprises the light-receiving and signal converter, second audio video processor, video output module and the audio output interface that connect successively, and described light-receiving and signal converter are connected with described conversion of signals and optical transmitter;
LED screen body controller array, comprise the more than one LED screen body controller monomer of connection arranged side by side, described LED screen body controller monomer comprises video signal input interface, DVI demoder, video secondary amplification processor and conversion of signals and the synchro control timing sequencer that is connected successively with described video output module; LED video data driving output module and output interface that described conversion of signals and synchro control timing sequencer also are connected with three grades of buffers and connect successively; Described LED screen body controller monomer also comprises and is used for shielding the two-way hardware external synchronization signal Peripheral Interface that the body controller monomer is connected and is connected with described conversion of signals and synchro control timing sequencer with adjacent LED.
2. LED display splicing control system as claimed in claim 1, it is characterized in that described IO interface comprises DVI/RGB input interface, UART/USB serial ports, infrared remote control mouth, double-tone video input SDI/HD-SDI interface, YpbPr interface, YcbCr interface, AV interface, Svideo interface, DVI interface, HDMI interface, audio frequency and video loop output SDI/HD-SDI interface, video output DVI/RGB interface and headphone monitor output interface.
3. LED display splicing control system as claimed in claim 1, it is characterized in that, described first audio video processor comprises the audio frequency and video input processing handover module that is connected with described IO interface, handle audio processing modules, video format modular converter and the high clear video image processing module that handover module is connected with the audio frequency and video input, described high clear video image processing module also is connected with SDRAM, DDR, FLASH and DVI/RGB converter.
4. LED display splicing control system as claimed in claim 1, it is characterized in that, described conversion of signals and optical transmitter comprise and are used for video, audio frequency and control signal changed and the FPGA of the transmission process of packing, described FPGA is connected with two one-level frame memories, and described FPGA is connected with serdes chip and the optic module that two-way connects successively.
5. LED display splicing control system as claimed in claim 1, it is characterized in that described light-receiving and signal converter comprise that the optic module that is used to receive the two-way serial data stream and being used for of being connected with described optic module go here and there to described serial data stream and the serdes chip of conversion, 8bit/10bit decoding and clock recovery.
6. LED display splicing control system as claimed in claim 4, it is characterized in that described second audio video processor comprises: what be connected with described serdes chip is used for sound, video sampling decoding and video data is carried out FPGA, two secondary frame memories that are connected with described FPGA, the clock synchronization generator that is connected with described FPGA and the audio conversion processing module that multizone is divided.
7. LED display splicing control system as claimed in claim 5 is characterized in that described video output module comprises a plurality of DVI conversion chips and a plurality of DVI output interface that is connected successively with the multi-channel video output of described second audio video processor.
8. LED display splicing control system as claimed in claim 7 is characterized in that described video output module also comprises VGA conversion chip that is used for the subregion video monitor and the VGA interface that is connected with described second audio video processor.
9. LED display splicing control system as claimed in claim 1 is characterized in that described system also comprises power amplifier amplifier and the audio amplifier that is connected successively with described audio output interface.
10. a LED display is characterized in that, described LED display comprises the described LED display splicing of claim 1 control system.
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| CN2009101892289A CN102103826A (en) | 2009-12-22 | 2009-12-22 | Light emitting diode (LED) display screen splicing control system and LED display screen |
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| CN2009101892289A CN102103826A (en) | 2009-12-22 | 2009-12-22 | Light emitting diode (LED) display screen splicing control system and LED display screen |
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2009
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Application publication date: 20110622 Assignee: Shenzhen Konka Video System Engineering Co., Ltd. Assignor: Konka Group Co., Ltd. Contract record no.: 2012440020426 Denomination of invention: Light emitting diode (LED) display screen splicing control system and LED display screen License type: Exclusive License Record date: 20121226 |
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Application publication date: 20110622 |