CN103873802A - High-definition video signal generator and signal generating method thereof - Google Patents
High-definition video signal generator and signal generating method thereof Download PDFInfo
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Abstract
The invention discloses a high-definition video signal generator and a signal generating method thereof. An MCU (Micro-programmed Control Unit) module acquires parameters set by a user through a man-machine interface module to generate a driving parameter sent to each module; a clock generating module generates a corresponding clock signal according to a clock driving parameter from the MCU module and transmits the corresponding clock signal to a video signal generating module to serve as a reference clock; the video signal generating module generates a corresponding video signal according to the reference clock and a video driving parameter from the MCU module and transmits the corresponding video signal to an HDMI (High-Definition Multimedia Interface) sending module; the HDMI sending module converts the video signal into an HDMI signal according to an HDMI driving parameter from the MCU module and sends the HDMI signal; furthermore, an audio signal generating module generates an audio signal according to an audio driving parameter from the MCU module and transmits the audio signal to the HDMI sending module. The output parameter characteristic of the video signal can be optionally set by the method, and the application range of the signal generator is widened.
Description
technical fieldthe present invention relates to the digital video generator in electronic information field.
background technologyalong with the development of high definition Display Technique, for example HDMI(High Definition Multimedia Interface of band high-definition interface, HDMI (High Definition Multimedia Interface)) or DVI(Digital Visual Interface, digital video interface) display device or the transducer of interface move towards market in a large number.Can not catch up with development completely for the signal source of testing in the production process of these display devices or transducer.If use DVD, the classical signal such as PS3 and PC source, because these signal sources are generally to decide the suitable video/audio signal of output according to the EDID information of obtained rear end display device or transducer, and the video/audio signal form of each signal source output is limited, as common DVD, can only export and there is 480P, 720P, 1080I, the HDTV (High-Definition Television) signal of the common form such as 1080P, PC also can only export the VESA signal of limited form and differ video color space (video color space is arbitrarily set surely, for example RGB, YUV444 or YUV422) or video signal type(video signal type, for example HDMI or DVI) etc., its image resolution ratio providing is can choice less as can be seen here, it is inadequate that output attribute arranges flexibility, cannot meet our testing requirement.
If use existing special test equipment, these equipment volume are larger, operate more complicatedly, bring many inconvenience undoubtedly to test.
For this reason, the manufacturer of display device or transducer can attempt designing some portable signal generators for production test, the Patent Application Publication that for example publication number is CN201682555U a use FPGA(Field-Programmable Gate Array, field programmable gate array) the 3G-SDI high definition digital video signal generator that designs, to export the signal of multi-mode, multi-format.The weak point of the prior art is, the exportable signal format of described 3G-SDI high definition digital video signal generator depends on the still image that FPGA kernel deposits and produces algorithm, and user cannot carry out self-defined to output image resolution.
summary of the inventionthe technical problem to be solved in the present invention is for above-mentioned the deficiencies in the prior art part, and a kind of flying-spot video generator and signal generating method thereof are proposed, with according to the relevant output parameter of user's request arbitrary disposition, meet testing of equipment or the debugging demand of each level.
For solving the problems of the technologies described above, basic conception of the present invention is: according to the transmission of image and show essence, define and then produce image by basic driver parameter.
As the technical scheme that realizes the present invention's design be, a kind of high-definition video signal generator is provided, especially, comprise the clock generation module, vision signal generation module and the HDMI sending module that connect successively; Also comprise human-machine interface module and the MCU module of interconnection, MCU module also connects respectively described clock generation module, vision signal generation module and HDMI sending module.
In such scheme, described vision signal generation module comprises fpga chip.
As the technical scheme that realizes the present invention design still, a kind of signal generating method of high-definition video signal generator is provided, this high-definition video signal generator comprises the clock generation module, vision signal generation module and the HDMI sending module that connect successively, also comprise human-machine interface module and MCU module, especially, comprise step:
A. MCU module is obtained the parameter of user's setting and is produced thus the driving parameter that is sent to each module by human-machine interface module;
B. clock generating module drives parameter to generate corresponding clock signal according to the clock from MCU module, flows to vision signal generation module and is used as reference clock;
C. vision signal generation module is according to described reference clock with generate corresponding vision signal from the video drive parameter of MCU module and be sent to HDMI sending module;
D. HDMI sending module sends according to driving parameter to convert described vision signal to HDMI signal from the HDMI of MCU module.
In such scheme, described human-machine interface module comprises keypad or display screen, connects described MCU module by serial ports or USB interface.
Particularly, in such scheme, in step C, vision signal comprises synchronizing signal and viewdata signal, and the generation of this vision signal comprises: the step that generates described synchronizing signal according to described reference clock and described video drive parameter; Generate the step of respective image data signal according to described reference clock and described video drive parameter, described synchronizing signal.
Further, described video drive parameter comprises row total pixel number Htotal, and row valid pixel is counted Hactive, after row, account for pixel count Hback, before row, account for pixel count Hfront, total line number Vtotal, effectively line number Vactive, after, account for line number Vback and before account for line number Vfront; Described synchronizing signal comprises line synchronizing signal HSYNC, field sync signal VSYNC and data useful signal DE; Each described synchronizing signal produces according to this: two counters are set, comprise row pixel counter HCountPixel and frame linage-counter VCountLine, produce the state machine that synchronizing signal generates; Utilize reference clock to change to produce each synchronizing signal to the triggering of state machine.
In such scheme, described high-definition video signal generator also comprises audio signal generation module, produce the audio signal corresponding with described vision signal according to the audio driven parameter from MCU module, transmit toward described HDMI sending module for carrying out the conversion of HDMI signal.The parameter that described user arranges comprises video resolution, video color space, high-definition digital content protecting agreement, video signal type, video color depth bit wide, audio sampling frequency or audio sample bit wide.
These measures can so that client as required self-defined output want the vision signal of resolution, and the output parameter feature of vision signal can arbitrarily arrange, signal generator have volume little, operate, install advantage simply and easily, expanded undoubtedly the scope of application of this signal generator.
brief description of the drawingsfig. 1 is the structured flowchart of signal generator of the present invention;
Fig. 2 is the schematic flow sheet of signal generating method of the present invention;
Fig. 3 is sequential relationship schematic diagram between vision signal and each driving parameter;
Fig. 4 is a specific embodiment of synchronizing signal time sequence parameter relation;
Fig. 5 has illustrated corresponding HSYNC synchronizing signal state machine in Fig. 4 embodiment;
Fig. 6 has illustrated corresponding VSYNC synchronizing signal state machine in Fig. 4 embodiment;
Fig. 7 has illustrated corresponding DE synchronizing signal state machine in Fig. 4 embodiment;
Fig. 8 is the colour bar sequence schematic diagram of color bar signal in Fig. 4 embodiment;
Fig. 9 has illustrated the spatial relationship between synchronizing signal and Fig. 8 picture signal in Fig. 4 embodiment;
Figure 10 has illustrated the corresponding viewdata signal state machine of color bar signal in Fig. 4 embodiment;
Figure 11 is I2S format audio signal sequence schematic diagram;
Figure 12 is that an online parameter of signal generator of the present invention and PC arranges interface embodiment.
embodimentbelow, the most preferred embodiment shown in by reference to the accompanying drawings is further set forth the present invention.
Signal generator of the present invention as shown in Figure 1, comprises the clock generation module, vision signal generation module and the HDMI sending module that connect successively, also comprises human-machine interface module and the MCU module of interconnection.MCU module is such as but not limited to connect respectively described clock generation module, vision signal generation module and HDMI sending module by iic bus.Vision signal generation module can adopt fpga chip to realize.
Fig. 2 has illustrated signal of the present invention to produce flow process, comprises step:
Steps A. MCU module is obtained the parameter of user's setting and is produced thus the driving parameter that is sent to each module; Described obtaining can complete by human-machine interface module.Be that serial ports or USB interface are set on signal generator of the present invention for the most simple and clear mode of user, make signal generator of the present invention and PC online, and then control software with PC and arrange, Figure 12 has illustrated PC to control one of interface of software.To say from design angle, send command word by keypad and serial ports the most succinct, but in order being user-friendly to, described human-machine interface module can also to comprise that is used for showing a display screen of selecting interface.Further, human-machine interface module adopts the comprehensive strong point of above-mentioned two kinds of modes of touching display screen.
Step B. clock generating module drives parameter to generate corresponding clock signal according to the clock from MCU module, flows to vision signal generation module and is used as reference clock.This reference clock is the pixel clock of image/video form, and the pixel clock of different video formats is different.
Step C. vision signal generation module is according to described reference clock and generate corresponding vision signal from the video drive parameter of MCU module and be sent to HDMI sending module.The corresponding described video drive parameter of one width transmitting image comprises:
Row total pixel number Htotal(Horizontal total pixel), row valid pixel is counted Hactive,
After row, account for pixel count Hback, before row, account for pixel count Hfront;
The total line number Vtotal (Vertical total line) in field, effective line number Vactive,
After, account for line number Vback, before, account for line number Vfront;
Wherein, the vector of H beginning is taking pixel (pixel) as unit, and the vector of V beginning is taking row (line) as unit, pixel of 1 clock generating, and the pixel number that different video format 1 row (line) comprises is different.
Described vision signal comprises synchronizing signal and viewdata signal.Wherein synchronizing signal specifically comprises line synchronizing signal (HSYNC), field sync signal (VSYNC) and data useful signal (Data Enable, writes a Chinese character in simplified form DE).Sequential relationship between these synchronizing signals and described video drive parameter is as shown in Figure 3: data useful signal DE is the appearance of logical zero corresponding row blanking pixel count Hblank or field blanking pixel count Vblank, the appearance of counting Hactive for logical one corresponding row valid pixel; The separation in the ranks of each line synchronizing signal HSYNC pulse representative image, separates between the field of each field sync signal VSYNC pulse representative image, during these separations must appear at data useful signal DE and are logical zero, and meets relational expression
Hblank=?Htotal-?Hactive=Hfront+Hsync+Hback
With
Vblank=?Vtotal-?Vactive=Vfront+Vsync+Vback
Wherein Hsync and Vsync represent respectively the pulse duration (pulse pixel count) of row, field sync signal.
In the step of the present invention that Fig. 2 shows, the generation of vision signal can be divided into two steps:
Generate the step of described synchronizing signal according to described reference clock and described video drive parameter;
Generate the step of respective image signal according to described reference clock and described video drive parameter, described synchronizing signal.
With a specific embodiment that produces the color bar signal (as schematically shown in Figure 8) of 1920*1080P 60Hz, above-mentioned steps process is described below.
First produce synchronizing signal: in FPGA, establish two counter HCountPixel and VCountLine, as the pixel counter of every row and the linage-counter of every frame, suppose using moment SH1 and SV1 and count starting point as counter HCountPixel and VCountLine, make often to come the rising edge of a reference clock (for sake of convenience taking rising edge as example, can select moment SH1HSYNC rising edge, moment SV1 is VSYNC rising edge; Actually can select trailing edge or other triggering mode, herein lower with) just flip-flop number HCountPixel add 1, until HCountPixel equals to reset after Htotal, HCountPixel is 0; And the each equal flip-flop number VCountLine that resets of this counter HCountPixel adds 1, until this counter VCountLine equals to reset after Vtotal again, this counter VCountLine is 0.Can produce according to these two counter HCountPixel and VCountLine the state machine that synchronizing signal generates, trigger state machine variation with the rising edge of reference clock, can produce respectively HSYNC, VSYNC and DE signal according to Fig. 5,6 and 7 method.The synchronizing signal time sequence parameter of the present embodiment should be as shown in Figure 4, Hactive=1920, Htotal=2200, Hblank=280, Hsync=44, Hfront=88, Hback=148; Vactive=1080, Vblank=45, VSYNC rising edge of a pulse arises from the 1125th HSYNC rising edge, Vsync=5, Vblank=36, Vfront=4.Fig. 5 has illustrated HSYNC signal condition machine to change: often carry out a reference clock rising edge triggering HcountPixel and add one, taking the SH1 moment as starting point, (now HcountPixel=0), makes HSYNC=1; When HSNC=1, often carry out a reference clock rising edge and also judge whether this counter equals to drive in this embodiment of Parameter H sync(=44), keep if not HSYNC=1, if make HSYNC=0; When HSNC=0, often carrying out a reference clock rising edge also judges whether this counter equals to drive in this embodiment of Parameter H total(=2200), keep if not HSYNC=0, if make HSYNC=1, HcountPixel(=0 resets simultaneously) and make VCountLine add one.Utilize this state machine, can obtain the HSYNC signal shown in Fig. 4.Fig. 6 has illustrated VSYNC signal condition machine to change: often carry out reference clock rising edge and trigger HcountPixel and add one, until HCountPixel equals to reset after Htotal HCountPixel be 0 and flip-flop number VCountLine add 1; Taking the SV1 moment as starting point, (now VCountLine=0), makes VSYNC=1; When VSYNC=1, often carrying out a reference clock rising edge also judges whether counter HcountPixel equals to drive in this embodiment of Parameter H total(=2200) and counter VCountLine whether equal in this embodiment of Vsync(=5), keep if not VSYNC=1, if make VSYNC=0; When VSYNC=0, often carrying out a reference clock rising edge also judges whether counter HcountPixel equals to drive in this embodiment of Parameter H total(=2200) and counter VCountLine whether equal in this embodiment of Vtotal(=1125), keep if not HSYNC=0, if make VSYNC=1, VCountLine(=0 resets simultaneously).Utilize this state machine, can obtain the VSYNC signal shown in Fig. 4.Fig. 7 has illustrated DE signal condition machine to change: often come a reference clock rising edge judge HcountPixel whether be greater than drive in this embodiment of Parameter H sync(=44) and this embodiment of Hback(in=148) sum of the two, and whether this HcountPixel is less than or equal to Htotal(=2200) and the Hfront(=88) difference of the two, and whether counter VCountLine is greater than Vsync(=5) and Vback(=36) sum of the two, and whether this VCountLine is less than or equal to Vtotal(=1125) and the Vfront(=4) difference of the two; If above-mentioned judged result is no, make DE=0; If the determination result is YES, make DE=1.Utilize this state machine, can obtain the DE signal shown in Fig. 4.
After synchronizing signal produces, regeneration viewdata signal: as shown in Figure 9, the picture signal shown in Fig. 8 is used in every row Hactive and every Vactive term of validity the relation between synchronizing signal and picture signal.For this reason, the present invention establishes a counter HCountRGB in FPGA, is used as the state counter of every row Hactive, produces view data.This counter HCountRGB=0 in the time that Hactive is 0, Hactive is that the rising edge that often carrys out a reference clock at 1 o'clock triggers this counter HCountRGB and adds one.View data corresponding to Fig. 8 image, taking RGB444 8BIT form as example, supposes that colour bar is equidistant, and the width of each colour bar is 1920/8=240(pixel).Wherein white colour pattern is R=255 as corresponding view data, G=255, B=255; Yellow colour pattern is R=255 as corresponding view data, G=255, B=0; Blue or green colour pattern is R=0 as corresponding view data, G=255, B=255; Green colour pattern is R=0 as corresponding view data, G=255, B=0; Purple colour pattern is R=255 as corresponding view data, G=0, B=255; The corresponding view data of blusher bar image is R=255, G=0, B=0; Blue colour pattern is R=0 as corresponding view data, G=0, B=255; Black colour pattern is R=0 as corresponding view data, G=0, B=0.The state machine of image data generating signal RGB as shown in figure 10: often setting viewdata signal in the SV1 moment is R=255, G=255, B=255.The rising edge that often carrys out a reference clock triggers state machine counter HCountRGB and adds in the lump and once judge, decides the view data of output.Specifically, in the time of R=255, G=255 and B=255, judging whether this HCountRGB is more than or equal to 240, and output image data is constant if not, is R=255, G=255 and B=0 if change setting viewdata signal; In the time of R=255, G=255 and B=0, judge whether this HCountRGB is more than or equal to 480, and output image data is constant if not, be R=0, G=255 and B=255 if change setting viewdata signal; In the time of R=0, G=255 and B=255, judge whether this HCountRGB is more than or equal to 720, and output image data is constant if not, be R=0, G=255 and B=0 if change setting viewdata signal; In the time of R=0, G=255 and B=0, judge whether this HCountRGB is more than or equal to 960, and output image data is constant if not, be R=255, G=0 and B=255 if change setting viewdata signal; In the time of R=255, G=0 and B=255, judge whether this HCountRGB is more than or equal to 1200, and output image data is constant if not, be R=255, G=0 and B=0 if change setting viewdata signal; In the time of R=255, G=0 and B=0, judge whether this HCountRGB is more than or equal to 1440, and output image data is constant if not, be R=0, G=0 and B=255 if change setting viewdata signal; In the time of R=0, G=0 and B=255, judge whether this HCountRGB is more than or equal to 1680, and output image data is constant if not, be R=0, G=0 and B=0 if change setting viewdata signal; In the time of R=0, G=0 and B=0, judge whether this HCountRGB is more than or equal to 1920, output image data is constant if not, is R=255, G=255 and B=255 if change setting viewdata signal ... repeat successively to obtain the viewdata signal corresponding with Fig. 8.When the image resolution ratio requiring is not 1920*1080P, or image is not colour bar illustrated in Figure 8, respectively judges that the comparing data of institute's foundation is as 240,480, and 720 grades should adjust accordingly, and view data is also corresponding to be adjusted according to initial conditions.
Further, as shown in Figure 2, signal generator of the present invention also comprises audio signal generation module, produces the audio signal corresponding with the vision signal of described vision signal generation module output according to the audio driven parameter from MCU module, and the test that is more conducive to audio-visual equipment is used.This audio signal generation module produces the method for audio signal taking Figure 11 as example, for example produce I2S format audio signal, described audio driven parameter comprises sample frequency wclk and audio sample figure place (being the data length of AIN), audio signal generation module output signal comprises sample frequency wclk, position sampling clock sclk and voice data AIN, wherein sclk numerical value equals twice sample frequency wclk and amasss with audio sample figure place is.Described audio signal generation module can be, but not limited to can realize with same FPGA together with described vision signal generation module.Step D. HDMI sending module sends according to drive parameter to convert described vision signal (/ and described audio signal) to HDMI signal from the HDMI of MCU module.HDMI drives parameter to comprise picture signal type, the selection of video color space etc., and this conversion can complete such as but not limited to the chip of silicon image company with existing integrated circuit, does not therefore repeat at this.
Experimental results show that, signal generator of the present invention can carry out the relevant audiovisual output parameter of flexible configuration according to client's demand, comprise video resolution(video resolution), video color space(video color space, RGB/YUV444/YUV422), HDCP(high-definition digital content protecting agreement), video signal type (video signal type, HDMI/DVI), video deep color bit depth(video color depth bit wide), audio sampling rate (audio sampling frequency, 44.1k/48k), audio bit depth (audio sample bit wide, 16/20/24bit) etc.Figure 12 arranges interface as example taking the online parameter of PC, and user's parameter setting up procedure is described.By arranging, respectively drive parameter to be: pixel clock is set to 54, Htotal=1124, Hactive=848, Hblank=276, Hfront=32, Hsync=128, Vtotal=525, Vactive=480, Vbank=45, Vfront=9, Vsync=6.Correspondingly, lower signal generator of the present invention is set by the audio-video signal of a more rare output self-defined VESA 848X480 60hz at this.
The foregoing is only embodiments of the invention, not thereby limit the scope of the claims of the present invention, every various equivalent structure transformations that utilize specification of the present invention and accompanying drawing content to do, are all in like manner included in scope of patent protection of the present invention.
Claims (10)
1. a high-definition video signal generator, is characterized in that:
Comprise the clock generation module, vision signal generation module and the HDMI sending module that connect successively; Also comprise human-machine interface module and the MCU module of interconnection, MCU module also connects respectively described clock generation module, vision signal generation module and HDMI sending module.
2. high-definition video signal generator according to claim 1, is characterized in that:
Described vision signal generation module comprises fpga chip.
3. the signal generating method of a high-definition video signal generator, this high-definition video signal generator comprises the clock generation module, vision signal generation module and the HDMI sending module that connect successively, also comprise human-machine interface module and MCU module, it is characterized in that, comprise step:
A. MCU module is obtained the parameter of user's setting and is produced thus the driving parameter that is sent to each module by human-machine interface module;
B. clock generating module drives parameter to generate corresponding clock signal according to the clock from MCU module, flows to vision signal generation module and is used as reference clock;
C. vision signal generation module is according to described reference clock with generate corresponding vision signal from the video drive parameter of MCU module and be sent to HDMI sending module;
D. HDMI sending module sends according to driving parameter to convert described vision signal to HDMI signal from the HDMI of MCU module.
4. the signal generating method of high-definition video signal generator according to claim 3, is characterized in that:
In steps A, described human-machine interface module comprises keypad or display screen, connects described MCU module by serial ports or USB interface.
5. the signal generating method of high-definition video signal generator according to claim 3, is characterized in that, in step C, vision signal comprises synchronizing signal and viewdata signal, and the generation of this vision signal comprises:
Generate the step of described synchronizing signal according to described reference clock and described video drive parameter;
Generate the step of respective image data signal according to described reference clock and described video drive parameter, described synchronizing signal.
6. the signal generating method of high-definition video signal generator according to claim 5, is characterized in that:
Described video drive parameter comprises row total pixel number Htotal, and row valid pixel is counted Hactive, after row, accounts for pixel count Hback, before row, account for pixel count Hfront, total line number Vtotal, effectively line number Vactive, after, account for line number Vback and before account for line number Vfront;
Described synchronizing signal comprises line synchronizing signal HSYNC, field sync signal VSYNC and data useful signal DE; Each described synchronizing signal produces according to this: two counters are set, comprise row pixel counter HCountPixel and frame linage-counter VCountLine, produce the state machine that synchronizing signal generates; Utilize reference clock to change to produce each synchronizing signal to the triggering of state machine.
7. the signal generating method of high-definition video signal generator according to claim 6, is characterized in that:
Viewdata signal only comprises the data-signal of the each image pixel in every row Hactive and every Vactive term of validity.
8. the signal generating method of high-definition video signal generator according to claim 3, is characterized in that:
Described high-definition video signal generator also comprises audio signal generation module, produces the audio signal corresponding with described vision signal according to the audio driven parameter from MCU module, transmits toward described HDMI sending module for carrying out the conversion of HDMI signal.
9. the signal generating method of high-definition video signal generator according to claim 8, is characterized in that:
Described audio driven parameter comprises sample frequency wclk and audio sample figure place.
10. the signal generating method of high-definition video signal generator according to claim 3, is characterized in that:
The parameter that described user arranges comprises video resolution, video color space, high-definition digital content protecting agreement, video signal type, video color depth bit wide, audio sampling frequency or audio sample bit wide.
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| CN104822040A (en) * | 2015-04-28 | 2015-08-05 | 深圳市载德光电技术开发有限公司 | Multi-format video sequence generation system based on FPGA and method thereof |
| CN104822040B (en) * | 2015-04-28 | 2018-06-19 | 深圳市载德光电技术开发有限公司 | A kind of multiple format video sequence generation system and method based on FPGA |
| CN105403381A (en) * | 2015-11-26 | 2016-03-16 | 洛阳瑞光影视光电技术有限公司 | Sdi signal generator |
| CN105403381B (en) * | 2015-11-26 | 2018-09-18 | 洛阳瑞光影视光电技术有限公司 | Sdi signal generator |
| CN109218812A (en) * | 2018-08-30 | 2019-01-15 | 广州帝特电子科技有限公司 | One kind extending equipment based on HDMI high-definition signal IP network |
| CN109218812B (en) * | 2018-08-30 | 2019-12-17 | 广州帝特电子科技有限公司 | based on HDMI high definition signal IP network extension equipment |
| CN109618074A (en) * | 2018-12-23 | 2019-04-12 | 中国航空工业集团公司洛阳电光设备研究所 | A kind of Robust Design method to nonstandard input vesa timing |
| CN113014915A (en) * | 2021-02-19 | 2021-06-22 | 青岛智动精工电子有限公司 | Signal source equipment and signal generation method of signal source equipment |
| CN113014915B (en) * | 2021-02-19 | 2023-02-24 | 青岛智动精工电子有限公司 | Signal source equipment and signal generation method thereof |
| CN114245029A (en) * | 2021-12-20 | 2022-03-25 | 北京镁伽科技有限公司 | FPGA-based data stream processing method and device and PG equipment |
| CN114245029B (en) * | 2021-12-20 | 2023-08-01 | 北京镁伽科技有限公司 | FPGA-based data stream processing method and device and PG equipment |
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