CN113014915B - Signal source equipment and signal generation method thereof - Google Patents
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Abstract
The application provides a signal source device and a signal generating method thereof, wherein the signal source device comprises: an interaction component configured to interact with an outside of the device and to obtain a selection instruction indicating a selected signal according to the interaction; the upper computer is configured to generate a control instruction for controlling the format of each selected signal according to the selection instruction; a signal generator configured to generate and output the selected signals in a corresponding format in parallel according to the control instruction. According to the signal source equipment integration method and device, the integration level of the signal source equipment can be improved.
Description
Technical Field
The present application relates to the field of communication devices, and in particular, to a signal source device and a signal generating method of the signal source device.
Background
In the field of communication devices, it is often necessary for a signal source device to generate and output a signal for testing or other applications depending on the output signal. In the related art, the integration level of the internal components of the signal source device is low, which results in a larger volume of the signal source device and fewer functions.
Disclosure of Invention
An object of the present application is to provide a signal source device and a signal generating method of the signal source device, which can improve the integration level of the signal source device.
According to an aspect of an embodiment of the present application, a signal source device is disclosed, the signal source device including:
an interaction component configured to interact with an outside of the device and to obtain a selection instruction indicating a selected signal according to the interaction;
the upper computer is configured to generate a control instruction for controlling the format of each selected signal according to the selection instruction;
a signal generator configured to generate and output each of the selected signals in a corresponding format in parallel according to the control instruction.
In an embodiment, the signal generator comprises: and (3) an FPGA chip.
In one embodiment, the interaction component comprises:
a display configured to display signal options for selection;
and the key is configured to transmit the selection instruction to the upper computer by triggering the signal option.
In an embodiment, the selected signal includes a plurality of analog video signals, and the signal generator is configured to generate and output the analog video signals in parallel according to the control instruction.
In one embodiment, the analog video signal comprises: VGA signal, CVBS signal, YCRCB component signal, DVI signal.
In an embodiment, the selected signal includes a plurality of HDMI signals, and the signal generator is configured to generate and output each of the HDMI signals in parallel according to the control instruction.
In an embodiment, the signal generator is configured to:
the method comprises the steps of generating a plurality of parallel digital signals corresponding to a target HDMI signal based on an internal preset phase-locked loop, converting the parallel digital signals into serial TMDS signals, and obtaining the target HDMI signal composed of the TMDS signals.
In an embodiment, the signal generator is configured to:
acquiring a reference clock signal;
inputting the reference clock signal into the phase-locked loop to obtain a pixel clock signal output by the phase-locked loop;
the parallel digital signals are generated based on the pixel clock signal and converted to a serial TMDS signal.
In an embodiment, the signal generator is configured to:
acquiring a target pixel clock frequency indicated by the control instruction;
screening out a first pixel clock signal matched with the target pixel clock frequency from the pixel clock signals;
and generating the parallel digital signals by taking the first pixel clock signal as a synchronization standard, and converting the parallel digital signals into serial TMDS signals.
In an embodiment, the signal generator is configured to:
screening out a second pixel clock signal other than the first pixel clock signal from the pixel clock signals before converting the parallel digital signals into a serial TMDS signal;
and respectively carrying out buffering processing, coding processing and output distribution processing on the parallel digital signals by taking the second pixel clock signal as a synchronous standard.
In an embodiment, the selected signal comprises a plurality of audio signals.
According to an aspect of an embodiment of the present application, a signal generating method of a signal source device is disclosed, the method including:
acquiring a selection instruction indicating a selected signal in response to an interaction with the outside of the device;
generating a control instruction for controlling the format of each selected signal according to the selection instruction;
and generating and outputting each selected signal with a corresponding format in parallel according to the control instruction by a signal generator arranged in the equipment.
The signal source equipment provided by the embodiment of the application realizes the parallel output of multi-format signals by arranging the signal generator with high integration level, reduces the volume of the signal source equipment, ensures the diversity of output signals and improves the integration level of the signal source equipment.
Other features and advantages of the present application will be apparent from the following detailed description, or may be learned by practice of the application.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
The above and other objects, features and advantages of the present application will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.
Fig. 1 shows a schematic structural diagram of a signal source device according to some embodiments.
Fig. 2 illustrates a schematic diagram of a signal generator generating and outputting an HDMI signal, according to some embodiments.
Fig. 3 shows a detailed schematic diagram of a signal generator generating and outputting an HDMI signal according to some embodiments.
Detailed Description
To make the purpose and embodiments of the present application clearer, the following will clearly and completely describe the exemplary embodiments of the present application with reference to the attached drawings in the exemplary embodiments of the present application, and it is obvious that the described exemplary embodiments are only a part of the embodiments of the present application, and not all of the embodiments.
It should be noted that the brief descriptions of the terms in the present application are only for the convenience of understanding the embodiments described below, and are not intended to limit the embodiments of the present application. These terms should be understood in their ordinary and customary meaning unless otherwise indicated.
The terms "first," "second," "third," and the like in the description and claims of this application and in the foregoing drawings are used for distinguishing between similar or analogous objects or entities and are not necessarily intended to limit the order or sequence in which they are presented unless otherwise indicated. It is to be understood that the terms so used are interchangeable under appropriate circumstances.
The terms "comprises" and "comprising," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a product or apparatus that comprises a list of elements is not necessarily limited to all elements expressly listed, but may include other elements not expressly listed or inherent to such product or apparatus.
The term "module" refers to any known or later developed hardware, software, firmware, artificial intelligence, fuzzy logic, or combination of hardware and/or software code that is capable of performing the functionality associated with that element.
The application proposes a signal source device, primarily for generating a test signal for testing a receiving device by means of the generated test signal. For example: the signal source equipment generates an audio test signal, and then transmits the audio test signal to a music player to be tested so as to test an audio module of the music player; or the signal source equipment generates a video test signal, and then transmits the video test signal to the television to be tested so as to test the video module of the television.
The signal source device proposed by the present application comprises: the device comprises an interaction component, an upper computer and a signal generator.
The interaction component is used for interacting with the outside of the signal source equipment and acquiring a selection instruction according to the interaction. The selection instruction is used to indicate the selected signal that the signal source device needs to generate. The number of the selected signals may be one, or greater than or equal to two.
And the interactive component transmits the acquired selection instruction to the upper computer, and the upper computer generates a control instruction according to the selection instruction. The control instructions are used to control the format of the selected signal. For example: the system of the selected signal, the resolution of the selected signal.
And the upper computer transmits the generated control instruction to the signal generator, and the signal generator generates and outputs each selected signal in a corresponding format in parallel according to the control instruction.
The number of signal generators is not limited, and may be one or more.
In one embodiment, an FPGA (Field Programmable Gate Array) chip is used as a signal generator for generating and outputting signals. Specifically, an FPGA chip is arranged in the signal source device and is programmed in advance, so that the FPGA chip can generate and output each selected signal in a corresponding format in parallel through a logic circuit of the FPGA chip according to a received control instruction.
The embodiment has the advantages that the FPGA chip is used as the signal generator, the arrangement of a data memory (such as RAM) can be omitted, the size of the signal source equipment is reduced, and the integration level of the signal source equipment is improved.
In one embodiment, the upper computer uses a chip of an ARM system.
In one embodiment, the interaction component comprises: a display and keys.
The display is primarily used to show the signal options available for selection during the interaction. The signal options generally include a category option of the signal, a format option of the signal, and a resolution option of the signal.
The key is mainly used for monitoring the triggering action of the signal option in the interaction process. The signal corresponding to the signal option triggered by the triggered action is the selected signal. And responding to the detected triggering action, triggering the corresponding signal option by the key, and transmitting a selection instruction for indicating the selected signal to the upper computer. The selection instruction mainly describes the signal option corresponding to the selected signal.
In one embodiment, the keys in the interactive component are inductive keys. The display is not only used for displaying the selectable signal options, but also used for monitoring the trigger action of the signal options and transmitting the selection instruction to the upper computer through the trigger signal selection.
In particular, the display may be configured as a touch sensitive display, which monitors the triggering of the signal option by monitoring a change in pressure or a change in capacitance.
In one embodiment, the signal generator is internally provided with an analog video signal output module for generating and outputting a plurality of paths of analog video signals in parallel. When the selected signal simultaneously includes a plurality of analog video signals, the upper computer transmits a control instruction indicating a format of each selected signal to the signal generator, so that the signal generator generates and outputs each selected analog video signal in parallel according to the control instruction.
In one embodiment, the plurality of analog video signals includes: a VGA (Video Graphics Array) signal, a Composite Video Blanking and Sync (Composite Video Blanking and Sync) signal, a YCRCB component signal, and a DVI (Digital Visual Interface) signal.
In an embodiment, the signal generator is internally provided with a digital video signal output module for generating and outputting multiple HDMI (High Definition Multimedia Interface) signals in parallel. When the selected signal includes a plurality of HDMI signals at the same time, the upper computer transmits a control instruction indicating the format of each selected signal to the signal generator, so that the signal generator generates and outputs each selected HDMI signal in parallel according to the control instruction.
In one embodiment, for a target HDMI signal to be generated, a signal generator generates a plurality of parallel digital signals corresponding to the target HDMI signal based on an internal preset phase-locked loop, wherein the plurality of parallel digital signals generally include video data, control data and auxiliary data which are respectively parallel; the signal generator performs parallel-to-serial conversion based on the phase-locked loop, and converts the plurality of parallel digital signals into a serial TMDS (Transition-modulated differential signaling) signal; and combining the generated TMDS signals into the target HDMI signal and outputting the target HDMI signal.
Fig. 1 shows a schematic structural diagram of a signal source device according to an embodiment of the present application.
Referring to fig. 1, in this embodiment, the signal source device mainly includes: the device comprises an upper computer, a signal generator adopting an FPGA chip, a display, a key, a crystal oscillator and a power supply.
The crystal oscillator is used for providing clock signals required by the device to work. The power supply is used for supplying electric energy required by the operation to the equipment.
The display displays various selectable signal options under the control of the upper computer.
The key is used for the external equipment or an external user to trigger the signal options displayed by the display. And responding to the detection of the trigger action by the key, and transmitting a selection instruction for indicating the selected signal to the upper computer by the key. Specifically, four keys distributed at four positions, up, down, left, and right, may be configured to monitor an upward selected trigger action, a downward selected trigger action, a leftward selected trigger action, and a rightward selected trigger action, respectively.
And after receiving the selection instruction, the upper computer generates a control instruction for indicating the detailed format of the selected signal and transmits the control instruction to the preprogrammed FPGA chip.
The FPGA chip can independently output one video signal under the instruction of the control instruction, and can also simultaneously output a plurality of video signals in parallel. The output signal includes two portions: output of analog video signals, output of digital video signals.
Wherein, the output of the analog video signal: according to the format indicated by the control instruction, the FPGA chip sends a plurality of preliminarily generated parallel signals to a circuit of the analog video signal output module; under the action of the circuit of the analog video signal output module, sending the plurality of parallel analog video signals to the corresponding analog-to-digital conversion modules; after the processing of the analog-to-digital conversion module, the corresponding analog video signal is obtained and is output through the corresponding analog video signal interface. Specifically, a DA conversion chip may be provided as a main component of the analog-to-digital conversion module.
Output of digital video signal: according to the format indicated by the control instruction, the FPGA chip sends a plurality of preliminarily generated parallel digital signals to a circuit of a digital video signal output module; and obtaining a corresponding HDMI signal under the action of the circuit of the digital video signal output module, and outputting the signal through a corresponding HDMI interface.
The circuit of the digital video signal output module converts a plurality of parallel digital signals into serial TMDS signals in the FPGA chip. The additional arrangement of a parallel-to-serial chip for generating the HDMI signal is avoided.
It should be noted that the embodiment is only an example and should not limit the function and the application scope of the present application.
In one embodiment, for a plurality of parallel digital signals corresponding to the target HDMI signal, the signal generator controls generation of the plurality of parallel digital signals by the pixel clock signal generated by the phase-locked loop, and converts the plurality of parallel digital signals into a plurality of serial TMDS signals.
Specifically, the signal generator acquires a reference clock signal. The reference clock signal is mainly used as a reference of a clock according to which each signal in the signal source equipment is generated and transmitted. A crystal oscillator may be provided at the signal source device to generate the reference clock signal.
And the signal generator inputs the acquired reference clock signal into a preset phase-locked loop and drives the phase-locked loop to output a pixel clock signal according to the circuit structure of the phase-locked loop. Further, the signal generator generates parallel digital signals from the pixel clock signal output from the phase locked loop, and converts the parallel digital signals into a serial TMDS signal.
In one embodiment, the pixel clock signal generated by the phase-locked loop in the signal generator comprises a first pixel clock signal for generating the target HDMI signal. In order to generate a target HDMI signal, the signal generator acquires a target pixel clock frequency from the received control instruction, and then screens out a first pixel clock signal matched with the target pixel clock frequency. And generating parallel digital signals by taking the first pixel clock signal as a synchronization standard, and converting the parallel digital signals into serial TMDS signals.
In an embodiment, the pixel clock signal generated by the phase locked loop in the signal generator comprises a second pixel clock signal in addition to the first pixel clock signal. The second pixel clock signal is used to process the parallel digital signals before parallel-to-serial conversion. Specifically, the signal generator takes a second pixel clock signal as a synchronous standard to buffer the parallel digital signals; then, a second pixel clock signal is taken as a synchronous standard, and the parallel digital signals are coded; and then taking a second pixel clock signal as a synchronous standard to perform output distribution processing on the parallel digital signals.
In one embodiment, the signal generator is internally provided with an audio signal output module for generating and outputting multiple audio signals in parallel.
Fig. 2 shows a schematic diagram of a signal generator according to an embodiment of the present application generating and outputting an HDMI signal.
Referring to fig. 2, in this embodiment, under the instruction of the control instruction, the signal generator of the FPGA chip is used to generate corresponding parallel digital signals for the HDMI signals with different resolutions (e.g., an HDMI signal with a 1080 × 1920 resolution, an HDMI signal with a 1366 × 768 resolution, an HDMI signal with a 1280 × 768 resolution, and an HDMI signal with a 1280 × 720 resolution), respectively, and further convert the corresponding parallel digital signals into serial TMDS signals and output the serial TMDS signals from the corresponding HDMI interfaces.
For example: for an HDMI signal with a 1080 × 1920 resolution, the FPGA chip generates a parallel digital signal with the resolution, and further converts the parallel digital signal with the resolution into a serial TMDS signal and outputs the serial TMDS signal to the HDMI interface with the resolution, so that the signal source device generates and outputs an HDMI signal with the 1080 × 1920 resolution.
It should be noted that the embodiment is only an exemplary illustration, and should not limit the function and the scope of the application.
Fig. 3 shows a detailed schematic diagram of the signal generator generating and outputting an HDMI signal according to an embodiment of the present application.
Referring to fig. 3, in this embodiment, a phase-locked loop in a signal generator of an FPGA chip is used to output a plurality of pixel clock signals at the input of a reference clock signal.
After the plurality of pixel clock signals output by the phase-locked loop are selected by the frequency selector, a first pixel clock signal used for generating a target HDMI signal is screened out. The first pixel clock signal is processed into a differential TMDS clock signal after being converted from a single-ended signal to a double-ended differential signal.
The second pixel clock signal except the first pixel clock signal is sent to the TMDS forming module to provide clock signals for the buffer module, the encoding module, the data output distributing module, the parallel-to-serial conversion module and the like.
The data transmission process of the TMDS signal is divided into three time periods of a video data transmission period, a data island transmission period and a control data transmission period.
The video data transmission period is to display a video signal on a display for transmitting the signal during a line forward or a field forward period.
Video data transmission period: video data of channels of TMDS0, TMDS1 and TMDS2 are sent to an encoding module for encoding processing after passing through a buffer module, and then the video data after encoding processing is sent to a data output distribution module to be selected and output.
The control data transmission period and the data island transmission period are for transmitting signals during a blanking period of an image. The control data transmission period is used to transmit control data of the video so that the receiving end extracts the synchronization signal. The data island transmission period is used to transmit auxiliary data. Wherein the auxiliary data comprises audio data.
Control data transmission period: the control data of the channels TMDS0, TMDS1 and TMDS2 are sent to the encoding module for encoding after passing through the buffer module, and then the encoded control data are sent to the data output distribution module to be selected and output.
Data island transmission period: the auxiliary data of the channels of TMDS0, TMDS1 and TMDS2 are buffered by the buffer module and then sent to the encoding module for encoding, and the encoded auxiliary data is sent to the data output distribution module for being selected and output.
In each clock cycle of the TMDS clock signal, the video data after encoding processing, the control data after encoding processing, and the auxiliary data after encoding processing, which are parallel on the respective channels, are converted into a serial TMDS signal, thereby obtaining three TMDS signals, i.e., TMDS0, TMDS1, and TMDS 2. Furthermore, the three TMDS signals and the TMDS clock signal are output to the HDMI interface together, so that the receiving device displays the corresponding multimedia.
In some embodiments, as shown, the video data transmission period: the green primary color G data on a TMDS0 channel, the blue primary color B data on a TMDS1 channel and the red primary color R data on a TMDS2 channel are sent to an 8B/10B coding module after passing through a buffer module, 8B/10B coding processing is carried out under the action of a clock signal output by a phase-locked loop, 8-bit data is converted into 10-bit data, and then the 10-bit data is sent to a data output distribution module to wait for being selected and output.
Control data transmission period: line HS and field VS synchronous signals on a TMDS0 channel, CTL0 and CTL1 synchronous signals on a TMDS1 channel and CTL2 and CTL3 synchronous signals on a TMDS2 channel are sent into a 2B/10B coding module after passing through respective buffer modules, 2B/10B coding processing is carried out under the action of a clock signal output by a phase-locked loop, 2-bit data is converted into 10-bit data, and then the 10-bit data is sent to a data output distribution module to wait for being selected and output.
Data island transmission period: auxiliary data on channels of TMDS0, TMDS1 and TMDS2 are sent to a 4B/10B coding module after passing through respective buffer modules, 4B/10B coding processing is carried out under the action of a clock signal output by a phase-locked loop, 4-bit data is converted into 10-bit data, and then the 10-bit data is sent to a data output distribution module to wait for being selected and output.
The 10-bit data waiting to be selected and output in the video data transmission period is recorded as 10-bit video data, the 10-bit data waiting to be selected and output in the control data transmission period is recorded as 10-bit control data, and the 10-bit data waiting to be selected and output in the data island is recorded as 10-bit auxiliary data. Then the 10-bit video data, the 10-bit control data and the 10-bit auxiliary data in parallel on the respective channels are converted into a serial TMDS signal in each clock cycle of the TMDS clock signal, thereby obtaining three TMDS signals TMDS0, TMDS1 and TMDS 2.
It should be noted that the embodiment is only an exemplary illustration, and should not limit the function and the scope of the application.
The application also provides a signal generation method of the signal source equipment, which is mainly applied to the signal source equipment provided by the application. By the method, the signal source equipment is controlled to respond to interaction with the outside of the equipment to acquire a selection instruction for indicating a selected signal; generating a control instruction for controlling the format of each selected signal according to the selection instruction; and then, generating and outputting each selected signal with a corresponding format in parallel according to the control instruction through a signal generator arranged in the equipment.
The signal generation method provided by the application provides flexible and rich signal generation control capability for the outside of the device, and allows the outside of the device to adaptively control the signal source device to simultaneously generate and output a plurality of signals in parallel. And because the generation and the output of the signal are realized by the signal generator with high integration, the phenomenon that the volume of the signal source equipment is increased due to the arrangement of a plurality of signal generators in the signal source equipment is avoided. The method and the device provide flexible and rich signal generation control capability and control the volume of the signal source equipment, thereby improving the integration level of the signal source equipment. The detailed components of the signal source device are not described herein again.
Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.
Claims (5)
1. A signal source device, characterized in that the signal source device comprises:
an interaction component configured to interact with an exterior of the device and to acquire a selection instruction indicating a selected signal in response to the interaction;
the upper computer is configured to generate a control instruction for controlling the format of each selected signal according to the selection instruction, wherein the selected signals comprise a plurality of analog video signals and a plurality of HDMI signals;
an FPGA chip configured to generate and output each of the analog video signals and each of the HDMI signals in parallel according to the control instruction;
when each HDMI signal is generated and output, the FPGA chip is configured to generate corresponding parallel digital signals for a target HDMI signal in the selected signal according to the control instruction; inputting a reference clock signal into a preset phase-locked loop to generate a first pixel clock signal and a second pixel clock signal, wherein the first pixel clock signal is matched with the target pixel clock frequency indicated by the control instruction; carrying out single-end signal to double-end differential processing on the first pixel clock signal to obtain a differential TMDS clock signal; processing the parallel digital signals by taking the second pixel clock signal as a synchronization standard to obtain each channel of TMDS signals corresponding to the parallel digital signals; and outputting the TMDS signals and the TMDS clock signals to an HDMI to obtain the target HDMI signal.
2. The signal source device of claim 1, wherein the interaction component comprises:
a display configured to display signal options for selection;
the key is configured to transmit the selection instruction to the upper computer by triggering the signal option.
3. The signal source device of claim 1, wherein the FPGA chip is configured to:
inputting the reference clock signal into the phase-locked loop to obtain a pixel clock signal output by the phase-locked loop;
screening out a first pixel clock signal matched with the target pixel clock frequency from the pixel clock signals;
and screening out second pixel clock signals except the first pixel clock signal from the pixel clock signals.
4. The signal source device of claim 1, wherein the FPGA chip is configured to:
and respectively taking the second pixel clock signal as a synchronization standard to perform buffering processing, coding processing and output distribution processing on the parallel digital signals.
5. A signal generation method of a signal source device, the method comprising:
acquiring a selection instruction for indicating a selected signal in response to interaction with the outside of the device, wherein the selected signal comprises a plurality of analog video signals and a plurality of HDMI signals;
generating a control instruction for controlling the format of each selected signal according to the selection instruction;
through an FPGA chip arranged in the equipment, generating and outputting each analog video signal and each HDMI signal in parallel according to the control instruction; when each HDMI signal is generated and output, generating corresponding parallel digital signals for a target HDMI signal in the selected signals through the FPGA chip according to the control instruction; inputting a reference clock signal into a preset phase-locked loop to generate a first pixel clock signal and a second pixel clock signal, wherein the first pixel clock signal is matched with the target pixel clock frequency indicated by the control instruction; carrying out single-ended signal to double-ended differential processing on the first pixel clock signal to obtain a differential TMDS clock signal; processing the parallel digital signals by taking the second pixel clock signal as a synchronous standard to obtain all channels of TMDS signals corresponding to the parallel digital signals; and outputting the TMDS signals and the TMDS clock signals to an HDMI to obtain the target HDMI signal.
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| US8274296B2 (en) * | 2009-11-11 | 2012-09-25 | Advantest Corporation | Test apparatus and electronic device that tests a device under test |
| CN111314576B (en) * | 2019-11-28 | 2023-01-13 | 苏州长风航空电子有限公司 | Analog video processing method |
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| CN201878274U (en) * | 2010-11-24 | 2011-06-22 | 北京格非科技发展有限公司 | Multi-format converter |
| CN103139594A (en) * | 2011-11-29 | 2013-06-05 | 上海全维光纤网络系统有限公司 | Generating method of multi-format video testing signal |
| CN103873802A (en) * | 2012-12-18 | 2014-06-18 | 深圳市广平正科技有限责任公司 | High-definition video signal generator and signal generating method thereof |
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