CN110087006B - Display control system, method and device - Google Patents
Display control system, method and device Download PDFInfo
- Publication number
- CN110087006B CN110087006B CN201910413427.7A CN201910413427A CN110087006B CN 110087006 B CN110087006 B CN 110087006B CN 201910413427 A CN201910413427 A CN 201910413427A CN 110087006 B CN110087006 B CN 110087006B
- Authority
- CN
- China
- Prior art keywords
- image
- channel
- programmable gate
- gate array
- field programmable
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/431—Generation of visual interfaces for content selection or interaction; Content or additional data rendering
- H04N21/4312—Generation of visual interfaces for content selection or interaction; Content or additional data rendering involving specific graphical features, e.g. screen layout, special fonts or colors, blinking icons, highlights or animations
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/438—Interfacing the downstream path of the transmission network originating from a server, e.g. retrieving MPEG packets from an IP network
- H04N21/4383—Accessing a communication channel
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/47—End-user applications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
- H04N5/50—Tuning indicators; Automatic tuning control
Abstract
The invention provides a display control system, a method and a device, wherein the system comprises a system processing chip and a field programmable gate array processor which are connected, the field programmable gate array processor is connected with a display panel, and the system processing chip is configured as follows: when a control interface calling instruction is monitored and a current signal access channel is in a first channel, acquiring an image input by external equipment of the field programmable gate array processor, and switching the current signal access channel into a second channel; the field programmable gate array processor is configured to: and when the system processing chip monitors a control interface calling instruction and the current signal access channel is in the first channel, transmitting the current input image of the external equipment to the system processing chip. The invention adopts the mode of combining the SoC and the FPGA processor, and can ensure that the display panel simultaneously displays the control interface when playing the image input by the external equipment connected with the FPGA processor.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a display control system, method, and apparatus.
Background
With the rise of artificial intelligence, Field-Programmable Gate arrays (FPGAs) are increasingly applied to the Field of algorithm hardware acceleration, and especially for processing pictures, because of the adoption of a parallel data processing mode of the FPGAs, picture processing through the FPGAs has more obvious advantages, the FPGAs can be applied to the technical Field of display.
However, the FPGA cannot implement a complex control menu, and the interaction capability with the user is weak, for example, when the FPGA is connected to an external signal source for playing an image, the FPGA cannot output the control menu on the played image for displaying.
Disclosure of Invention
The technical scheme of the invention aims to provide a display control system, a display control method and a display control device, which are used for solving the problem that a display control menu cannot be output on a played image when the image is played through an FPGA (field programmable gate array) in the prior art.
The invention discloses a display control system, which comprises a system processing chip and a field programmable gate array processor which are connected, wherein the field programmable gate array processor is connected with a display panel, and the display control system comprises:
the system processing chip is configured to: when a control interface calling instruction is monitored and a current signal access channel is in a first channel, acquiring an image input by external equipment of the field programmable gate array processor, and switching the current signal access channel into a second channel;
the field programmable gate array processor is configured to: when the system processing chip monitors a control interface calling instruction and a current signal access channel is in a first channel, transmitting a current input image of the external equipment to the system processing chip;
when the current signal access channel is in a first channel, the image source of the display panel is the external device; and when the current signal access channel is in the second channel, the image source of the display panel is the system processing chip.
Further, the system processing chip is further configured to: when the current signal access channel is in a second channel, transmitting an image to be displayed to the field programmable gate array processor;
the field programmable gate array processor is further configured to: and outputting the image to be displayed to the display panel for display.
Further, the system processing chip is further configured to: and after monitoring a control interface calling instruction, switching a current signal access channel from a first channel to a second channel, acquiring an image input by the external equipment of the field programmable gate array processor, and generating the image to be displayed according to the image input by the external equipment of the field programmable gate array processor and the control interface called by the control interface calling instruction.
Further, when transmitting an image to be displayed to the field programmable gate array processor, the system processing chip outputs the image to be displayed with a first resolution to the field programmable gate array processor;
when the field programmable gate array processor outputs the image to be displayed to the display panel for display, the field programmable gate array processor converts the image to be displayed with a first resolution into the image to be displayed with a second resolution and outputs the image to be displayed to the display panel for display;
the second resolution is greater than the first resolution.
Further, the second resolution is 2 times the first resolution.
Further, when the system processing chip generates the image to be displayed according to the image input by the external device of the field programmable gate array processor and the control interface called by the control interface calling instruction, the system processing chip is specifically configured to:
and taking the image transmitted by the field programmable gate array processor and input by an external device as a background, and taking the control interface called by the control interface calling instruction as a superposed picture on the background to generate the image to be displayed.
Further, the field programmable gate array processor is further configured to: when the system processing chip does not monitor a control interface calling instruction and the current signal access channel is in the first channel, the current input image of the external equipment is directly transmitted to the display panel for display.
Further, the system processing chip is further configured to:
and when the current signal access channel is in the second channel, if a control interface calling instruction is monitored, generating the image to be displayed according to the control interface called by the control interface calling instruction.
Further, the system processing chip is further configured to:
after a control interface is displayed on a display panel, if a switching instruction of a signal access channel is monitored within a preset time, responding to the switching instruction to switch the signal access channel;
after the display panel displays the control interface, a switching instruction of the signal access channel is not monitored after a preset time length, and the current signal access channel before the control interface calling instruction is received is a first channel, and the current signal access channel is switched to the first channel.
Further, the system processing chip is further configured to: when a control interface calling instruction is monitored and the current signal access channel is in the first channel, outputting a data transmission instruction to the field programmable gate array processor;
the field programmable gate array is further configured to: and when the current signal access channel is in the first channel, responding to the data transmission instruction, and transmitting the current input image of the external equipment to the system processing chip.
Further, the system processing chip sends the data transmission instruction to the field programmable gate array through a first interface, and receives the image output by the field programmable gate array through a second interface.
The invention also discloses a display control method, which is applied to a system processing chip, wherein the system processing chip is connected with a field programmable gate array processor, and the field programmable gate array processor is connected with a display panel, and the display control method comprises the following steps:
when a control interface calling instruction is monitored and a current signal access channel is in a first channel, acquiring an image input by external equipment of the field programmable gate array processor, and switching the current signal access channel into a second channel;
when the current signal access channel is in a first channel, the image source of the display panel is an external device connected with the field programmable gate array processor; and when the current signal access channel is in the second channel, the image source of the display panel is the system processing chip.
Further, the method further comprises;
and when the current signal access channel is in a second channel, transmitting an image to be displayed to the field programmable gate array processor, so that the field programmable gate array processor outputs the image to be displayed to the display panel for display.
Further, after monitoring a control interface call instruction, switching a current signal access channel from a first channel to a second channel, and acquiring an image input by an external device of the field programmable gate array processor, the method further comprises:
and generating the image to be displayed according to the image input by the external equipment of the field programmable gate array processor and the control interface called by the control interface calling instruction.
Further, transmitting an image to be displayed to the field programmable gate array processor, comprising:
outputting the image to be displayed with a first resolution to the field programmable gate array processor;
when the to-be-displayed image is output to the display panel for display, the field programmable gate array processor converts the to-be-displayed image with a first resolution into the to-be-displayed image with a second resolution and outputs the to-be-displayed image with the second resolution to the display panel for display;
the second resolution is greater than the first resolution.
Further, the method further comprises:
and when the current signal access channel is in the second channel, if a control interface calling instruction is monitored, generating the image to be displayed according to the control interface called by the control interface calling instruction.
Further, the method further comprises:
after a control interface is displayed on a display panel, if a switching instruction of a signal access channel is monitored within a preset time, responding to the switching instruction to switch the signal access channel;
after the display panel displays the control interface, a switching instruction of the signal access channel is not monitored after a preset time length, and the current signal access channel before the control interface calling instruction is received is a first channel, and the current signal access channel is switched to the first channel.
The invention also discloses a display control device, which is applied to a system processing chip, wherein the system processing chip is connected with a field programmable gate array processor, the field programmable gate array processor is connected with a display panel, and the display control device comprises:
the processing module is used for acquiring an image input by the field programmable gate array processor from the external equipment when monitoring a control interface calling instruction and a current signal access channel is in a first channel, and switching the current signal access channel into a second channel;
when the current signal access channel is in a first channel, the image source of the display panel is an external device connected with the field programmable gate array processor; and when the current signal access channel is in the second channel, the image source of the display panel is the system processing chip.
The invention also discloses a display control method, which is applied to a display control system comprising a system processing chip and a field programmable gate array processor which are connected, wherein the field programmable gate array processor is connected with a display panel, and the method comprises the following steps:
when monitoring a control interface calling instruction and a current signal access channel is in a first channel, the system processing chip acquires an image input by the field programmable gate array processor through external equipment and switches the current signal access channel into a second channel;
when the system processing chip monitors a control interface calling instruction and a current signal access channel is in a first channel, the field programmable gate array processor transmits an image currently input by external equipment to the system processing chip;
when the current signal access channel is in a first channel, the image source of the display panel is the external device; and when the current signal access channel is in the second channel, the image source of the display panel is the system processing chip.
At least one of the above technical solutions of the specific embodiment of the present invention has the following beneficial effects:
the display control system and the method of the embodiment of the invention adopt a mode of combining the system processing chip SoC and the field programmable gate array FPGA processor, so that the display panel can simultaneously display a control interface when playing the image input by the external equipment connected to the FPGA processor, thereby solving the problem that the display control menu can not be output on the played image when playing the image through the FPGA in the prior art.
Drawings
FIG. 1 is a schematic diagram of a display control system according to the present invention;
FIG. 2 is a schematic diagram illustrating an implementation flow of the display control system according to the embodiment of the present invention;
FIG. 3 is a flowchart illustrating a display control method according to an embodiment of the invention;
fig. 4 is a schematic structural diagram of a display control apparatus according to an embodiment of the present invention.
Detailed Description
In order to make the technical problems, technical solutions and advantages of the present invention more apparent, the following detailed description is given with reference to the accompanying drawings and specific embodiments.
In order to solve the problem that a display control menu cannot be output on a played image when the image is played through an FPGA in the prior art, the display control System in the embodiment of the invention adopts a mode of combining a System on Chip (SoC) and a field programmable gate array FPGA processor, so that a display panel can simultaneously display a control interface when playing the image input by an external device connected to the FPGA processor.
Specifically, fig. 1 is a schematic diagram of an architecture of a display control system according to an embodiment of the present invention. Referring to fig. 1, the display control system according to the embodiment of the present invention includes: a SoC 10 and an FPGA processor 20. The SoC 10 is connected to the FPGA processor 20, the FPGA processor 20 is connected to the display panel 30, and the display image control output of the display panel 30 can be realized by combining the SoC 10 and the FPGA processor 20.
The FPGA processor 20 may be connected to the external device 40, and specifically may be connected to the external device through a High Definition Multimedia Interface (HDMI) input IN port, through which image information input by the external device 40 may be transmitted to the display panel 30 by the FPGA processor 20 for playing.
The FPGA processor 20 is further connected to the SoC 10 through a connection interface, and optionally the SoC 10 is connected to the FPGA processor 20 through an I2C interface and a V-By-One interface, respectively. The SoC 10 may output a control signal to the FPGA processor 20 through the I2C interface, and perform image data transmission with the FPGA processor 20 through the V-By-One interface. In the display control system according to the embodiment of the present invention, the SoC 10 may operate a control system of the display device to monitor a control interface call instruction input by a user.
Further, in the display control system according to the embodiment of the present invention, the signal access channels for the display panel 30 to display the image include two channels, where in the first channel, the image source of the display panel 30 is the external device 40, and the FPGA processor 20 obtains the image to be displayed from the external device 40 and transmits the image to the display panel 30 for display; in the second channel, the image source of the display panel 30 is the SoC 10, and the FPGA processor 20 obtains the image to be displayed from the SoC 10 and transmits the image to the display panel 30 for display.
Specifically, an embodiment of the present invention provides a display control system, which is shown in fig. 1 and includes a system processing chip (SoC 10) and a field programmable gate array processor (FPGA processor) 20 connected to each other, where the FPGA processor 20 is connected to a display panel, where:
the system processing chip is configured to: when a control interface calling instruction is monitored and a current signal access channel is in a first channel, acquiring an image input by external equipment of the field programmable gate array processor, and switching the current signal access channel into a second channel;
the field programmable gate array processor is configured to: when the system processing chip monitors a control interface calling instruction and a current signal access channel is in a first channel, transmitting a current input image of the external equipment to the system processing chip;
when the current signal access channel is in a first channel, the image source of the display panel is the external device; and when the current signal access channel is in the second channel, the image source of the display panel is the system processing chip. The display control system according to the embodiment of the present invention combines the FPGA processor 20 with the SoC 10, and the SoC 10 is utilized to monitor a control interface call instruction input by a user, and when the control interface call instruction is monitored and the current signal access channel is in the first channel, the current signal access channel can be switched to the second channel, and an image input by the external device is obtained from the FPGA processor 20.
Based on the above manner, by switching the current signal access channel to the second channel and acquiring the image input by the external device from the FPGA processor 20, and by using the control command processing function and the picture operation processing function of the SoC 10, the SoC 10 can combine the image input by the external device with the control interface called by the control interface calling instruction to generate an image to be displayed, and the image to be displayed is output by the FPGA processor 20 to the display panel 30 for display.
Therefore, the SoC 10 outputs to the FPGA processor 20, and includes the image to be displayed currently on the external device 40 and the control interface called by the control interface calling instruction, so that the display panel 30 displays the control interface when playing the image input by the external device 40 connected to the FPGA processor 20, and the problem that the display control menu cannot be output on the played image when playing the image through the FPGA in the prior art can be solved.
In addition, when the SoC 10 generates the image to be displayed according to the image input by the external device by the FPGA processor 20 and the control interface called by the control interface calling instruction, the configuration is specifically as follows:
and taking the image input by the external equipment and transmitted by the FPGA processor 20 as a background, and taking the control interface called by the control interface calling instruction as a superposed picture on the background to generate the image to be displayed.
For example, the control interface called by the control interface calling instruction may include switching signal channels and setting Display parameters by a user through a menu of On-Screen Display (OSD).
The SoC 10 generates an image to be displayed by using the image output by the FPGA processor 20 as a background and using the control interface called by the control interface calling instruction as a superimposed picture on the background. Specifically, those skilled in the art should understand how to process an image by using one image as a background and superimposing another image on the background, and the image processing technique is not a research focus of the present invention and will not be described in detail herein.
Optionally, in this embodiment of the present invention, the SoC 10 is further configured to:
when a control interface calling instruction is monitored and the current signal access channel is in the first channel, outputting a data transmission instruction to the field programmable gate array processor;
the FPGA processor 20 is further configured to: and when the current signal access channel is in the first channel, responding to the data transmission instruction, and transmitting the current input image of the external equipment to the system processing chip.
Optionally, the SoC 10 sends a data transmission instruction to the FPGA processor 20 through the first interface, and receives an image output by the FPGA processor 20 through the second interface.
Specifically, the SoC 10 may output a data transfer instruction to the FPGA processor 20 through the I2C interface; the SoC 10 may receive an image output By the FPGA processor 20 and input By an external device through a V-By-One interface; the SoC 10 may also transmit the image to be displayed to the FPGA processor 20 through the V-By-One interface.
Optionally, in the display control system according to the embodiment of the present invention, the SoC 10 is further configured to: when the current signal access channel is in the second channel, transmitting the image to be displayed to the FPGA processor 20;
the FPGA processor 20 is further configured to: and outputting the image to be displayed to the display panel for display.
When the current signal access channel is in the second channel, the image source of the display panel 30 is the SoC 10, the SoC 10 transmits the image to be displayed to the FPGA processor 20, and the image to be displayed is transmitted to the display panel 30 through the FPGA processor 20 for display.
In addition, the SoC 10 is further configured to: and when a control interface calling instruction is monitored, switching the current signal access channel from the first channel to the second channel, acquiring an image input by the external equipment of the FPGA processor 20, and generating an image to be displayed according to the image input by the external equipment 40 of the FPGA processor 20 and the control interface called by the control interface calling instruction.
Further, after the image to be displayed is generated, because the current signal access channel is in the second channel, the SoC 10 transmits the image to be displayed to the FPGA processor 20, and transmits the image to be displayed to the display panel 30 through the FPGA processor 20 for display, the image input by the external device 40 and the control interface called by the control interface calling instruction can be simultaneously displayed on the display panel 30.
Optionally, in the display control system according to the embodiment of the present invention, by using a characteristic that the FPGA processor 20 can process an image with a higher resolution than the SoC 10, the image to be displayed, which is transmitted to the FPGA processor 20 by the SoC 10, may be subjected to resolution conversion by the FPGA processor 20, so as to improve the resolution of the image displayed on the display panel 30.
Specifically, the SoC 10 outputs the image to be displayed with a first resolution to the FPGA processor 20 when transmitting the image to be displayed to the field programmable gate array processor;
when outputting the image to be displayed to the display panel 30 for display, the FPGA processor 20 converts the image to be displayed with the first resolution into an image to be displayed with the second resolution, and outputs the image to be displayed to the display panel for display;
wherein the second resolution is greater than the first resolution.
Optionally, the second resolution is 2 times the first resolution.
For example, the first resolution is 4K and the second resolution is 8K.
By adopting the display control system of the embodiment of the invention, the image output by the SoC 10 can be displayed on the display panel 30 in 8K resolution by combining the SoC 10 with the FPGA processor 20.
Further, the display panel 30 is a panel supporting 8K image display.
In addition, when the FPGA processor 20 transmits the image currently input by the external device to the SoC 10, the FPGA processor 20 is further configured to: the image with the second resolution currently input by the external device is converted into the image with the first resolution and then sent to the SoC 10, so that after the SoC 10 obtains the image with the first resolution currently input by the external device, the image to be transmitted is obtained after the image is combined with the control interface called by the control interface calling instruction and then is transmitted to the FPGA processor 20, and after the image with the first resolution is converted into the image to be transmitted with the second resolution by the FPGA processor 20, the image to be transmitted is sent to the display panel 30 to be displayed.
By adopting the display control system of the embodiment of the invention, when the image on the external device 40 is output to the display panel 30, the image with the resolution of 8K can be output to the display panel 30; in addition, the FPGA processor 20 further has a resolution processing function, although the SoC 10 cannot realize 8K image display, and the resolution of the image to be displayed output by the SoC 10 to the FPGA processor 20 is 4K, the FPGA processor 20 can process the image to be transmitted with the resolution of 4K into the image to be transmitted with the resolution of 8K, and then transmit the image to be transmitted to the display panel 30 for display, so that the display panel 30 can display the image to be transmitted with the resolution of 8K.
Optionally, when the image input by the external device 40 has the second resolution (8K), the FPGA processor 20 is further configured to:
the method comprises the steps of processing an image with 8K resolution input on the external device 40 into an image with 4K resolution (first resolution), transmitting the image with 4K resolution to the SoC 10, and transmitting the image to be transmitted to the FPGA processor 20 after the SoC 10 generates the image to be transmitted with 4K resolution by the image with 4K resolution input by the external device and a control interface called by a control interface calling instruction.
Based on the above processing mode, the SoC 10 is combined with the FPGA processor 20, so that the display panel can play the input image of the external device connected to the FPGA processor, and display the control interface, and display the high-resolution image.
Optionally, in the display control system according to the embodiment of the present invention, the FPGA processor 20 is further configured to: when the SoC 10 does not monitor the control interface invoking instruction and the current signal access channel is in the first channel, the currently input image of the external device 40 is directly transmitted to the display panel 30 for display.
Optionally, the image input by the external device 40 has a second resolution (8K), and when the image is in the first channel, the image with the resolution of 8K can be displayed on the display panel 30.
Optionally, in the display control system according to the embodiment of the present invention, the SoC 10 is further configured to:
and when the current signal access channel is in the second channel, if a control interface calling instruction is monitored, generating the image to be displayed according to the control interface called by the control interface calling instruction.
Based on the above manner, if the SoC 10 monitors the control interface call instruction when the current signal access channel is in the second channel, the SoC 10 directly combines the pre-stored image to be output with the control interface called by the control interface call instruction, generates an image to be displayed, and transmits the image to be displayed to the FPGA processor 20, so that the FPGA processor 20 displays the image output by the SoC 10 and the image combined with the control interface. In the embodiment of the present invention, optionally, the image pre-stored on the SoC 10 has a second resolution;
wherein, when the current signal access channel is in the second channel, the SoC 10 is configured to, when outputting the pre-stored image to the FPGA processor 20:
compressing an image to be output to obtain an image with a first resolution;
outputting the image with the first resolution to the FPGA processor 20; wherein, the FPGA processor 20 stretches the image with the first resolution into an image with the second resolution and transmits the image to the display panel 30;
wherein the second resolution is greater than the first resolution.
For example, the second resolution may be 8K, and the first resolution may be 4K.
In the above manner, although the SoC 10 cannot support 8K image display, the SoC 10 may compress the stored image with the resolution of 8K into 4K and transmit the compressed image to the FPGA processor 20, and the FPGA processor 20 stretches the third image with the resolution of 4K into 8K and transmits the stretched image to the display panel 30 for display, thereby implementing image display of 8K image data from the SoC 10 on the 8K display panel.
Therefore, by adopting the display control method of the embodiment of the invention, the display panel can play the input image of the external equipment connected to the FPGA processor, and simultaneously display the control interface, and the signal input channel can be switched from the external equipment connected to the FPGA processor 20 to the storage equipment of the SoC 10, so that the high-resolution display of the image from the SoC on the display panel 30 can be realized.
Optionally, the SoC 10 is further configured to:
after a control interface is displayed on a display panel, if a switching instruction of a signal access channel is monitored within a preset time, responding to the switching instruction to switch the signal access channel;
after the display panel displays the control interface, a switching instruction of the signal access channel is not monitored after a preset time length, and the current signal access channel before the control interface calling instruction is received is a first channel, and the current signal access channel is switched to the first channel.
Specifically, with reference to fig. 1, after the display panel 30 displays the control interface, the SoC 10 monitors a switching instruction of the signal access channel within a preset time period, where the channel switching instruction is used to instruct to perform signal channel switching, and if the channel switching instruction instructs that the signal input channel is switched from the external device connected to the FPGA processor 20 to the storage device of the SoC 10 itself, that is, the first channel is switched to the second channel, according to the channel switching instruction, the SoC 10 outputs the image to be displayed stored in the storage device of the SoC 10 to the FPGA processor 20, so that the FPGA processor 20 transmits the image to be displayed to the display panel 30, and the display panel 30 displays the image output by the SoC 10.
Optionally, according to the switching instruction, the SoC 10 may further send a data transmission stop instruction to the FPGA processor 20, so that the FPGA processor 20 stops sending the image to be currently displayed on the external device 40 to the SoC 10.
If the channel switching instruction indicates that the signal input channel is switched from the storage device of the SoC 10 to the external device connected to the FPGA processor 20, that is, the second channel is switched to the first channel, according to the channel switching instruction, the SoC 10 stops outputting the image to the FPGA processor 20, and the FPGA processor 20 obtains the image input by the external device 40 and directly outputs the image to the display panel 30 for display.
Based on the above, optionally, after the SoC 10 monitors that the control interface calls the instruction, and the current signal access channel is in the first channel, the current signal access channel is switched to the second channel, and the image input by the external device by the FPGA processor 20 is acquired, the display control system according to the embodiment of the present invention is further configured to:
if the control interface calling instruction is not monitored within the preset time, outputting a data transmission stopping instruction to the FPGA processor 20.
Specifically, if no control interface calling instruction is monitored within the preset time, the FPGA processor 20 may stop sending the image to be displayed currently on the external device 40 to the SoC 10 by outputting a data transmission stopping instruction to the FPGA processor 20 according to the data transmission stopping instruction, and further, if the FPGA processor 20 does not continuously receive the image data sent by the SoC 10, the FPGA processor 20 may directly transmit the image to be displayed currently on the external device 40 to the display panel 30 for displaying, so as to switch to directly output the image on the external device to the display panel 30 by the FPGA processor 20.
Based on the above manner, after the control interface is displayed on the display panel, the switching instruction of the signal access channel is not monitored after the preset time, and the current signal access channel before the control interface calling instruction is received is the first channel, and the current signal access channel is switched to the first channel. According to the above, with the display control system according to the embodiment of the present invention, in conjunction with fig. 1, the display control system is applied with the following three operation modes:
a first operating mode: the external device 40 connected with the FPGA processor 20 is used as a signal access channel, and the image data with the resolution of 8K on the external device 40 is directly transmitted to the display panel 30 by the FPGA processor 20 for display (the current signal access channel is in the first channel);
a second working mode: the SoC 10 receives the control interface calling instruction, the external device 40 connected with the FPGA processor 20 serves as a signal access channel, image data on the external device 40 is compressed into 4K by the FPGA processor 20 and then transmitted to the SoC 10, the SoC 10 combines an image transmitted by the FPGA processor 20 with a control interface called by the control interface calling instruction to generate an image to be displayed and then transmits the image to the FPGA processor 20, and the FPGA processor 20 stretches the image to be displayed to 8K and then transmits the image to the display panel 30 for display (the current signal access channel is switched from a first channel to a second channel);
the third working mode is as follows: the SoC 10 uses its own storage device as a signal access channel, the SoC 10 compresses an image with a resolution of 8K stored in its own storage device into an image of 4K, and transmits the image to the FPGA processor 20, and the FPGA processor 20 stretches the image of 4K into 8K, and transmits the image to the display panel 30 for display (the current signal access channel is in the second channel).
In the second working mode, after the SoC 10 receives the control interface calling instruction, although the external device 40 is currently used as the signal access channel for image display of the display panel 30, the SoC 10 acquires the image data sent by the FPGA processor 20, and by using the powerful UI function of the SoC 10, the control interface called by the control interface calling instruction and the image sent by the FPGA processor 20 can be combined and then sent to the display panel 30 by the FPGA processor 20 for display. The processing procedure gives the user the experience of using the external device 40 as a signal access channel, and realizes the effect of image display by combining the image input by the external device with the control interface.
Specifically, with the display control method according to the embodiment of the present invention, referring to fig. 2 and shown in fig. 1, after step S210 begins, the method includes:
s220, the SoC 10 monitors a control interface calling instruction;
s230, determining whether the signal access channel of the current image display of the display panel 30 is the external device 40; if yes, go to step S240; if the determination result is negative, go to step 260; specifically, when the determination result is negative, that is, the signal access channel displayed by the current image is the SoC 10, at this time, the SoC 10 may directly output image data to the FPGA processor 20 according to the control interface called by the control interface calling instruction and the image stored in the current storage device of the FPGA processor, so that the FPGA processor 20 transmits the image data output by the SoC 10 to the display panel 30 for display, that is, executes the third operating mode;
s240, outputting a data transmission instruction to the FPGA processor 20, and acquiring an image to be displayed currently on the external equipment output by the FPGA processor 20;
s250, switching a signal access channel displayed by a current image of the display panel 30 to the SoC 10, generating an image to be displayed by the SoC 10 according to the image output by the FPGA processor 20 and the control interface called by the control interface calling instruction, transmitting the generated image to be displayed to the FPGA processor 20, and outputting the image to be displayed to the display panel 30 by the FPGA processor 20 for display, that is, executing the second working mode;
s260, displaying the control interface called by the control interface calling instruction on the display panel 30;
s270, the SoC 10 determines whether a channel switching instruction input by the user is received, and if the channel switching instruction is received, executes step S280; if the channel switching instruction is not received, step S290 is executed;
s280, switching signal access channels; specifically, if the signal access channel is switched from the external device 40 to the SoC 10 according to the channel switching instruction, the second working mode is switched to the third working mode; if the signal access channel is switched from the SoC 10 to the external device 40 according to the channel switching instruction, switching from the third working mode to the first working mode;
s290, determining whether the signal access channel before receiving the control interface call instruction is the external device 40, if so, executing step S291; if not, i.e. the external device 40 is the SoC 10, then step S292 is executed;
s291, switching the signal access channel into an external device, namely, switching into a first working mode;
and S292, ending.
In the embodiment of the present invention, in the above process, outputting an image to be displayed to an FPGA processor includes:
converting an image to be displayed according to a pre-stored XML file to obtain a register parameter array which can be output to an FPGA processor by the image to be displayed;
and outputting the register parameter array to the FPGA processor.
It will be appreciated that any of the processes described above for transferring image data from the SoC 10 to the FPGA processor 20 may be used.
Specifically, the display parameter settings of the SoC 10 to the FPGA processor 20 are primarily set through the I2c interface. In the invention, the display parameter setting of the SoC 10 to the FPGA processor 20 is stored through an XML file. When the SoC 10 outputs the image data to the FPGA processor 20, the XML file is read, the XML file is parsed, the image data to be output is converted into a register parameter array which can be output to the FPGA processor, and therefore resource and cost are avoided being consumed when the parameters of the register of the FPGA processor 20 are set one by one.
By adopting the display control system of the embodiment of the invention, the SoC 10 transmits a data transmission instruction to the FPGA processor 20, so that the FPGA processor 20 transmits the image to be displayed on the current external device to the SoC 10, and combines the image to be displayed on the external device with the control interface called by the control interface calling instruction by using the picture operation processing function of the SoC 10 to generate the image to be displayed, and outputs the image to enable the display panel 30 to display the image.
By adopting the mode, the generated image to be displayed comprises the image to be displayed on the current external equipment and the control interface called by the control interface calling instruction, and the display panel simultaneously displays the control interface when playing the image input by the external equipment connected to the FPGA processor, so that the problem that the display control menu cannot be output and displayed on the played image when the image is played through the FPGA in the prior art can be solved.
Therefore, by combining the SoC 10 with the FPGA processor 20, the display control system according to the embodiment of the present invention can more efficiently and flexibly control and configure the FPGA, and realize the effect of combining the image input by the external device with the control interface to display the image while realizing high-resolution image display, so as to facilitate the user to set the display parameters and switch the display channels.
An embodiment of the present invention further provides a display control method, which is applied to a system processing chip, wherein the system processing chip is connected to a field programmable gate array processor, the field programmable gate array processor is connected to a display panel, and as shown in fig. 3, the display control method includes:
s310, when a control interface calling instruction is monitored and the current signal access channel is in the first channel, acquiring an image input by the field programmable gate array processor through external equipment, and switching the current signal access channel into the second channel;
when the current signal access channel is in a first channel, the image source of the display panel is an external device connected with the field programmable gate array processor; and when the current signal access channel is in the second channel, the image source of the display panel is the system processing chip.
As shown in fig. 1, in the display control method according to the embodiment of the present invention, by combining the FPGA processor 20 with the SoC 10, when the SoC 10 monitors a control interface calling instruction input by a user and a current signal access channel is in a first channel, the FPGA processor 20 transmits an image to be displayed on a current external device to the SoC 10, so that the SoC 10 can combine the image with the control interface called by the control interface calling instruction to generate an image to be displayed, and output the image to the display panel 30 through the FPGA processor 20, so that the display panel 30 displays the image to be displayed.
In the above manner, since the image to be displayed on the display panel 30 includes the image to be displayed on the current external device and the control interface invoked by the control interface invoking instruction, the display panel can simultaneously display the control interface when playing the image input by the external device connected to the FPGA processor, thereby solving the problem that the display control menu cannot be output on the played image when playing the image through the FPGA in the prior art.
Optionally, the method further comprises;
and when the current signal access channel is in a second channel, transmitting an image to be displayed to the field programmable gate array processor, so that the field programmable gate array processor outputs the image to be displayed to the display panel for display.
Optionally, after monitoring a control interface call instruction, switching a current signal access channel from a first channel to a second channel, and acquiring an image input by an external device of the field programmable gate array processor, the method further includes:
and generating the image to be displayed according to the image input by the external equipment of the field programmable gate array processor and the control interface called by the control interface calling instruction.
Optionally, the display control method, which transmits an image to be displayed to the field programmable gate array processor, includes:
outputting the image to be displayed with a first resolution to the field programmable gate array processor;
when the to-be-displayed image is output to the display panel for display, the field programmable gate array processor converts the to-be-displayed image with a first resolution into the to-be-displayed image with a second resolution and outputs the to-be-displayed image with the second resolution to the display panel for display;
the second resolution is greater than the first resolution.
Optionally, the second resolution is 2 times the first resolution.
For example, the first resolution is 4K and the second resolution is 8K.
By adopting the display control method provided by the embodiment of the invention, the image output by the SoC can be displayed on the display panel at the resolution of 8K by combining the SoC and the FPGA processor.
Optionally, the method further comprises:
and when the current signal access channel is in the second channel, if a control interface calling instruction is monitored, generating the image to be displayed according to the control interface called by the control interface calling instruction.
Optionally, the method further comprises:
after a control interface is displayed on a display panel, if a switching instruction of a signal access channel is monitored within a preset time, responding to the switching instruction to switch the signal access channel;
after the display panel displays the control interface, a switching instruction of the signal access channel is not monitored after a preset time length, and the current signal access channel before the control interface calling instruction is received is a first channel, and the current signal access channel is switched to the first channel.
It should be noted that, when the display control method according to the embodiment of the present invention is applied to a system processing chip, the specific process and detailed description of the display control method executed by the system processing chip may refer to the above detailed description in conjunction with fig. 1, and are not described herein again.
An embodiment of the present invention further provides a display control device, which is applied to a system processing chip, wherein the system processing chip is connected to a field programmable gate array processor, the field programmable gate array processor is connected to a display panel, and as shown in fig. 4, the display control device includes:
the processing module 410 is configured to, when monitoring that a control interface call instruction is received and a current signal access channel is located in a first channel, obtain an image input by an external device by the field programmable gate array processor, and switch the current signal access channel to a second channel;
when the current signal access channel is in a first channel, the image source of the display panel is an external device connected with the field programmable gate array processor; and when the current signal access channel is in the second channel, the image source of the display panel is the system processing chip.
Optionally, the display control apparatus further includes;
and an image transmission module 420, configured to transmit, when the current signal access channel is in the second channel, an image to be displayed to the field programmable gate array processor, so that the field programmable gate array processor outputs the image to be displayed to the display panel for display.
Optionally, after monitoring that the control interface calls the instruction, the processing module 410 switches the current signal access channel from the first channel to the second channel, and acquires an image input by the external device by the field programmable gate array processor, further configured to:
and generating the image to be displayed according to the image input by the external equipment of the field programmable gate array processor and the control interface called by the control interface calling instruction.
Optionally, the image transmission module 420 transmits the image to be displayed to the field programmable gate array processor, specifically:
outputting the image to be displayed with a first resolution to the field programmable gate array processor;
when the to-be-displayed image is output to the display panel for display, the field programmable gate array processor converts the to-be-displayed image with a first resolution into the to-be-displayed image with a second resolution and outputs the to-be-displayed image with the second resolution to the display panel for display;
the second resolution is greater than the first resolution.
Optionally, the apparatus further comprises:
the image generating module 430 is configured to, when the current signal access channel is in the second channel, generate the image to be displayed according to the control interface called by the control interface calling instruction if the control interface calling instruction is monitored.
Optionally, the apparatus further comprises a switching module 440 configured to:
after a control interface is displayed on a display panel, if a switching instruction of a signal access channel is monitored within a preset time, responding to the switching instruction to switch the signal access channel;
after the display panel displays the control interface, a switching instruction of the signal access channel is not monitored after a preset time length, and the current signal access channel before the control interface calling instruction is received is a first channel, and the current signal access channel is switched to the first channel.
By adopting the display control method and the display control device, the display panel can play the input image of the external equipment connected with the FPGA processor and display the effect of a control interface, and the signal input channel can be switched from the external equipment connected with the FPGA processor to the storage equipment of the SoC, so that the high-resolution display of the image from the SoC on the display panel is realized.
The embodiment of the invention also provides a display control method, which is applied to a display control system comprising a system processing chip and a field programmable gate array processor which are connected, wherein the field programmable gate array processor is connected with a display panel, and the method comprises the following steps:
when monitoring a control interface calling instruction and a current signal access channel is in a first channel, the system processing chip acquires an image input by the field programmable gate array processor through external equipment and switches the current signal access channel into a second channel;
when the system processing chip monitors a control interface calling instruction and a current signal access channel is in a first channel, the field programmable gate array processor transmits an image currently input by external equipment to the system processing chip;
when the current signal access channel is in a first channel, the image source of the display panel is the external device; and when the current signal access channel is in the second channel, the image source of the display panel is the system processing chip.
Optionally, when the current signal access channel is in the first channel, the system processing chip monitors a control interface call instruction, and outputs a data transmission instruction to the field programmable gate array processor;
the field programmable gate array processor transmits the image input by the external equipment to the system processing chip according to the data transmission instruction;
the system processing chip generates the image to be displayed according to the image input by the external equipment of the field programmable gate array processor and the control interface called by the control interface calling instruction, and transmits the image to be displayed to the field programmable gate array processor;
and the field programmable gate array processor transmits the image to be displayed output by the system processing chip to a display panel for display.
Optionally, the method further comprises:
when the current signal access channel is in a second channel, the system processing chip transmits an image to be displayed to the field programmable gate array processor;
and the field programmable gate array processor outputs the image to be displayed to the display panel for display.
Optionally, after monitoring a control interface call instruction, the system processing chip switches the current signal access channel from the first channel to the second channel, and acquires an image input by the external device to the field programmable gate array processor, the method further includes:
and the system processing chip generates the image to be displayed according to the image input by the external equipment of the field programmable gate array processor and the control interface called by the control interface calling instruction.
Optionally, the system processing chip outputs the image to be displayed with a first resolution to the field programmable gate array processor when transmitting the image to be displayed to the field programmable gate array processor;
when the field programmable gate array processor outputs the image to be displayed to the display panel for display, the field programmable gate array processor converts the image to be displayed with a first resolution into the image to be displayed with a second resolution and outputs the image to be displayed to the display panel for display;
the second resolution is greater than the first resolution.
Optionally, the method further comprises:
when the system processing chip does not monitor a control interface calling instruction and the current signal access channel is in the first channel, the field programmable gate array processor directly transmits the current input image of the external equipment to the display panel for display.
Optionally, the method further comprises:
and when the current signal access channel is in the second channel, if a control interface calling instruction is monitored, the system processing chip generates the image to be displayed according to the control interface called by the control interface calling instruction.
Optionally, the method further comprises:
after a display panel displays a control interface, if the system processing chip monitors a switching instruction of a signal access channel within a preset time, responding to the switching instruction to switch the signal access channel;
after the display panel displays the control interface, the system processing chip does not monitor a switching instruction of the signal access channel after a preset time length, and switches the current signal access channel into the first channel if the current signal access channel before receiving the control interface calling instruction is the first channel.
Specifically, the connection manner between the system processing chip, the field programmable gate array processor and the display panel and the specific process for respectively executing the display control method according to the embodiment of the present invention may refer to the detailed description above with reference to fig. 1, and are not described herein again.
While the preferred embodiments of the present invention have been described, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention.
Claims (14)
1. A display control system is characterized by comprising a system processing chip and a field programmable gate array processor which are connected, wherein the field programmable gate array processor is connected with a display panel, and the display control system comprises:
the system processing chip is configured to: when a control interface calling instruction is monitored and a current signal access channel is in a first channel, acquiring an image input by external equipment of the field programmable gate array processor, switching the current signal access channel into a second channel, taking the image input by the external equipment and transmitted by the field programmable gate array processor as a background, and taking the control interface called by the control interface calling instruction as a superposed picture on the background to generate an image to be displayed according to the image input by the external equipment of the field programmable gate array processor and the control interface called by the control interface calling instruction; when the current signal access channel is in a second channel, transmitting the image to be displayed to the field programmable gate array processor;
the field programmable gate array processor is configured to: when the system processing chip monitors a control interface calling instruction and a current signal access channel is in a first channel, transmitting a current input image of the external equipment to the system processing chip; after the system processing chip switches the current signal access channel from the first channel to the second channel, transmitting the image currently input by the external equipment to the system processing chip, and outputting the image to be displayed transmitted by the system processing chip to the display panel for displaying;
when the current signal access channel is in a first channel, the image source of the display panel is the external device; and when the current signal access channel is in the second channel, the image source of the display panel is the system processing chip.
2. The display control system according to claim 1, wherein the system processing chip outputs the image to be displayed with a first resolution to the field programmable gate array processor while transmitting the image to be displayed to the field programmable gate array processor;
when the field programmable gate array processor outputs the image to be displayed to the display panel for display, the field programmable gate array processor converts the image to be displayed with a first resolution into the image to be displayed with a second resolution and outputs the image to be displayed to the display panel for display;
the second resolution is greater than the first resolution.
3. The display control system of claim 2, wherein the second resolution is 2 times the first resolution.
4. The display control system of claim 1, wherein the field programmable gate array processor is further configured to: when the system processing chip does not monitor a control interface calling instruction and the current signal access channel is in the first channel, the current input image of the external equipment is directly transmitted to the display panel for display.
5. The display control system of claim 1, wherein the system processing chip is further configured to:
and when the current signal access channel is in the second channel, if a control interface calling instruction is monitored, generating the image to be displayed according to the control interface called by the control interface calling instruction.
6. The display control system of claim 1, wherein the system processing chip is further configured to:
after a control interface is displayed on a display panel, if a switching instruction of a signal access channel is monitored within a preset time, responding to the switching instruction to switch the signal access channel;
after the display panel displays the control interface, a switching instruction of the signal access channel is not monitored after a preset time length, and the current signal access channel before the control interface calling instruction is received is a first channel, and the current signal access channel is switched to the first channel.
7. The display control system of claim 1, wherein the system processing chip is further configured to: when a control interface calling instruction is monitored and the current signal access channel is in the first channel, outputting a data transmission instruction to the field programmable gate array processor;
the field programmable gate array is further configured to: and when the current signal access channel is in the first channel, responding to the data transmission instruction, and transmitting the current input image of the external equipment to the system processing chip.
8. The display control system according to claim 7, wherein the system processing chip sends the data transmission instruction to the field programmable gate array through a first interface, and receives an image output by the field programmable gate array through a second interface.
9. A display control method is applied to a system processing chip, the system processing chip is connected with a field programmable gate array processor, and the field programmable gate array processor is connected with a display panel, wherein the display control method comprises the following steps:
when a control interface calling instruction is monitored and a current signal access channel is in a first channel, acquiring an image input by external equipment of the field programmable gate array processor, and switching the current signal access channel into a second channel;
according to the image input by the external equipment of the field programmable gate array processor and the control interface called by the control interface calling instruction, taking the image input by the external equipment and transmitted by the field programmable gate array processor as a background, and taking the control interface called by the control interface calling instruction as a superposed picture on the background to generate an image to be displayed; when the current signal access channel is in a second channel, transmitting the image to be displayed to the field programmable gate array processor so that the field programmable gate array processor outputs the image to be displayed to the display panel for display;
when the current signal access channel is in a first channel, the image source of the display panel is an external device connected with the field programmable gate array processor; and when the current signal access channel is in the second channel, the image source of the display panel is the system processing chip.
10. The display control method of claim 9, wherein transmitting an image to be displayed to the field programmable gate array processor comprises:
outputting the image to be displayed with a first resolution to the field programmable gate array processor;
when the to-be-displayed image is output to the display panel for display, the field programmable gate array processor converts the to-be-displayed image with a first resolution into the to-be-displayed image with a second resolution and outputs the to-be-displayed image with the second resolution to the display panel for display;
the second resolution is greater than the first resolution.
11. The display control method according to claim 9, characterized in that the method further comprises:
and when the current signal access channel is in the second channel, if a control interface calling instruction is monitored, generating the image to be displayed according to the control interface called by the control interface calling instruction.
12. The display control method according to claim 9, characterized in that the method further comprises:
after a control interface is displayed on a display panel, if a switching instruction of a signal access channel is monitored within a preset time, responding to the switching instruction to switch the signal access channel;
after the display panel displays the control interface, a switching instruction of the signal access channel is not monitored after a preset time length, and the current signal access channel before the control interface calling instruction is received is a first channel, and the current signal access channel is switched to the first channel.
13. A display control device is applied to a system processing chip, the system processing chip is connected with a field programmable gate array processor, the field programmable gate array processor is connected with a display panel, and the display control device comprises:
the processing module is used for acquiring an image input by the field programmable gate array processor from the external equipment when monitoring a control interface calling instruction and a current signal access channel is in a first channel, and switching the current signal access channel into a second channel; and
according to the image input by the external equipment of the field programmable gate array processor and the control interface called by the control interface calling instruction, taking the image input by the external equipment and transmitted by the field programmable gate array processor as a background, and taking the control interface called by the control interface calling instruction as a superposed picture on the background to generate an image to be displayed; when the current signal access channel is in a second channel, transmitting the image to be displayed to the field programmable gate array processor so that the field programmable gate array processor outputs the image to be displayed to the display panel for display;
when the current signal access channel is in a first channel, the image source of the display panel is an external device connected with the field programmable gate array processor; and when the current signal access channel is in the second channel, the image source of the display panel is the system processing chip.
14. A display control method is applied to a display control system comprising a system processing chip and a field programmable gate array processor which are connected, wherein the field programmable gate array processor is connected with a display panel, and the method comprises the following steps:
when monitoring a control interface calling instruction and a current signal access channel is in a first channel, the system processing chip acquires an image input by an external device of the field programmable gate array processor, switches the current signal access channel into a second channel, and generates an image to be displayed by taking the image input by the external device and transmitted by the field programmable gate array processor as a background and taking the control interface called by the control interface calling instruction as a superposed picture on the background according to the image input by the external device of the field programmable gate array processor and the control interface called by the control interface calling instruction; when the current signal access channel is in a second channel, transmitting the image to be displayed to the field programmable gate array processor;
when the system processing chip monitors a control interface calling instruction and a current signal access channel is in a first channel, the field programmable gate array processor transmits an image currently input by external equipment to the system processing chip; after the system processing chip switches the current signal access channel from the first channel to the second channel, transmitting the image currently input by the external equipment to the system processing chip, and outputting the image to be displayed transmitted by the system processing chip to the display panel for displaying;
when the current signal access channel is in a first channel, the image source of the display panel is the external device; and when the current signal access channel is in the second channel, the image source of the display panel is the system processing chip.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910413427.7A CN110087006B (en) | 2019-05-17 | 2019-05-17 | Display control system, method and device |
| PCT/CN2020/085090 WO2020233295A1 (en) | 2019-05-17 | 2020-04-16 | Display control system, method and apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910413427.7A CN110087006B (en) | 2019-05-17 | 2019-05-17 | Display control system, method and device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110087006A CN110087006A (en) | 2019-08-02 |
| CN110087006B true CN110087006B (en) | 2022-04-15 |
Family
ID=67420731
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910413427.7A Active CN110087006B (en) | 2019-05-17 | 2019-05-17 | Display control system, method and device |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN110087006B (en) |
| WO (1) | WO2020233295A1 (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110087006B (en) * | 2019-05-17 | 2022-04-15 | 京东方科技集团股份有限公司 | Display control system, method and device |
| CN111405213B (en) | 2020-03-24 | 2022-08-09 | 京东方科技集团股份有限公司 | Interface access method, display device and electronic equipment |
| CN111464783B (en) * | 2020-03-31 | 2021-10-01 | 京东方科技集团股份有限公司 | Monitor system and display control method thereof |
| WO2022148056A1 (en) * | 2021-01-11 | 2022-07-14 | 海信视像科技股份有限公司 | Display device and driving method |
| CN114302196B (en) * | 2021-01-14 | 2023-05-05 | 海信视像科技股份有限公司 | Display device, external device and play parameter adjusting method |
| CN116126651A (en) * | 2022-11-08 | 2023-05-16 | 广东高云半导体科技股份有限公司 | System and method for realizing display processing |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103995598A (en) * | 2014-02-26 | 2014-08-20 | 山东超越数控电子有限公司 | HPS-based OSD interface switching scheme of FPGA |
| JP2017003756A (en) * | 2015-06-10 | 2017-01-05 | シャープ株式会社 | Liquid crystal display and television apparatus |
| CN106385553A (en) * | 2016-08-14 | 2017-02-08 | 深圳市芯智科技有限公司 | High-resolution ultrahigh-definition display system and method |
| CN107493444A (en) * | 2017-08-21 | 2017-12-19 | 康佳集团股份有限公司 | A kind of 8K TVs and its implementation for supporting double-channel signal |
| CN107566765A (en) * | 2017-08-21 | 2018-01-09 | 康佳集团股份有限公司 | A kind of on-screen menu display control method, storage medium and 8K TVs |
| CN108063904A (en) * | 2018-01-18 | 2018-05-22 | 康佳集团股份有限公司 | A kind of television set double-channel signal switching system, method and television set |
| CN109089063A (en) * | 2018-09-30 | 2018-12-25 | 深圳市天视通电子科技有限公司 | A kind of video resolution regulating system, method and built-in network video recorder |
| CN109445876A (en) * | 2018-12-12 | 2019-03-08 | 北京时代奥视科技有限公司 | The method and monitor of LUT data load |
| CN109801586A (en) * | 2019-03-26 | 2019-05-24 | 京东方科技集团股份有限公司 | Display controller, display control method and system, display device |
| CN110336961A (en) * | 2019-05-30 | 2019-10-15 | 深圳小佳科技有限公司 | Television channel switching handling method, TV and storage medium |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102246556B1 (en) * | 2014-12-02 | 2021-04-30 | 엘지전자 주식회사 | Multimedia device and method for controlling the same |
| CN105657487A (en) * | 2015-08-21 | 2016-06-08 | 乐视致新电子科技（天津）有限公司 | Audio/video playing equipment |
| CN204836362U (en) * | 2015-08-30 | 2015-12-02 | 深圳市特力科信息技术有限公司 | High definition video OSD menu stack module based on FPGA |
| CN105677254B (en) * | 2016-01-06 | 2019-10-25 | 深圳市紫光同创电子有限公司 | A kind of data processing method and device |
| US10979728B2 (en) * | 2017-04-24 | 2021-04-13 | Intel Corporation | Intelligent video frame grouping based on predicted performance |
| CN108632505B (en) * | 2018-03-21 | 2020-12-01 | 西安电子科技大学 | High dynamic video processing system based on SoC FPGA |
| CN110087006B (en) * | 2019-05-17 | 2022-04-15 | 京东方科技集团股份有限公司 | Display control system, method and device |
-
2019
- 2019-05-17 CN CN201910413427.7A patent/CN110087006B/en active Active
-
2020
- 2020-04-16 WO PCT/CN2020/085090 patent/WO2020233295A1/en active Application Filing
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103995598A (en) * | 2014-02-26 | 2014-08-20 | 山东超越数控电子有限公司 | HPS-based OSD interface switching scheme of FPGA |
| JP2017003756A (en) * | 2015-06-10 | 2017-01-05 | シャープ株式会社 | Liquid crystal display and television apparatus |
| CN106385553A (en) * | 2016-08-14 | 2017-02-08 | 深圳市芯智科技有限公司 | High-resolution ultrahigh-definition display system and method |
| CN107493444A (en) * | 2017-08-21 | 2017-12-19 | 康佳集团股份有限公司 | A kind of 8K TVs and its implementation for supporting double-channel signal |
| CN107566765A (en) * | 2017-08-21 | 2018-01-09 | 康佳集团股份有限公司 | A kind of on-screen menu display control method, storage medium and 8K TVs |
| CN108063904A (en) * | 2018-01-18 | 2018-05-22 | 康佳集团股份有限公司 | A kind of television set double-channel signal switching system, method and television set |
| CN109089063A (en) * | 2018-09-30 | 2018-12-25 | 深圳市天视通电子科技有限公司 | A kind of video resolution regulating system, method and built-in network video recorder |
| CN109445876A (en) * | 2018-12-12 | 2019-03-08 | 北京时代奥视科技有限公司 | The method and monitor of LUT data load |
| CN109801586A (en) * | 2019-03-26 | 2019-05-24 | 京东方科技集团股份有限公司 | Display controller, display control method and system, display device |
| CN110336961A (en) * | 2019-05-30 | 2019-10-15 | 深圳小佳科技有限公司 | Television channel switching handling method, TV and storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2020233295A1 (en) | 2020-11-26 |
| CN110087006A (en) | 2019-08-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110087006B (en) | Display control system, method and device | |
| CN111899680B (en) | Display device and setting method thereof | |
| US20070177015A1 (en) | Image data transfer processor and surveillance camera system | |
| JP2018093305A (en) | Display device, control method for the same, program, and storage medium | |
| US20030080985A1 (en) | Method of adjusting image, and image display system, image display device and image data generation device | |
| CN112954419B (en) | Display device and display method | |
| CA2732781C (en) | Method and apparatus for selecting video channel, video device and tv device | |
| CN111684792B (en) | Video display device, video display method, and video signal processing device | |
| US11545071B2 (en) | Display device and control method thereof | |
| WO2017181760A1 (en) | Media playing control method, media source device, and media playing device and system | |
| CN114157898A (en) | Signal switching system and signal switching method | |
| CN111026497A (en) | Device for providing multiple screens and method for dynamically configuring multiple screens | |
| KR20170133170A (en) | Method and system for providing video | |
| KR100818238B1 (en) | Multi-display circuit system | |
| CN113014915B (en) | Signal source equipment and signal generation method thereof | |
| CN215072653U (en) | Video seamless switching circuit and device and system thereof | |
| US20240113958A1 (en) | Electronic device and mode switching method | |
| CN211378162U (en) | Digital television test signal transmitting device | |
| JP6150571B2 (en) | Display device and control method thereof | |
| CN213122917U (en) | KVM multi-system combined control device based on OSD | |
| CN217825156U (en) | Image display system | |
| CN111541923B (en) | Remote control method, storage medium, processor, remote control equipment and remote control system | |
| TWM569117U (en) | Wireless message transceiver system | |
| CN213751890U (en) | LED control system with video processing function | |
| CN114449239A (en) | Control method of projection equipment, projection equipment and communication equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |