CN201682555U - 3G-SD I high definition digital video signal generator - Google Patents
3G-SD I high definition digital video signal generator Download PDFInfo
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- CN201682555U CN201682555U CN2009202480775U CN200920248077U CN201682555U CN 201682555 U CN201682555 U CN 201682555U CN 2009202480775 U CN2009202480775 U CN 2009202480775U CN 200920248077 U CN200920248077 U CN 200920248077U CN 201682555 U CN201682555 U CN 201682555U
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Abstract
With the view to satisfy broadband user's need for high code rated and low jitter digital video signal source in the voice frequency field, the utility model provides a 3G-SD1 high definition digital video signal generator which comprises an oscillator, a precision clock regulator, a control button, a display, an FPGA, a parallel/serial converter as well as a power source. The oscillator is connected with the precision clock regulator and the FPGA is connected with all the other components except the oscillator. The model and format of a digital video signal are pre-stored in the FPGA; the calculating method of generating static images is available in the IP core of the FPGA; the signal generator is capable of outputting a digital serial signal with an maximal transmission rate of 3Gbps and also capable of outputting multi-model and multi-format signals in convenient and practical ways and with a high assurance factor.
Description
Technical field
The utility model belongs to the video and audio frequency technology applications field in the electronic information field, relates to a kind of digital video generator.
Technical background
Growing along with science and technology, people's living standard is more and more higher.In broadcast television industry, simulated television is replaced by the digital video display instrument gradually, and relevant looks the development that the audio frequency industry also begins to pay close attention to all the more 3G-SDI (serial digital interface of 3Gbps speed).The digital television signal definition develops into 1280 * 720p (lining by line scan) and 1920 * 1080i by the 720 * 576i (interlacing scan) of single-definition, and up-to-date high definition digital television signal has reached 1920 * 1080p, i.e. 3G digital TV in high resolution signal.Present display generally can be supported the signal input of 1080p, also has some DVD and high definition player to support output of 1080p analog component signal and HDMI (HDMI (High Definition Multimedia Interface)) output as signal source.But the bandwidth that the 3G-SDI signal generator provides is very big, and code check is 2 times of high definition sdi signal source, and the technical indicator of various aspects all will promote like this, and higher to the requirement of low jitter, and these all will increase the design difficulty of 3G-SDI signal generator.
Summary of the invention
In order to overcome above technical problem, the utility model provides a kind of 3G-SDI high-definition digital video signal generator.It is based on the 3G-SDI signal generator of FPGA (field programmable logic array), produce the 3G-SDI digital video test signal of multiple prescribed form by the programmed algorithm of FPGA, signal format is backward compatible, support SD-SDI (serial digital interface of single-definition) and HD-SDI (serial digital interface of high definition), and support to embed audio-frequency function.Simultaneously, utilize USB (USB) interface and SD (safe digital card)/MMC (multimedia card) interface can also export the dynamic or static test signal of User Defined programming.
For realizing above purpose, the technical solution of the utility model is:
3G-SDI high-definition digital video signal generator comprises oscillator 1, precision interval clock adjuster 2, control button 6, display 7, FPGA8, parallel-to-serial converter 9 and power supply 10; Oscillator 1 is connected with precision interval clock adjuster 2, and FPGA8 is connected with each parts except that oscillator 1; Prestore among the FPGA8 pattern and the form of digital video signal have the algorithm that generates still image in the IP kernel of FPGA8.
The operation principle of this signal generator is: oscillator 1 clocking; The user makes order by 6 couples of FPGA8 of control button then, select the signal mode and the signal format of output, precision interval clock adjuster 2 receives the instruction that FPGA8 transmits, signal mode and the corresponding surge frequency range of form that the clock signal that oscillator is produced is modulated into and selects input among the FPGA8; FPGA8 selects corresponding internal algorithm in the IP kernel, generate a frame test pattern, then this process is carried out repetition, export with the parallel digital signal form according to the form that the user selects, use the transmission rate of the frequency of oscillation of precision interval clock adjuster 2 modulation as clock control output parallel digital signal; At last, the signal of 9 pairs of parallel-to-serial converters and line output carries out and goes here and there conversion process, obtains serial digital signal, and reaches the standard transmission speed of requirement pattern.
Display 7 shows the pattern and the form of output signal in real time;
Power supply 10 is FPGA 8 and peripheral chip power supply.
Further improvement of the utility model is: this signal generator also is provided with USB interface 3, SD/MMC card 4 and synchronous DRAM 5, and the three all is connected with FPGA8.The user can import self-defining picture signal to FPGA 8 by USB interface 3 or SD/MMC card 4, FPGA 8 is by the internal algorithm of its IP kernel, the serial signal of input is changed into parallel signal and deposits among the SDRAM 5, be input among the FPGA 8 with higher rate then, according to select form through preset algorithm with signal layout again, generate the parallel digital signal that requires.Export the transmission rate of parallel digital video signal again as clock control with the frequency of oscillation of precision interval clock adjuster 2 modulation.
The signal format that this signal generator can produce has 11 kinds: the digital video signal that generates output 1080p@50Hz, 1080p@59.94Hz, 1080p@60Hz form under 2.97Gbps speed; Under 1.485Gbps and 1.483Gbps speed, generate the digital video signal of output 1080i@50Hz, 1080i@59.94Hz, 1080i@60Hz, 720p@50Hz, 720p@59.94Hz and 720p@60Hz form; Generate the signal of output 480i and 576i form in the SD scope.
The signal mode that this signal generator prestores has 9 kinds: color bar signal, frequency signal, black burst, ill-condition matrix signal, brightness gradient signal, Y/C gamut ramp signal, SMPTE 75% bar shaped signal, SMPTE RP219 bar shaped signal and bright pulse and bar shaped signal.
Another improvement of written or printed documents signal generator is: can be in every parallel digital signal passage embedded audio signal, undertaken by 9 pairs of video/audio signals of parallel-to-serial converter again and go here and there conversion process, output contains the serial digital signal of embedded audio.
The beneficial effects of the utility model are: this signal generator is core with FPGA, by to the writing of its inside IP kernel, and has realized following function with the assembly of peripheral circuit: generate the digital serial signal that output is up to the 3Gbps transmission rate; The signal of output multi-mode, multi-format is supported to embed audio frequency, can satisfy the requirement of most fields to signal source, and is convenient, practical; This invention is with low cost, the coefficient of safety height.
Description of drawings
Fig. 1 is the signal generating system structure chart of 3G-SDI high-definition digital video signal generator;
Fig. 2 is the signal generating system workflow diagram of 3G-SDI high-definition digital video signal generator;
Fig. 3 is the outside drawing in kind of 3G-SDI high-definition digital video signal generator.
Embodiment
Embodiment 1
Below in conjunction with the drawings and specific embodiments the utility model is elaborated.
As shown in Figure 1, the 3G-SDI signal generator comprises oscillator 1, precision interval clock adjuster 2, control button 6, display 7, FPGA 8, parallel-to-serial converter 9 and power supply 10.Oscillator 1 connects precision interval clock adjuster 2, and FPGA 8 is connected with each parts except that oscillator 1.There is the algorithm that generates still image in the IP kernel of FPGA (8).
The workflow diagram of signal generating system as shown in Figure 2:
At first, by oscillator 1 clocking.The user makes order by 6 couples of FPGA8 of control button, select the signal mode and the signal format of output, precision interval clock adjuster 2 receives the instruction that FPGA8 transmits, signal mode and the corresponding surge frequency range of form that the clock signal that oscillator is produced is modulated into and selects input among the FPGA8.
Then, FPGA8 selects corresponding internal algorithm in the IP kernel, generate a frame test pattern, the form of selecting according to the user carries out repetition to this process, with the output of parallel digital signal form, export the transmission rate of parallel digital signal as clock control with the frequency of oscillation of precision interval clock adjuster 2 modulation.
If desired image is embedded audio frequency, can be in parallel data signal embedded audio signal.
At last, 9 pairs of signals of parallel-to-serial converter carry out and go here and there conversion process, the output serial digital signal.
Display 7 shows the pattern and the form of this signal in real time, if the user imports self-defining signal pattern, display 7 can the shows signal image be user-defined mode (a self-defined pattern).
Power supply 10 is FPGA 8 and peripheral chip power supply.
This 3G-SDI signal generating system can generate 11 kinds of format signals altogether, can generate the digital video signal of output 1080p@50Hz, 1080p@59.94Hz, 1080p@60Hz form under 2.97Gbps speed; Under 1.485Gbps and 1.483Gbps speed, can generate the digital video signal of output 1080i@50Hz, 1080i@59.94Hz, 1080i@60Hz, 720p@50Hz, 720p@59.94Hz and 720p@60Hz form; Can generate the signal of output 480i and these two kinds of forms of 576i in the SD scope.
This system prestore output signal mode have 9 kinds: color bar signal, frequency signal, black burst, ill-condition matrix signal, brightness gradient signal, Y/C gamut ramp signal, SMPTE 75% bar shaped signal, SMPTE RP219 bar shaped signal and bright pulse and bar shaped signal.Because FPGA has good programmability, can increase new signal format and pattern by upgrading chip program.
As shown in Figure 3, the using method of this signal generator: after system powers on, at first press switch, the waiting system initialization.Configuration to signal is provided with, and presses the ENTER key and confirms that system will preset the signal of this type.Press the RUN key then, signal generator begins to export the signal that presets.When each shutdown was started shooting again, signal generator was preserved the state behind the last operation automatically, and can recover running status last time.
Embodiment 2
Change the mode of the generation parallel digital video signal in this system works flow process: can import self-defining picture signal in order to make the user, this system also is provided with USB interface 3, SD/MMC card 4 and SDRAM 5, all is connected with FPGA8.The user imports self-defining picture signal to FPGA8 by USB interface 3 or SD/MMC card 4, FPGA8 is by the internal algorithm of its IP kernel, the serial signal of input is changed into parallel signal and deposits among the SDRAM 5, be input among the FPGA 8 with higher rate then, according to select form through preset algorithm with signal layout again, generate the parallel digital signal that requires.Export the transmission rate of parallel digital video signal again as clock control with the frequency of oscillation of precision interval clock adjuster 2 modulation.This is the further improvement of native system, makes the function hommization more of this signal generating system.
When adopting this mode to generate parallel signal, the using method of this signal generator is: after system powers on, at first press switch, the waiting system initialization.Insert SD/MMC card or USB memory device after initialization finishes, import picture, press the ENTER key and confirm that system will preset the signal that User Defined is provided with.Press the RUN key then, signal generator begins to export the signal that presets.When each shutdown was started shooting again, signal generator was preserved the state behind the last operation automatically, and can recover running status last time.
In addition described with embodiment 1.
Claims (4)
1.3G-SDI the high-definition digital video signal generator is characterized in that, it comprises oscillator (1), precision interval clock adjuster (2), control button (6), display (7), FPGA (8), parallel-to-serial converter (9) and power supply (10); Oscillator (1) is connected with precision interval clock adjuster (2), and FPGA (8) is connected with each parts except that oscillator (1); Prestore among the FPGA (8) pattern and the form of digital video signal have the algorithm that generates still image in the IP kernel of FPGA (8).
2. 3G-SDI high-definition digital video signal generator according to claim 1 is characterized in that, this signal generator also is provided with USB interface (3), SD/MMC card (4) and synchronous DRAM (5), all is connected with FPGA (8).
3. 3G-SDI high-definition digital video signal generator according to claim 1, it is characterized in that described signal format has 11 kinds: the digital video signal that under 2.97Gbps speed, generates output 1080p@50Hz, 1080p@59.94Hz, 1080p@60Hz form; Under 1.485Gbps and 1.483Gbps speed, generate the digital video signal of output 1080i@50Hz, 1080i@59.94Hz, 1080i@60Hz, 720p@50Hz, 720p@59.94Hz and 720p@60Hz form; Generate the signal of output 480i and 576i form in the SD scope.
4. 3G-SDI high-definition digital video signal generator according to claim 1, it is characterized in that described signal mode has 9 kinds: color bar signal, frequency signal, black burst, ill-condition matrix signal, brightness gradient signal, Y/C gamut ramp signal, SMPTE 75% bar shaped signal, SMPTE RP219 bar shaped signal and bright pulse and bar shaped signal.
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| CN2009202480775U CN201682555U (en) | 2009-11-13 | 2009-11-13 | 3G-SD I high definition digital video signal generator |
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| CN2009202480775U CN201682555U (en) | 2009-11-13 | 2009-11-13 | 3G-SD I high definition digital video signal generator |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103873802A (en) * | 2012-12-18 | 2014-06-18 | 深圳市广平正科技有限责任公司 | High-definition video signal generator and signal generating method thereof |
| CN104486576A (en) * | 2014-12-30 | 2015-04-01 | 南京巨鲨显示科技有限公司 | Conversion system converting full-interface input signals to SDI output signals |
| CN104822040A (en) * | 2015-04-28 | 2015-08-05 | 深圳市载德光电技术开发有限公司 | Multi-format video sequence generation system based on FPGA and method thereof |
| CN106254800A (en) * | 2015-12-30 | 2016-12-21 | 合肥爱维信息科技有限公司 | Radio and television high definition all-in-one |
-
2009
- 2009-11-13 CN CN2009202480775U patent/CN201682555U/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103873802A (en) * | 2012-12-18 | 2014-06-18 | 深圳市广平正科技有限责任公司 | High-definition video signal generator and signal generating method thereof |
| CN104486576A (en) * | 2014-12-30 | 2015-04-01 | 南京巨鲨显示科技有限公司 | Conversion system converting full-interface input signals to SDI output signals |
| CN104822040A (en) * | 2015-04-28 | 2015-08-05 | 深圳市载德光电技术开发有限公司 | Multi-format video sequence generation system based on FPGA and method thereof |
| CN104822040B (en) * | 2015-04-28 | 2018-06-19 | 深圳市载德光电技术开发有限公司 | A kind of multiple format video sequence generation system and method based on FPGA |
| CN106254800A (en) * | 2015-12-30 | 2016-12-21 | 合肥爱维信息科技有限公司 | Radio and television high definition all-in-one |
| CN106254800B (en) * | 2015-12-30 | 2019-08-20 | 合肥爱维信息科技有限公司 | Radio and television high definition all-in-one machine |
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Granted publication date: 20101222 Termination date: 20131113 |