CN101720008B

CN101720008B - 3G-SDI high-definition digital video signal generation system

Info

Publication number: CN101720008B
Application number: CN2009102198730A
Authority: CN
Inventors: 周春雷; 刘兴华
Original assignee: DALIAN KEDI VIDEO TECHNOLOGY Co Ltd
Current assignee: DALIAN KEDI VIDEO TECHNOLOGY Co Ltd
Priority date: 2009-11-13
Filing date: 2009-11-13
Publication date: 2011-04-20
Anticipated expiration: 2029-11-13
Also published as: CN101720008A

Abstract

The invention provides a 3G-SDI high-definition digital video signal generation system for satisfying the demands of video/audio fields on digital video signal sources with broadband, high code rate and low jitter. A user selects inputting signal patterns and formats through control keys; a precision interval clock regulator modulates a clock signal generated by an oscillator in a corresponding oscillation frequency range and transmits to an FPGA; the FPGA generates and outputs a required parallel digital signal through a corresponding internal algorithm in an IP core; and parallel/series conversion is conducted by a parallel/series converter to obtain a series digital signal, and a standard transmission rate of a required pattern is reached. The signal generation system can generate and output digital series signals with transmission rate as high as 3Gbps and can output signals with multiple patterns and formats; in addition, the signal generation system is convenient and practical and has high safety factor.

Description

The 3G-SDI high-definition digital video signal generation system

Technical field

The invention belongs to the video and audio frequency technology applications field in the electronic information field, relate to a kind of digital video signal generating system.

Technical background

Growing along with science and technology, people's living standard is more and more higher.In broadcast television industry, simulated television is replaced by the digital video display instrument gradually, and relevant looks the development that the audio frequency industry also begins to pay close attention to all the more 3G-SDI (serial digital interface of 3Gbps speed).The digital television signal definition develops into 1280 * 720p (lining by line scan) and 1920 * 1080i by the 720 * 576i (interlacing scan) of single-definition, and up-to-date high definition digital television signal has reached 1920 * 1080p, i.e. 3G digital TV in high resolution signal.Present display generally can be supported the signal input of 1080p, also has some DVD and high definition player to support output of 1080p analog component signal and HDMI (HDMI (High Definition Multimedia Interface)) output as signal source.But the bandwidth that the 3G-SDI signal generator provides is very big, and code check is 2 times of high definition sdi signal source, and the technical indicator of various aspects all will promote like this, and higher to the requirement of low jitter, and these all will increase the design difficulty of 3G-SDI signal generator.

Summary of the invention

In order to overcome above technical problem, the invention provides a kind of 3G-SDI high-definition digital video signal generation system.This system is based on the 3G-SDI signal generating system of FPGA (field programmable logic array), produce the 3G-SDI digital video test signal of multiple prescribed form by the programmed algorithm of FPGA, signal format is backward compatible, support SD-SDI (serial digital interface of single-definition) and HD-SDI (serial digital interface of high definition), and support to embed audio-frequency function.Simultaneously, utilize USB (USB) interface and SD (safe digital card)/MMC (multimedia card) interface can also export the dynamic or static test signal of User Defined programming.

For realizing above purpose, technical scheme of the present invention is:

The workflow of 3G-SDI signal generating system:

A. oscillator 1 clocking;

B. the user makes order by 6 couples of FPGA8 of control button, select the signal mode and the signal format of output, precision interval clock adjuster 2 receives the instruction that FPGA8 transmits, and the corresponding surge frequency range of signal format that the clock signal that oscillator is produced is modulated into and selects inputs among the FPGA8;

C.FPGA8 selects corresponding internal algorithm in the IP kernel, generate a frame test pattern, then this process is carried out repetition, export with the parallel digital signal form according to the form that the user selects, the frequency of oscillation of using the modulation of b process is controlled the transmission rate of output parallel digital signal as clock frequency;

D. the parallel digital signal of the 9 couples of FPGA8 of parallel-to-serial converter output carries out and goes here and there conversion process, obtains serial digital signal, and reaches the standard transmission speed of requirement pattern;

Display 7 shows the pattern and the form of output signal in real time;

Power supply 10 is the overall work circuit supply.

Further improvement of the present invention: native system also is provided with USB interface 3, SD/MMC card 4 and SDRAM (synchronous DRAM) 5, all is connected with FPGA 8.The user can import self-defining picture signal to FPGA 8 by USB interface 3 or SD/MMC card 4, FPGA 8 is by the internal algorithm of its IP kernel, the serial signal of input is changed into parallel signal and deposits among the SDRAM 5, be input among the FPGA 8 with higher rate then, according to select form through preset algorithm with signal layout again, generate the parallel digital signal that requires.Again with the frequency of oscillation of precision interval clock adjuster 2 modulation as clock frequency, control the transmission rate of output parallel digital video signal.

Native system is total to 11 kinds of energy output signal forms under different transmission rates: the digital video signal that generates output 1080p@50Hz, 1080p@59.94Hz, 1080p@60Hz form under 2.97Gbps speed; Under 1.485Gbps and 1.483Gbps speed, generate the digital video signal of output 1080i@50Hz, 1080i@59.94Hz, 1080i@60Hz, 720p@50Hz, 720p@59.94Hz and 720p@60Hz form; In the SD scope, generate the signal of output 480i and 576i form.

The output mode signal that native system prestores has 9 kinds: color bar signal, frequency signal, black burst, ill-condition matrix signal, brightness gradient signal, Y/C gamut ramp signal, SMPTE 75% bar shaped signal, SMPTE RP219 bar shaped signal and bright pulse and bar shaped signal, select for the user.

If desired image is embedded audio frequency, can be in every parallel digital signal passage embedded audio signal.Undertaken by 9 pairs of video/audio signals of parallel-to-serial converter at last and go here and there conversion process, output contains the serial digital signal of embedded audio.

The invention has the beneficial effects as follows: this signal generating system is core with FPGA, by to the writing of its inside IP kernel, and has realized following function with the assembly of peripheral circuit: generate the digital serial signal that output is up to the 3Gbps transmission rate; The signal of output multi-mode, multi-format is supported to embed audio frequency, can satisfy the requirement of most fields to signal source, and is convenient, practical; This invention is with low cost, the coefficient of safety height.

Description of drawings

Fig. 1 is the structure chart of 3G-SDI signal generating system;

Fig. 2 is the workflow diagram of 3G-SDI signal generating system;

Fig. 3 is the outside drawing in kind that adopts the signal generator of 3G-SDI signal generating system among the present invention.

Embodiment

Embodiment 1

Below in conjunction with the drawings and specific embodiments the present invention is elaborated, but be not limited to embodiment.

As shown in Figure 1, the 3G-SDI signal generating system comprises oscillator 1, precision interval clock adjuster 2, control button 6, display 7, FPGA 8, parallel-to-serial converter 9 and power supply 10.Oscillator 1 connects precision interval clock adjuster 2, and FPGA 8 is connected with each parts except that oscillator 1.

The workflow diagram of signal generating system as shown in Figure 2:

At first, by oscillator 1 clocking.The user makes order by 6 couples of FPGA8 of control button, select the signal mode and the signal format of output, precision interval clock adjuster 2 receives the instruction that FPGA8 transmits, and the corresponding surge frequency range of signal format that the clock signal that oscillator is produced is modulated into and selects inputs among the FPGA8.

Then, FPGA8 selects corresponding internal algorithm in the IP kernel, generate a frame test pattern, this process is carried out repetition, export with the parallel digital signal form according to the form that the user selects, export the transmission rate of parallel digital signal with the frequency of oscillation of precision interval clock adjuster 2 modulation as clock control.

If desired image is embedded audio frequency, can be in parallel data signal embedded audio signal.

At last, 9 pairs of parallel digital signals of exporting from FPGA8 of parallel-to-serial converter carry out and go here and there conversion process, the output serial digital signal.

Display 7 shows the pattern and the form of this signal in real time, if the user imports self-defining signal pattern, display 7 can the shows signal image be user-defined mode (a self-defined pattern).

Power supply 10 is FPGA 8 and peripheral chip power supply.

This 3G-SDI signal generating system can generate 11 kinds of format signals altogether under different transmission rates, can generate the digital video signal of output 1080p@50Hz, 1080p@59.94Hz, 1080p@60Hz form under 2.97Gbps speed; Under 1.485Gbps and 1.483Gbps speed, can generate the digital video signal of output 1080i@50Hz, 1080i@59.94Hz, 1080i@60Hz, 720p@50Hz, 720p@59.94Hz and 720p@60Hz form; In the SD scope, can generate the signal of output 480i and these two kinds of forms of 576i.

This system prestore output signal mode have 9 kinds: color bar signal, frequency signal, black burst, ill-condition matrix signal, brightness gradient signal, Y/C gamut ramp signal, SMPTE 75% bar shaped signal, SMPTE RP219 bar shaped signal and bright pulse and bar shaped signal.Because FPGA has good programmability, can increase new signal format and pattern by upgrading chip program.

As shown in Figure 3, be the using method of the signal generator of core with the native system: after system powers on, at first press switch, the waiting system initialization.Configuration to signal is provided with, and presses the ENTER key and confirms that system will preset the signal of this type.Press the RUN key then, signal generator begins to export the signal that presets.When each shutdown was started shooting again, signal generator was preserved the state behind the last operation automatically, and can recover running status last time.

Embodiment 2

Change the mode of the generation parallel digital video signal in this system works flow process: can import self-defining picture signal in order to make the user, this system also is provided with USB interface 3, SD/MMC card 4 and SDRAM 5.The user imports self-defining picture signal to FPGA 8 by USB interface 3 or SD/MMC card 4, FPGA 8 is by the internal algorithm of its IP kernel, the serial signal of input is changed into parallel signal and deposits among the SDRAM 5, be input among the FPGA 8 with higher rate then, according to select form through preset algorithm with signal layout again, generate the parallel digital signal that requires.Export the transmission rate of parallel digital video signal again as clock control with the frequency of oscillation of precision interval clock adjuster 2 modulation.This is the further improvement of native system, makes the function hommization more of this signal generating system.

When adopting this mode to generate parallel signal, the using method of this signal generator is: after system powers on, at first press switch, the waiting system initialization.Insert SD/MMC card or USB memory device after initialization finishes, import picture, press the ENTER key and confirm that system will preset the signal that User Defined is provided with.Press the RUN key then, signal generator begins to export the signal that presets.When each shutdown was started shooting again, signal generator was preserved the state behind the last operation automatically, and can recover running status last time.

In addition described with embodiment 1.

Claims

1.3G-SDI high-definition digital video signal generation system is characterized in that, the workflow of this system is:

A. oscillator (1) clocking;

B. the user makes order by control button (6) to FPGA (8), select the signal mode and the signal format of output, precision interval clock adjuster (2) receives the instruction that FPGA (8) transmits, the corresponding surge frequency range of signal format that the clock signal that oscillator is produced is modulated into and selects inputs among the FPGA (8);

C.FPGA (8) uses the internal algorithm in the IP kernel, generate a frame test pattern, then the forming process of a frame test pattern is carried out repetition, export with the form of parallel digital signal according to the form that the user selects, the frequency of oscillation of b process modulation as clock frequency, is controlled the transmission rate of output parallel digital signal;

D. parallel-to-serial converter (9) carries out the parallel digital signal of FPGA (8) output and goes here and there conversion process, obtains serial digital signal, and reaches the transmission standard of user-selected signal format;

Display (7) shows the pattern and the form of output signal in real time;

Power supply (10) is the overall work circuit supply.

The signal format that can select to export has 11 kinds: the digital video signal that generates output 1080p@50Hz, 1080p@59.94Hz, 1080p@60Hz form under 2.97Gbps speed; Under 1.485Gbps and 1.483Gbps speed, generate the digital video signal of output 1080i@50Hz, 1080i@59.94Hz, 1080i@60Hz, 720p@50Hz, 720p@59.94Hz and 720p@60Hz form; In the SD scope, generate the signal of output 480i and 576i form.

The signal mode that can select to export has 9 kinds: color bar signal, frequency signal, black burst, ill-condition matrix signal, brightness gradient signal, Y/C gamut ramp signal, SMPTE 75% bar shaped signal, SMPTERP219 bar shaped signal and bright pulse and bar shaped signal.

2. 3G-SDI high-definition digital video signal generation system according to claim 1, it is characterized in that, this system also is provided with USB interface (3), SD/MMC card (4) and synchronous DRAM (5), the user imports self-defining picture signal to FPGA (8) by USB interface (3) or SD/MMC card (4), FPGA (8) is by the internal algorithm of its IP kernel, the serial signal of input is changed into parallel signal and deposits among the SDRAM (5), SDRAM (5) is input to parallel signal among the FPGA (8) with two-forty, according to the internal algorithm of form in IP kernel of selecting with picture signal layout again, generate parallel digital signal, again with the frequency of oscillation of precision interval clock adjuster (2) modulation as clock frequency, control the transmission rate of output parallel digital video signal.

3. 3G-SDI high-definition digital video signal generation system according to claim 1 and 2 is characterized in that, embedded audio signal in described parallel digital signal.