KR20020062292A - Single horizontal scan range CRT monitor - Google Patents

Abstract

A single horizontal scanning range CRT monitor comprising: a receiver for receiving display signals in a digital format from an external source, first display signals having one of a plurality of input resolutions, and connected to the receiver and receiving the first display signals. Supplied to detect the input resolution of the first display signals and having the vertical output resolution selected from a plurality of different output resolutions that match the detected input resolutions of the first display signals. It includes a converter. All of the plurality of output resolutions have the same horizontal resolution, and all of the digital output signals have the same horizontal frequency.

Description

Single horizontal scan range CRT monitor

Background of the Invention

There is little standardization among personal computer (PC) manufacturers in the resolution and frequency of display signals generated by the display cards of PCs. In contrast, it is generally more complex and expensive to produce analog monitors that can adapt to multiple display signal frequencies. One such viable configuration is shown in FIG. 1. In this configuration, the PC 10 includes a display card (not shown) having a digital-to-analog (D / A) converter 12 to convert analog display signals at a frequency and resolution set by the PC to a CRT multiple scan frequency. Output to the monitor 14. The monitor 14 detects this frequency and adjusts its scanning frequency to match the frequency of the original display signals. This monitor is complex and expensive to implement.

Also, another viable monitor display configuration is shown in FIG. Again, the PC 10 comprises a display card (not shown) having a digital to analog (D / A) converter 12, which converts analog display signals at a frequency and resolution set by the PC to a single scanning frequency liquid crystal display device. (LCD) Outputs to the monitor 16. LCD monitor 16 includes an A / D converter 18 for converting the received analog signals into digital signals. A scaling engine 20 inside the LCD monitor 16 converts the digital display signals to a frequency and resolution compatible with the LCD monitor 16 and converts them to display circuitry (not shown) inside the LCD monitor 16. Supply. In this configuration, the A / D converter and the LCD panel are expensive.

Also, another viable configuration is shown in FIG. 3. In this configuration, the PC 10 includes a display card (not shown) having a digital-to-analog (D / A) converter 12 to monitor analog display signals at a frequency and resolution set by the PC in a single scan CRT monitor. It outputs to the A / D converter 24 of (22). The output of the A / D converter 24 is supplied to a scaling engine 26 which converts the digital display signals to a frequency and resolution compatible with the CRT monitor 22 and supplies them to the D / A converter 28. do. The analog output display signals of the D / A converter 28 are supplied to the monitor 22 for display at a frequency and resolution compatible with the monitor. This configuration also has the disadvantage of being complicated and expensive to manufacture.

Finally, in the viable configuration of FIG. 4, the PC 30 with the internal scaling engine 32 outputs digital display signals at a resolution and frequency compatible with the single scan LCD monitor 16. This configuration has the advantage of low cost, while the LCD panel is still expensive for general use in desktop PCs and the like.

What is needed for a single horizontal scanning range monitor is preferably a CRT monitor, which is not complicated to low cost manufacturing, and the monitor has display circuits that output display signals at various different scanning frequencies and display resolutions. Allow to be compatible with PCs.

FIELD OF THE INVENTION The present invention relates to computer monitors, and more particularly to a single horizontal scan range cathode ray tube (CRT) monitor for use in personal computers having different output display signal types.

1 is a block diagram of a first viable monitor configuration implementing a CRT monitor capable of multiple scan frequencies.

2 is a block diagram of a second viable monitor configuration implementing an LCD monitor incorporating an A / C converter and a scaling engine.

3 is a block diagram of a third executable monitor configuration implementing a CRT single scan monitor.

4 is a block diagram of a fourth viable monitor configuration implementing a scaling engine at a PC to supply digital output display signals to an LCD monitor.

5 shows a first embodiment of the present invention for implementing a digital interface video board in a PC that outputs digital display signals to a CRT single scan frequency monitor incorporating a digital display signal receiver, a memory, a scaling engine, and a D / A converter. Block diagram.

6 is a more detailed block diagram of the embodiment of FIG.

7 is a detailed block diagram of a variation of the embodiment of FIG.

8 is a timing diagram for use in explaining read and write operations to the frame memory of the embodiment of FIG.

9A and 9B are tables of conversion frequencies and resolutions performed by the present invention in two different embodiments.

10 is a block diagram of a second embodiment of the present invention.

This and other objects are achieved by the present invention of a single horizontal scanning range monitor that receives display signals in digital format from an external source such as a personal computer. The original display signals can have one of a plurality of input resolutions and scanning frequencies. The converter supplied with the original display signals detects a particular input resolution of the original display signals and matches them to a plurality of different scan frequencies that match the detected input resolution of the original display signals and the horizontal scan frequency such as the horizontal scan frequency of the monitor. Convert from output resolutions to digital output signals having a selected vertical output resolution.

Preferably, the monitor is a cathode ray tube (CRT) monitor. In some embodiments, the original display signals are converted into output signals having a single predetermined horizontal resolution regardless of the horizontal resolution of the original display signals. In one preferred embodiment, this converter is an integrated circuit chip.

The monitor includes a display data input to receive original display data. The display data input may be a receiver from which an external source transmits the first display data in digital format. In some preferred embodiments, the converter is a circuit comprising a frame memory. Display signal conversion is achieved by controlling the data writing and reading speeds into the frame memory. The converter is connected to a resolution detector that detects the resolution of the original display signals and outputs a resolution detection signal in addition to the frame memory, and a display data input, a frame memory and a monitor, writes the first display signals to the frame memory and And a first multiplexer that switches between reading the digital output signals to the monitor. The address counter controller controls the addresses at which data is written to and read from the frame memory. A vertical sync generator connected to the resolution detector generates a vertical sync pulse for the monitor at a selected one of a plurality of vertical sync frequencies as a function of the detected resolution of the original display signals. The horizontal sync generator generates horizontal sync pulses at the monitor's single horizontal scan frequency. The data output clock generator generates a data output clock signal according to the product of a single horizontal scan frequency and a multiplayer factor, such as the sum of the horizontal output resolution and the horizontal gap.

The second multiplexer receives the clock and vertical sync signals from the display data input. The second multiplexer is connected to an address counter, a data output clock signal generator and a horizontal synchronization generator, and the combination of the vertical synchronization signal and the clock from the display data input or the horizontal from the horizontal output generator and the data output clock signal from the data output clock generator. One of the combination of sync pulses is selectively supplied to an address counter controller. A sector controller writes the original display data to the frame memory simultaneously and alternately at the original resolutions and scan frequencies, and digitally from the frame memory to the monitor at scan frequencies compatible with the resolutions and monitor. The first multiplexer and the second multiplexer are controlled to read the output data signals.

In embodiments in which the converter belongs to the monitor, it is desirable to have the display signals transmitted to the monitor in digital form by the PC. The receiver is integrated as part of the display data input of the monitor and receives the digital display signals and sends them to the transducer. In preferred embodiments, the receiver comprises a transition minimized differential scaling (TMDS) receiver, a low voltage differential signaling (LVDS) receiver, a low voltage differential signaling display interface (LDI). interface) and a gigabit video interface (GVIF) receiver.

In one preferred embodiment where the receiver is a TMDS receiver, the clock from the receiver is a transition minimum differential scaling (TMDS) clock signal. The horizontal sync generator includes a phase locked loop (PLL) for generating a data output clock. In a preferred embodiment, the horizontal sync generator generates horizontal sync pulses at a frequency of 80 kHz. The vertical sync generator generates vertical sync pulses at a selected one of frequencies of 79.9 Hz, 95.1 Hz, 124.8 Hz, 98.9 Hz, 88.4 Hz and 75.1 Hz in accordance with the resolution detection signal.

Some of the transducers of the preferred embodiments described above, in particular said transducers in which the transducer is an integrated circuit,

Input Converted fH (kHz) fV (Hz) Clock (MHz)

640 × 480 1400 × 960 80 79.9 151.68

720 × 400 1400 × 800 80 95.1 151.68

800 × 600 1400 × 600 80 124.8 151.68

1024 × 768 1400 × 768 80 98.9 151.68

1152 × 864 1400 × 864 80 88.4 151.68

1280 × 1024 1400 × 1024 80 75.1 151.68

To change the resolution of the original display signals

Where "Input" is the resolution of the first display signals in the pixels, "Converted" is the resolution of the display output signals in the pixels, "fH" is the horizontal frequency of the display output signals at kHz, and "fV (Hz) "is the vertical synchronization frequency of the display output signals, and" Clock "(calculated by fH x (horizontal resolution) x (constant)) is the data output clock at MHz. In these examples, the constant is approximately 1.35.

In still other embodiments, the conversion of the resolutions of the original display signals is shown in the following table,

Input Converted fH (kHz) fV (Hz) Clock (MHz)

640 × 480 1280 × 960 80 79.9 138.24

720 × 400 720 × 800 80 95.1 78.08

800 × 600 800 × 600 80 124.8 87.04

1024 × 768 1024 × 768 80 98.9 111.36

1152 × 864 1152 × 864 80 88.4 125.44

1280 × 1024 1280 × 1024 80 75.1 138.24

According to

Here, the constant for calculating the clock is approximately 1.36.

The invention also encompasses methods implemented with processing steps executed by the elements of the single horizontal scanning range monitors described above.

The above and other objects, features and advantages of the present invention will be more readily understood upon consideration of the following detailed description of certain preferred embodiments of the present invention.

Now, particularly in FIG. 5, a first embodiment of the present invention includes a PC 36 having a digital video interface board 38 that acts as a digital display data transmitter. The transmitter can be any one of a transition minimum differential scaling (TMDS) transmitter, a low voltage differential signal transmission (LVDS) transmitter, a low voltage differential signal transmission display interface (LDI) transmitter or a gigabit video interface (GVIF) transmitter. The PC 36 outputs digital display data according to the format of the transmitter for resolutions such as fH and fV. In a preferred embodiment, the transmitter transmits encoded RGB video display data and is a TMDS transmitter manufactured by Genesis Microchip Inc.

The digital data in the PC 36 is supplied to the CRT single scan frequency monitor 22 by cable connection or the like. In the CRT monitor 22, the input display data output by the PC 36 is received at the receiver 40 corresponding to the transmitter 38, and the receiver 40 has a corresponding TMDS, LVDS, LDI or GVIF. Receiver. In this example, the TMDS receiver is manufactured from Silicon Image's model number Sil151. Receiver 40 outputs the received digital display data to scaling engine 42 in CRT monitor 22.

The scaling engine 42 converts the digital display signals output by the PC 36 and received by the receiver 40. Such conversion may be in accordance with the condition of FIG. 9A. For example, for display signals with original resolution of 640 × 480 pixels, scaling engine 42 may have 1400 × 960 pixels at horizontal scan frequency fH of 80 kHz and vertical scan frequency fV of 79.9 Hz. Output digital display signals with a resolution of The data output clock is at a frequency of 151.68 MHz. On the other hand, if the original resolution of the display signals is 1024 x 768 pixels, the scaling engine 42 converts these signals into digital display signals having a resolution of 1400 x 768 pixels, 80 kHz fH and 98.9 MHz fV. Let's do it. In this embodiment, the horizontal resolution of the output digital display signals is invariant 1400 pixels regardless of the horizontal resolution of the initial display data.

The scaling engine 42 is an integrated chip of the type described in US Pat. No. 5,602,599 and manufactured by 1999 Concourse Dr., San Jose CA 95131 as gmZ1, gmZ2, gmZ3, gmZd1, or gmZR × 1 models from Genesis Microchip Inc. It can be implemented in In addition, scaling engine 42 may be a specially programmed microcomputer.

Scaling engine 42 uses either on-board memory or memory 44 in CRT 22 to make the conversion. The memory may be dynamic random access memory (DRAM). The digital display signal output from the scaling engine 42 is converted by a D / A converter (actually separate D / A converters for each color) and displayed on a single scan CRT 22.

Now, particularly in FIG. 6, the preferred version shows the embodiment of FIG. 5 in more detail. In this preferred version, the PC 36 has a digital video interface board 38 which is a TMDS transmitter 48. The digital RGB signals in TMDS format are supplied via a cable or the like connected to the TMDS receiver 50 in the CRT monitor 22. One suitable receiver would be the model gmZR × 1 from Genesis Microchip Inc. TMDS receiver 50 outputs the initial display signals to scaling chip 44 as 8-bit digital RGB signals. Inside the scaling chip 44 is a microprocessor 52 that provides calculation results for the necessary timing signals and scaling functions.

Scaling chip 44 writes digital display data to frame memory 42 having separate memory planes for RGB signals. Each memory plane holds, for example, 1024 x 768 8-bit color "words" as resolution conversion is performed. Output digital display data from the scaling engine 44 in the form of an 8-bit color word for the respective RGB signals is output to each of the separate D / A converters 46R, 46G and 46B at the converted resolution according to the table of FIG. 9A. Supplied. RGB analog output display signals from the D / A converters 46R, 46G and 46B are supplied to the monitor 22 for display.

Now, particularly in FIG. 7, another embodiment of the present invention will be described. Components in the above-described embodiments usually have the same reference signs, and their operation is not described in more detail. In this embodiment, a discrete circuit replaces the scaling chip 44. The 8-bit RGB signals output from the TMDS receiver 50 are supplied to the first select switch 54. The selector switch selectively connects the respective digital RGB signals to either the input / output (I / O) terminals of the first dynamic RAM (DRAM) 58 or the I / O terminals of the second DRAM 60. . DRAMs 58 and 60 constitute a frame memory. The second select switch 56 consists of separate D / A converters 46R, 46G and 46B for the I / O terminals of the DRAMs 58 and 60 and supplies analog display signals to the monitor 22. Is connected to the D / A converter 46.

The TMDS receiver also outputs the horizontal synchronizing signal H.SYNC, the vertical synchronizing signal V.SYNC, and the TMDS clock signal TMDS CLK. The H.SYNC signal is supplied to the third select switch 68 in accordance with the TMDS CLK signal. V.SYNC is also supplied to the sector controller 72. The switch 68 alternately supplies V.SYNC to the input of either the first address counter controller 64 or the second address counter controller 66. do. The switch 68 also supplies TMDS CLK simultaneously and alternately to the other input of the first address counter controller 64 or the other input of the second address counter controller 66.

The address counter controllers 64 and 66 are connected to address lines of the DRAMs 58 and 60, respectively, so that display data controls the addresses stored in and read from the DRAMs 58 and 60. Also connected to the address counter controllers 64 and 66 is the fourth selector switch 70. The horizontal sync generator 78 includes a monitor 22, a phase locked loop (PLL) circuit 74, a D / A converter 46, a vertical sync generator 80, a sector controller 72, and a fourth selector switch 70. Generate 80 kHz ("fH") H.SYNC signals. The PLL 74 receives the H.SYNC signal having the horizontal scanning frequency fH and outputs a data output clock signal Read CLK having the same frequency as the product of fH and the multiplayer factor from the resolution multiplexer circuit 76. . The multiplayer factor is equal to the sum of the display output signals and the horizontal resolution and horizontal spacing. In this example, Read CLK = fH × (horizontal resolution) × (constant). Read CLK is supplied to switch 70 and D / A converter 46. Note that the vertical sync generator 80 is supplied to the output of the resolution detector 62. The vertical sync generator 80 changes the frequency fV of its output V.SYNC signal to the monitor 22 according to the detected resolution of the original display signals, as shown in FIG. 9B.

Sector controller 72 controls the operations of switches 54, 56, 68, and 70. In operation, switches 54 and 56 operate simultaneously as a first multiplexer, whereby select switch 54 is connected to supply input display signals to be written to DRAM 58, and switch 56 is a D / A converter. Via 46 is connected to read the stored display signals from DRAM 60 to monitor 22. The switches 68 and 70 constitute a second multiplexer, and the sector controller 72 controls the switches 68 and 70 to actuate the switches 54 and 56 at the same time so that the switch 54 is The display data is connected to write the DRAM 58, the switch 56 is connected to read the display data from the DRAM 60, and the switch 68 is connected to the TMDS CLK signal and the V.SYNC from the TMDS receiver 50. Is connected to supply a signal to the address counter controller 64. At the same time, sector controller 72 causes switch 70 to supply Read CLK signal from PLL 74 and H. SYNC signal from horizontal sync generator 78 to address counter controller 66.

The sector controller 72 also switches switches 54, 56, 64 and 66 to change connections to be connected to either one of the two DRAMs 58 and 60 and the address counter controllers 64 and 66, respectively. To control. In this manner, the first set of received digital display data from receiver 50 is written to DRAM 58 at one resolution and set of frequencies, and the second set of received digital display data is at a different resolution and frequency. Is read from DRAM 60 in the set of bits. The process then reverses by causing switches 54, 56, 68, and 70 to simultaneously change their connections to either of the two DRAMs 58 or 60, so that the first set of display data is converted to resolution and frequency. Are read from DRAM 58 and a third set of received display data from TMDS receiver 50 is stored in DRAM 60.

Now, particularly in FIG. 8, the timing of the processing for writing to and reading from the DRAMs 58 and 60 is described in more detail. As shown in the figure, the writing of received input display data from the receiver 50 to the frame memory DRAMs 58 and 60 is controlled by a 60 Hz V.SYNC signal from the receiver 50. In the figure, this is indicated by the first “input” period 82 for the DRAM 56. Reading of data from the DRAMs 58 and 60 to the monitor 22 is synchronized with the 98.9 Hz V.SYNC signal from the V.SYNC generator 80. This is indicated by the output period 84 when display data is read from the DRAM 60. Next, the display data stored in the DRAM 58 is read in the cycle 86. It can be seen herein that certain fH and fV values are merely examples.

All display data stored in one of the DRAMs 58 or 60 can be read in two 98.9 Hz V.SYNC periods, but the write time to the DRAMs is shorter in duration. Note that the duration of the output period 84 exceeds the duration of the input period 82. Since the data write and data read cycles are not the same in duration, the period of the first data write / read cycle may then overlap the read and write operations to the same memory. For example, all of the display data can be read from one of the DRAMs before all the data is input to the other DRAM. In this case, the DRAM to be read is simply read back, so that the same data is reproduced again. This is shown in time periods 90 and 92.

After period 86, for example, display data is read from DRAM 60 for the first two of three consecutive 98.9 Hz V.SYNC periods during period 90. Since the DRAM 58 is written at the V.SYNC timing from the receiver 50, the writing of the received display data to the DRAM 58 requires that at least two 98.9 Hz V.SYNC cycles are from the beginning of the period 90. It did not complete until elapsed. That is, all display data has been read out from the DRAM 60 before the process of writing the data into the DRAM 58 is completed during the period 92. Therefore, the DRAM 58 is not prepared to be read at this time. Therefore, display data once read from DRAM 60 during period 90 of the first portion is read back at the last 98.9 Hz V.SYNC interval 94 of period 90. The observer of the monitor 22 does not notice the same display data being repeated. Thereafter, display data is read from the DRAM 58. This process is then repeated for every display data read / write cycle.

In the embodiment described above, the scaling engine belongs to the monitor. However, in another embodiment, the scaling engine may belong to a PC. Now, particularly in FIG. 10, a second embodiment of the present invention includes a PC 30 incorporating a scaling engine 34. The scaling engine 34 performs the same conversion of the digital display signals output in the PC 30 and outputs the converted digital display signals to the D / A converter 928 of the single horizontal scanning frequency CRT monitor 22 for display. . This conversion may be in accordance with the conditions of FIG. 9A. The horizontal scan frequency of the monitor 22 is fH, which is 80 kHz in the preferred embodiments described herein. Scaling engine 34 is also described in US Pat. No. 5,602,599 and is of an integrated type manufactured by 1999 Concourse Dr., San Jose CA 95131 as gmZ1, gmZ2, gmZ3, gmZd1, or gmZR × 1 models from Genesis Microchip Inc. It can be implemented in a chip. In addition, scaling engine 34 may be a specially programmed microprocessor. In addition, the scaling engine 34 may have the same structure as the circuit of FIG. 7 in which the TMDS receiver 50 is replaced by the display adapter of the PC 30. In this embodiment, this transformation is in accordance with FIG. 9B.

The above description is a single horizontal scan range CRT monitor that allows a single scan CRT to interface economically and conveniently with PCs having different digital display outputs.

While the invention has been shown and described with respect to preferred embodiments, it is to be understood that various changes and modifications are within the spirit and scope of the invention as claimed. Any structure, material or act that performs functions in coordination with the corresponding claimed elements in all means or steps and corresponding structures, materials, acts and equivalents and functional elements of the claims below. Include them.

Claims (43)

In a single horizontal scan range monitor supplied with the first display signals in digital format from an external source, The first display signals have one of a plurality of input resolutions, Cathode ray tube (CRT) display with a single horizontal scanning frequency, and Receiving the original display signals, detecting an input resolution of the first display signals, and applying the first display signals to the detected input resolution of the first display signals and the single horizontal scanning frequency of the CRT display. And a converter for converting from a plurality of matched different output resolutions into digital output signals having different vertical output resolutions selected and for supplying the digital output signals to the CRT display. The method of claim 1, And the transducer comprises a frame memory. The method of claim 1, The external source transmits the original display signals in a digital format and the monitor comprises a receiver to receive the original display signals and to supply them to the transducer. The method of claim 3, wherein And the receiver is a transition minimum differential scaling (TMDS) receiver. The method of claim 3, wherein And the receiver is a low voltage differential signal transmission (LVDS) receiver. The method of claim 3, wherein And the receiver is a low voltage differential signal transmission display interface (LDI) receiver. The method of claim 3, wherein And the receiver is a gigabit video interface (GVIF) receiver. The method of claim 1, And a digital to analog converter for converting the digital output signals into corresponding analog output signals. The method of claim 8, The original display signals and the digital output signals have corresponding red, green and blue components, Wherein the digital to analog converter has separate converters for each color component. The method of claim 1, And the converter converts the original digital display signals into digital output signals having one predetermined horizontal resolution irrespective of the horizontal resolution of the first digital display signals. The method of claim 1, The transducer is shown in the following table, namely Input Converted fH (kHz) fV (Hz) Clock (MHz) 640 × 480 1400 × 960 80 79.9 151.68 720 × 400 1400 × 800 80 95.1 151.68 800 × 600 1400 × 600 80 124.8 151.68 1024 × 768 1400 × 768 80 98.9 151.68 1152 × 864 1400 × 864 80 88.4 151.68 1280 × 1024 1400 × 1024 80 75.1 151.68 A scaling circuit for converting the resolution of the original display signals according to: Where "Input" is the resolution of the original display signals in pixels, "Converted" is the resolution of the display output signals in pixels, and "fH" is the horizontal frequency of the display output signals at kHz wherein "fV (Hz)" is the vertical sync frequency of the display output signals and "Clock" is the data output clock at MHz. In the single horizontal scanning range monitor, Display with a single horizontal scanning frequency, A display data input having one of a plurality of input resolutions, a clock signal, a horizontal synchronizing signal and a vertical synchronizing signal and receiving first display signals in digital format from an external source, and Receiving the first display signals and the horizontal synchronizing signal and the vertical synchronizing signal from the display data input, detecting the input resolution of the first display signals, and receiving the first display signals of the first display signals. A converter for converting the detected input resolution and a plurality of different output resolutions matching the single horizontal scanning frequency of the display into digital display output signals having a selected vertical output resolution, The converter, Frame memory, A resolution detector for detecting the resolution of the first display signals and outputting a resolution detection signal, A device connected to the display data input, the frame memory, and the display, for switching between writing the first display signals in the frame memory and reading the digital display output signals from the frame memory to the display. 1 multiplexer, An address counter controller for controlling addresses at which data is written to and read from the frame memory, A vertical sync generator coupled to the resolution detector and generating a vertical sync pulse at a selected one of a plurality of vertical sync frequencies as a function of the detected resolution of the first display signals, A horizontal sync generator for generating a horizontal sync pulse at the single horizontal scan frequency, A data output clock generator for generating a data output clock signal as a function of said single horizontal scan frequency and said horizontal resolution of said digital display output signals, The vertical synchronizing signal from the display data input connected between the clock output terminal of the display data input, the vertical synchronizing signal output of the display data input, the address counter, the data output clock signal generator, and the horizontal synchronizing generator; And a second multiplexer for selectively supplying either the combination of the clock or the combination of the data output clock signal from the data output clock generator and the horizontal synchronization pulse from the horizontal sync generator to the address counter controller; Simultaneously and alternately, the original display data is written to the frame memory at the original resolution and scan frequencies, and the scan frequency differs from the resolutions and frequencies of the original display data and matches the requirements of the display. And a sector controller controlling the first multiplexer and the second multiplexer to read the digital output data signals from the frame memory to the display. The method of claim 12, And the transducer belongs to the monitor. The method of claim 12, The transducer belongs to the external source. The method of claim 12, Wherein the display is a cathode ray tube (CRT). The method of claim 12, Wherein said sector controller is supplied with said vertical sync signal from said display data input and said horizontal sync pulse from said horizontal sync generator. The method of claim 12, And the resolution detector receives the horizontal sync signal and the vertical sync signal from the display data input. The method of claim 12, The external source includes a transmitter for transmitting the original display signals in the digital format and the display data input includes a receiver for receiving the original display signals and feeding them to the transducer monitor. The method of claim 18, And the receiver outputs a transition minimum differential scaling (TMDS) clock signal to the clock output terminal of a display data input. The method of claim 12, And the frame memory includes at least two memory banks that are alternately written and read, and a pair of address controllers that control the reading and writing of data in the memory banks. The method of claim 12, The data output clock generator includes a phase locked loop (PLL) circuit that is supplied with the horizontal sync pulse and a multiplayer factor that is a function of the single predetermined horizontal resolution, And the data output clock generator generates the data output clock at a frequency equal to the product of the single horizontal scan frequency and the multiplayer factor. The method of claim 12, And the horizontal sync generator generates horizontal sync pulses at a frequency of 80 kHz. The method of claim 12, And the vertical sync generator generates vertical sync pulses at a selected one of frequencies of 79.9 Hz, 95.1 Hz, 124.8 Hz, 98.9 Hz, 88.4 Hz and 75.1 Hz in accordance with the resolution detection signal. The method of claim 12, The transducer is shown in the following table, i.e. Input Converted fH (kHz) fV (Hz) Clock (MHz) 640 × 480 1280 × 960 80 79.9 138.24 720 × 400 720 × 800 80 95.1 78.08 800 × 600 800 × 600 80 124.8 87.04 1024 × 768 1024 × 768 80 98.9 111.36 1152 × 864 1152 × 864 80 88.4 125.44 1280 × 1024 1280 × 1024 80 75.1 138.24 Converts the resolution of the original display signals according to Where "Input" is the resolution of the original display signals in pixels, "Converted" is the resolution of the display output signals in pixels, and "fH" is the horizontal frequency of the display output signals at kHz wherein "fV (Hz)" is the vertical sync frequency of the display output signals and "Clock" is the data output clock at MHz. A method for adapting a single horizontal scanning range monitor having a single horizontal scanning frequency to receive and display original display signals generated by a digital type computer having one of a plurality of input resolutions, the method comprising: Detecting the input resolution of the original display signals, Converting the first display signals into digital output signals having a vertical output resolution selected from the plurality of different output resolutions that match the detected input resolution and the single horizontal scan frequency of the first display signals; Supplying the digital output signals to the monitor for display. The method of claim 25, The converting step includes converting the original display signals into digital output signals having a single predetermined horizontal resolution irrespective of the horizontal resolution of the original display signals. Way. The method of claim 25, And said converting comprises writing to and reading from frame memory. The method of claim 25, Receiving the original display signals from the computer. The method of claim 28, And said receiving comprises transition minimum differential scaling (TMDS). The method of claim 28, And the receiving step comprises a low voltage differential signal transmission (LVDS) step. The method of claim 28, And said receiving comprises a low voltage differential signal transmission display interfacing (LDI) step. The method of claim 28, And said receiving comprises a gigabit video interfacing (GVIF) step. The method of claim 25, And digital to analog converting the digital output signals into corresponding analog output signals. The method of claim 27, The original display signals and the digital output signals have corresponding red, green, and blue components, and the digital to analog conversion includes a separate digital to analog to convert each color component. Range monitor adaptation method. The method of claim 25, The converting step is described in the following table, that is, Input Converted fH (kHz) fV (Hz) Clock (MHz) 640 × 480 1400 × 960 80 79.9 151.68 720 × 400 1400 × 800 80 95.1 151.68 800 × 600 1400 × 600 80 124.8 151.68 1024 × 768 1400 × 768 80 98.9 151.68 1152 × 864 1400 × 864 80 88.4 151.68 1280 × 1024 1400 × 1024 80 75.1 151.68 A scaling step of converting the resolution of the original display signals according to: Where "Input" is the resolution of the original display signals in pixels, "Converted" is the resolution of the display output signals in pixels, and "fH" is the horizontal frequency of the display output signals at kHz wherein "fV (Hz)" is the vertical synchronization frequency of the display output signals and "Clock" is the data output clock at MHz. A method for adapting a single horizontal scanning range monitor having a single horizontal scanning frequency to receive and display original display signals generated by a digital type computer having one of a plurality of input resolutions, the method comprising: Receiving the first display signals, then outputting the first display signals to one of the plurality of input resolutions, and additionally outputting a clock signal, a horizontal sync signal, and a vertical sync signal; Detecting the input resolution of the original display signals, A digital output having an output vertical resolution selected from said detected display resolution of said first display signals, a single predetermined horizontal resolution and a plurality of different output resolutions matching said single horizontal scanning frequency; Converting them into signals, Supplying the digital output signals to the monitor, The converting step, Alternately writing the first display signals to a frame memory and reading the digital output signals from the frame memory, Controlling the addresses where data is written to and read from the frame memory by an address counter controller, Generating a vertical sync pulse at a selected one of a plurality of vertical sync frequencies compatible with the monitor as a function of the detected resolution of the first display signals, Generating a horizontal sync pulse at the single horizontal scan frequency, Generating a data output clock, and Either the combination of the vertical synchronization signal and the clock from the first display data generation step or the combination of the data output clock from the data output clock generation step and the horizontal synchronization pulse from the horizontal synchronization pulse generation step is used for the address counter. Selectively supplying to the controller, wherein the address counter controller writes the first display data to the frame memory simultaneously and alternately, and reads the digital output data signals from the frame memory to the monitor. And a horizontal horizontal scanning range monitor adaptation method. The method of claim 36, And the monitor is a cathode ray tube (CRT) monitor. The method of claim 36, And the clock from the receiving step is a transition minimum differential scaling (TIMS) clock signal. The method of claim 36, And the frame memory comprises at least two memory banks that are alternately written and read. The method of claim 36, Generating a data output clock using a phase locked loop (PLL) in accordance with the product of the horizontal sync and multiplayer factors corresponding to the sum of the desired horizontal resolution and horizontal blank spacing. How to monitor. The method of claim 36, And said generating horizontal sync step generates horizontal sync pulses at a frequency of 80 kHz. The method of claim 36, The vertical synchronization generating step generates vertical synchronization pulses at a selected one of frequencies of 79.9 Hz, 95.1 Hz, 124.8 Hz, 98.9 Hz, 88.4 Hz and 75.1 Hz in accordance with the resolution detection signal. . The method of claim 36, The converting step is described in the following table, that is, Input Converted fH (kHz) fV (Hz) Clock (MHz) 640 × 480 1280 × 960 80 79.9 138.24 720 × 400 720 × 800 80 95.1 78.08 800 × 600 800 × 600 80 124.8 87.04 1024 × 768 1024 × 768 80 98.9 111.36 1152 × 864 1152 × 864 80 88.4 125.44 1280 × 1024 1280 × 1024 80 75.1 138.24 Converts the resolution of the original display signals according to Where "Input" is the resolution of the original display signals in pixels, "Converted" is the resolution of the display output signals in pixels, and "fH" is the horizontal frequency of the display output signals at kHz wherein "fV (Hz)" is the vertical sync frequency of the display output signals and "Clock" is the data output clock at MHz.