JPH07503327A - Analog video interface for digital video display - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] for digital video display analog video interface The present invention provides at least one analog signal with composite or separate horizontal and vertical deflection signals. an analog video input for receiving an analog video signal; Digitization means for digitizing log video signals and desired video frequency generate a basic clock signal having a frequency at least n times (where n≧1) and a control signal for digital display in synchronization with the basic tarok signal. a sampling clock signal for the digitizing means; and a means for generating a sampling clock signal for the digitizing means. Equipped with an analog video interface for digital video display devices. related.

For example, a computer graphics display with a VGA display adapter The system typically uses monochrome or color shade controlled by an analog video signal. Use polar ray tube displays (analog voltage varies the brightness of pixels of various colors) directly). Most laptop computers have LCD displays. Display (LCD) panel is used. Some of the desktop computers (PS) In special models, the CRT display can be replaced with a digital LCD, plasma or electronic Efforts have been made to replace them with chromoluminescent (EL) panels.

A digital display panel requires a number of control signal lines to transfer the color information to the screen. Requires parallel digital control, which means that the amount increases. Fray Fraction rate control (FRC) and dithering are achieved by processing image information into pulses. , the same effect can be achieved with fewer control signals (i.e., without increasing the number of signal lines). aim to achieve. These techniques typically produce flickering in the image. make you feel the same A very large number of lines are connected to the so-called flat wires inside the laptop computer. Although the display panel can be easily installed using cables, located in a separate housing in the top computer, and the image information is Transferred to the display panel through a separate external video cable. As the number of signal lines increases When using a video cable, it becomes stiffer, takes up more space, and This is a major inconvenience in use. In addition, various display panels have signal lines or Different control and timing signals require different interfaces to operate. do. This requires the use of different cables for different display panels.

In addition, the positioning of the image on the screen changes from panel to panel, making it difficult for proper operation. Requires various timings. Different panels support different numbers of colors However, they are also mutually exclusive in this regard (see number of digital signal lines). Additionally, the bidet The cable's digital signal does not easily interfere with the environment (RFI, EMI, EMC). Ru.

The digital signal in a digital display panel is a traditional analog video interface. Requires a non-standard display adapter with an incompatible interface shall be. Currently, display adapters that support digital display panels The circuits are not produced on a large scale and for this reason they only support analog cathode ray tubes. more expensive than mass-produced circuits.

As you can see from the above, more than digital LCD, plasma, or EL display. Widely used for control signals, interfaces and displays that support them Adapters are used in opposition to each other and especially in most computer equipment. established standards of practice and related interfaces (such as VGA) Very limited by the fact that it goes against traditional display adapters. subordinate For example, VG via an analog video interface compliant with this standard. A display adapter allows you to control the digital display panel There is a need for equipment. This also digitizes the analog video signal and An interface device uses a digital interface to generate control signals for the display panel. shall be provided in conjunction with the display panel. but, This involves several major issues.

EP 0 269 199 A has a constant basic clock frequency generated locally. An LCD display is disclosed. This basic tarok frequency is the desired video frequency. It is a multiple of the wave number. It is then synchronized with the incoming horizontal sync signal and the base clock. A control pulse is provided. The sampling clock is a pulse that controls the basic clock. is obtained by dividing by

However, in order to operate properly, digital display panels must be compatible with analog video signals. Requires a properly and accurately phased clock signal, otherwise the screen Flickering easily occurs in the displayed image. Similarly, sample The video frequency should always be as close as possible to the video frequency of your display adapter. Must be close. For example, the video frequency of a VGA display adapter Although the wavenumbers have values that comply with the standards of practice, they are always correct in the adapter. is not observed exactly and, as a result, the entire image area of the digital display panel is required. It is very difficult to maintain proper synchronization. In addition, a display adapter The video frequency is not constant, but moves within relatively narrow limits. this Therefore, the display of EP 0 269 199 A is Does not guarantee high image quality because the video frequencies of the play are substantially different from each other . One easy solution to the problem is to run the cable directly from the display adapter. It supplies a lock signal when necessary. However, such compatible discs This is because the play adapter cable connection does not contain video control signals. Creates incompatibility with display adapters that comply with implementation standards. In addition, 2 When a high frequency clock signal of 5-30MHz is transmitted through the video cable , interface problems easily occur.

It is an object of the present invention to enable high quality flicker-free images in digital display panels. while maintaining the desired wide range (analog display adapter and cable used). Analog video interface for digital display devices compatible with blue linkage The goal is to provide a

This allows the display to further analyze based on the received signal. means for determining a real video frequency of a log video signal; Synthesize a basic clock with a frequency that is at least n times (where n≧1) the external frequency a base comprising programmable frequency synthesizer means responsive to said determining means to and means for generating a clock signal. Analog video input for digital video display in the formats listed This is accomplished through interfaces.

In the present invention, the composite lock signal is a constant clock signal of the digital display panel. is used in place of the sampling clock, so that the frequency of the synthesized R-lock signal is The wave number is adjusted by the actual video frequency of the received video signal. sufficient accuracy In order to determine the real video frequency of the received video signal at The interface determines the duration of the received horizontal or vertical deflection period and each particular display resolution. Video based on video clock period (pixels) in deflection period relative to degree Calculate the frequency. Preferably, the base has a frequency that is a multiple of the real video frequency. This clock is synthesized based on the calculated real video frequency and All control signals for the operating clock and digital display are based on the base clock frequency. derived from the number. The inventor has created a screen that is stable and free of interference (pixel flickering). In order to acquire images (without curling), the sampling clock period is thicker than 1/4 of the clock period (video clock period of the received analog video signal) The fundamental clock frequency (n =4) is particularly convenient.

In addition, the sampling point must always coincide with the stable part of the video signal. To prevent quantization errors and provide a stable flicker-free image on the screen.

If the sampling time matches the change time of the video signal, flickering or The correct image information appears on the screen. With this method, the sampling clock and all display control signals are synchronized with the received video signal with sufficient accuracy. Digi The sampling clock and video clock of the digital display are based on, for example, 4. It is easily obtained by dividing this clock frequency. Correspondingly, display and Other possible control signals and horizontal and vertical deflection signals required by the pulses are: each contains a number of basic clock periods determined by register parameters formed by software. Therefore, the video interface according to the present invention The display adapter (video signal) and the requirements of the digital display used. make it possible to adjust The generated horizontal deflection signal is included in the horizontal deflection period (sync pulse). By increasing or decreasing the number of basic clock periods, the received horizontal deflection signal It is easy to synchronize instantly with Two short horizontal sync pulses during each horizontal deflection period interlaced scanning is made easier on digital displays by generating It will be held on. Correspondingly, when the display adapter is in character mode, the image is By generating more than one horizontal sync pulse during some of the horizontal sync periods, Stretched in the orthogonal direction, thus creating additional empty lines between character lines. Ru. Additionally, display adapters typically have 720 pixels per horizontal line. In character mode, the video signal is By omitting the corresponding video clock pulse of the digital display, Acceptable by digital display panel with 640 pixels per horizontal line As a result, every ninth pixel of the video signal is not displayed on the screen. stomach.

In the video interface according to the invention, the brightness is digitized by a voltage digitize the video signal while keeping the size of the range unchanged. By changing or controlling the operation of the background light inverter on the screen Adjustments will be made. The digitization limit is changed to adjust the contrast. , the lower limit is kept constant. In addition, the characteristics of the digital video display being controlled Brightness, contrast, color and/or word length corrections as required by gender can be decoded almost arbitrarily by means of an indexed conversion memory provided after the digitization means. This is done on digitized video data.

The video interface according to the invention allows a variety of digital monochrome and Color display panels (LCD, TFT LCD, EL) comply with implementation standards Analog interface and standard VGA adapter and other analog displays adapter (8514/A, XGA, multimedia adapter, etc.) interfaced with a standard video cable. video interface by invention The interface is thus independent of the display adapter (and independent of the resolution). (almost independent), and 640 pixel display mode only (,720 pixel display mode) Provides compatibility with cell character mode. Due to its internal digital linkage, The interface is designed specifically for each manufacturer's display panel. In addition, convert For memory purposes, contrast and brightness may be adjusted specifically for each user or application. Adjusted by the software, and the color scale of the display panel can be adjusted by various The color scale is corrected for the panel (gamma correction) or the color scale is set by the user. Set.

The invention will now be described in more detail by means of exemplary embodiments with reference to the accompanying drawings. be done.

FIG. 1 shows a computer table to which a video interface according to the present invention can be applied. 1 is a block diagram showing a display system.

Figure 2 shows how the horizontal and vertical synchronization signals of a video signal position the image on the screen. The screen of the video display device is shown showing the installation.

FIG. 3 is a plot diagram illustrating an analog video interface according to the present invention. Ru.

FIG. 4 is a block diagram showing the control unit of FIG. 3.

FIG. 5 is a timing diagram illustrating sampling of an analog video signal.

6, 7 and 8 are timing diagrams illustrating synchronization of horizontal deflection signals.

FIG. 9 is a timing diagram illustrating pixel removal in character mode.

Figures 10 and 11 show non-interlaced and interlaced display models, respectively. FIG. 3 is a timing diagram showing the generation of horizontal synchronization pulses in a mode.

FIG. 12 is a timing diagram showing image enlargement.

FIG. 13 is a block diagram illustrating the use of FRC circuitry to control a color panel. It is.

Figure 14 shows a monochrome display with intermediate memory divided into two blocks. FIG. 3 is a block diagram used for control.

The present invention is applicable to the control of display devices that can be controlled by digital video signals. be done. Such display devices include, for example, liquid crystal displays and plasma displays. rays, electroluminescent displays, etc.

FIG. 1 shows a computer system to which the invention is applied. computer system The system is a personal computer to which a keyboard 3, a mouse 4, and a display device 2 are connected. Equipped with a computer 1 (PC). PCI consists of several physical signals and includes a display device that generates a video signal that is applied to the display device 2 through a cable 5; Includes adapter.

Figure 2 shows the deflection or control signals for the video signal and the image on the screen of the cathode ray tube. This shows the influence on the positioning of Horizontal line or horizontal deflection period HPER is -horizontal line is scanned across the screen from left to right until the start of the next horizontal line. H.P.E. R is the active display period HAC defining the active image area 21 on the screen. τ+vt, at least front porch HFP, horizontal synchronization pulse H8YNC and A blanking period HBLANK is provided with a back porch HBP. Next The electron beam glue trace to the start of the line during the blanking period HBLANK arise. Correspondingly, the image or vertical deflection period VPER is equal to the display period VACTIVE. , at least front porch VFP, vertical sync pulse VSYNC and back porch A blanking period VBLANK including VBP is provided. All of the above for vertical deflection All control periods are formed from multiple horizontal deflection periods HPER, the number of multiples being As mentioned, the programmable control parameters determine in each particular case. Ru.

Holding of display periods HActtvt and VAct+vt regarding periods HPER and VPER The duration typically determines the width and height of the displayed image, ie, the image size. Each Display period HA (TIVE and V ACTIVE synchronization pulse H3YNC and The position of VSYNC determines the position of the image in the horizontal and vertical directions.

Video frequency is the video dot clock, i.e. the frequency of the video clock. means that - the video clock period displays - pixels on the screen This is the time needed to do so. The resolution is the period HAcr+vt in the horizontal direction the number of video periods in the vertical direction and the number of periods HPER in the period VACTIVE It is.

In most of the latest personal computers (IBM PC compatible, etc.), VGA (Video Graphics Array) display adapter is the above-mentioned EGAS Replaced CGASMDA and HGC display adapters. By invention The video interface actually applies to any display adapter. However, VGA adapters and the latest adapters (XGA, 8514/A, etc.) It is interesting to consider the compatibility acquired by the invention, and therefore the invention It is described below by using it as an example.

Figure 3 shows an output for coupling a digital LCD display panel to an analog video signal. The interface device according to the invention is shown. The principle of the device is to receive analog video signals It also digitizes in real time and generates the appropriate timing signals for the display panel. As a result, the digitized video signal is transferred in serial form to the electronics of the display panel. be done. The video interface according to the invention enables standard practice VGA display. All play adapter display modes are compatible with the analog CRT display shown in Figure 2. The same is done by a digital LCD panel, as in the display screen. . Compatible VGA display adapters typically support 720x400 resolution characters. mode and 640x480 resolution graphics mode (the most widely used VG A display mode) can be generated.

The device of FIG. 3 is divided into several blocks based on functionality. these bro The rack includes an analog video manual 31, a CPU micro adapter 32, and a communication channel. interface circuit 33, EEPROM memory 34, control circuit 35, A/D Conversion circuit 36, conversion memory 37, output, sofa 38, and LC display panel It is 39.

Video power 31 shall be coupled to a standard practice VGA display adapter The video interface of the VGA adapter is primarily intended for video transfer. The signals in Table 1 are used for this purpose.

Table 1 VGA Display Adapter Signal Interface Signal Name Description 1. Analog control signal for R red. Used only on color display devices.

2 G Analog control signal for green or monochrome level. Monochrome level system control is used only on monochrome displays.

3 B Analog control signal for blue color. Used only on color display devices.

4 ID2 Identification signal for display device 2゜5 Reserve (ground) Reserve (ground) 6 R Return Red analog signal ground (bin 1). Used only with color display devices be done.

7 G return Grounding of green color or monochrome level signal.

8 B return Blue color ground signal. Used only on color display devices.

9 Key encoding (pin hole of connector is closed) 10 GND Digital signal connection earth 11 1DO display device identification signal 0 12 1DI Display device identification signal 1 13 Horizontal deflection signal for H3YNC display 14 For VSYNC display Vertical deflection signal 15 Reserve Reserve In a preferred embodiment of the device according to the invention, the RSG and B video signals of Table 1 are signal (0~7V) and TTL level horizontal and vertical deflection signal H3YNC (!:VS YNC is used. Analog video signals RSG and B are provided by separate A/D converters 36. The received horizontal deflection signals H3YNC and VSYNC are sent to the control circuit 35. is applied to the CPU 32.

The CPU controls and initiates the operation of all devices and selects the correct display mode . Additionally, by using communication link 33, CPU 32 can perform the functions shown in FIG. FI patent application 9 through standard VGA video interface and cable 5 Communication with the central unit 1 of the PC (Fig. 1) according to the principles disclosed in No. 14435. believe This allows the PC to connect to the software through the video interface. The display device can be controlled more easily. The control program controls image position, brightness, and control. Includes controls for trust, stretching and color correction, display mode selection, etc. Appropriate The CPU 32 then transfers various display device identification and status data to the PCI. Ru.

When controlling the device, CPU 32 uses device characteristics stored in memory 34. do. Memory 34 is non-volatile and it is connected to the PC through communication link 33. It may also be reprogrammable by software. Memory consists of several types of tables. Contains parameters that represent the display mode, and these parameters Used by CPU 32 when mode is used. In general, image positioning, Display mode, contrast, brightness and color correction parameters are stored in memory 34 be done.

Based on the deflection signals (their timing and polarity) that it receives, the CPU 32 to identify the display mode used by the display adapter and display The mode starts the device. As mentioned above, the sampling frequency is In order to obtain a stable and interference-free image using the converter 36, the display adapter should be very close to the video frequency used by the monitor. However, the seeds The video frequency of various display adapters may vary from the nominal VGA video frequency. The interface device according to the invention can thereby be used with sufficient accuracy in order to It must be possible to determine the video frequency of each video signal received by do not have.

In a preferred embodiment of the invention, CPU 32 is configured to The video frequency is calculated using the flat deflection signal H3YNC. With this, it becomes V GA display adapter horizontal resolution (active video period HA in Figure 2) CTIVE) comprises 640 pixels, i.e. for the video clock period. The length of the corresponding horizontal deflection period HPER is 800 pixels or video clock period. Use the information that exists. The CPU is clocked by the device's accurate internal reference clock signal. For some horizontal deflection periods HPER of the received horizontal deflection signal H3YNC, Calculate the time spent. The actual duration of the video clock period is By dividing the calculated duration of the horizontal deflection period HPER by a predetermined number of 800 between be acquired. The result is the video used by the VGA display adapter Indicates how much the frequency deviates from the nominal video frequency for the above VGA resolution . Based on this information, the CPU 32 determines the Generate an appropriate register value and apply it to control circuit 35. For example, horizontal The calculated length of the deflection period HPER is 31°778 microseconds (the deflection frequency is 31.468 microseconds). kHz), - the length of the video clock period is HPER/800=39. 721nsT, and supports a video frequency of 25.175MHz. Horizontal deflection period If the HPER contains about 800 pixels, the PC, through the communication link 33, Transfer the new value to the CPU 32.

The control circuit 35 generates mutually synchronized control signals. In other words, the A/D converter The sampling clock SAMPLE of the output buffer 36 and the control clock SAMPLE of the output buffer 38 clock LOAD, video clock CLOCK of digital display 39, deflection and and control signals H3YNC', BLANK', and VSYNC'. control circuit 35 is a phase-locked loop (PLL) and a voltage controlled oscillator (VCO) 41 including. In a preferred embodiment of the invention, the PLL operates at four times the video frequency (n =4) at a clock frequency 4XCLK, and this clock frequency is controlled by VCO of circuit 41 based on parameters supplied by CPU 32. are synthesized. The frequency synthesis range is relatively narrow, 24-29MHz; As a result, a sufficiently stable lock frequency is obtained. To reduce RFI interference In addition, circuit 41 is preferably an integrated circuit, such as an IC31394, and Lock signal 4xCLK is used only within circuit 41.

As a result, the circuit 41 also outputs the clock signal 4xCLK and the control signal CLOCK. Contains the registers needed to generate SAMPLE and LOAD. circuit 41 is also the reference frequency in the synthesis of the signal 4xCLK and for the CPU 32. Contains a crystal XTAL used as an accurate reference clock. applied to circuit 41 The polarity of the received horizontal and vertical deflection signals H3YNC and VSYNC is determined by circuit 35 before The internal polarity of the circuit 35 is set by the polarity adjustment circuit 44B, and the internal polarity of the circuit 35 is synchronized with the digital synthesis stage 45.

The circuit 35 also provides the appropriate deflection signals H3YNC', VS for the display panel 39. The signals include a deflection controller °43 that generates YNC' and BLANK''; Synchronized with the receive deflection signals H3YNC and VSYNC, the CRT beam shown in FIG. Elements HSYNC, HBP, HACTI that are the same as the video signal! , HFP, VSYNC , VBP, VAct+vi & VFP, the 6° controller 43 controls the deflection. Contains control registers used in Programmable deflection controller 43 Therefore, various components (A/D, conversion circuit, FRC circuit) are used in the device. , it is easy to adapt the timing of the device to the components used. love of invention In a new embodiment, the horizontal deflection signals HSYNC' and BLANK' are 4x formed by a programmable number of periods of the CLK clock signal, and The period signal VSYNC' consists of a programmable number of horizontal deflection periods HPER. . The polarity of the generated deflection signal is determined by a polarity adjustment circuit 44A on each display panel 39. Adapted.

Circuit 41.43.44A and 448ft, control bus 30”C’CPU3211:, J = Controlled by parameters programmed in control register 42 It will be done.

As mentioned above, circuit 41 operates at a frequency four times the video frequency and therefore Therefore, the horizontal deflection signal is typically accurate to at least one quarter of the video clock period. It is possible to synchronize all signals generated by No. H3YNC and circuit 35. It is Noh. Sampling clock SAMPLE and digital display 30 clock Each lock period is 4 periods of basic clock 4xCLK (original video frequency) Consists of.

The sampling of analog signals R%G and B by the A/D converter is shown in Figure 5. be done. A/D conversion uses the sampling clock signal SAMPLE is performed at a time determined by circuit 35, so that the sample quantization is always performed in the stable part of the video signal to prevent quantization errors and To provide a stable flicker-free image. As shown in Figure 5, this With two periods of basic clock 4xCLK at the beginning of the deo clock period This is done by timing the rising leading edge of the sampling pulse. As a result, the trailing edge of the pulse that activates sampling is a stable signal point. falls in the middle of the video clock period.

The interface device shown in Figure 3 is a VGA display adapter. control circuit to be started at any instant (deflection period of the received video signal) with respect to Path 35 is used for receiving horizontal synchronization, for example when changing the display mode or starting the device. The horizontal synchronizing pulse H3YNC' generated thereby is applied to the period pulse H3YNC. Must be able to phase lock automatically. This characteristic is required. Another reason is that the device's internal clock CLOCK is not accurate to the video frequency of the received signal. is not equal to .

Referring to FIG. 4, in order to perform the above operation, a phaseron loop of circuit 41 is used. The horizontal deflection pulse H3YNC received from 45 and synchronized with 4xCLK is Horizontal deflection pulse H3YNC' generated at clock frequency 4xCLK and compare. If the pulses H3YNC and HSYNC' are exactly in phase, the adjustment No adjustment will be made. The leading edge (state change) of pulse H3YNC' is the received pulse H3Y If it occurs after the leading edge of the NC, it is sent to the digital display 39 Phase and sample of deflection signals HS YNC', VSYNC' and BLANK' The phase of the sampling signal SAMPLE and the signal LOAD depends on one or more clocks controlling the signals. proceed by "stealing" the clock pulse 4xCLK. In the case of Figure 6 , the leading edge of pulse H8YNC' is delayed by two 4xCLK periods; Therefore, the above phase shift is caused by the pulse H3 by two clock periods 4xCLK. This is done by shortening YNC'.

Correspondingly, when pulse H3YNC' arrives earlier with respect to pulse H3YNC , the phase of the above control signal is determined by one or more 4xCLK clocks as shown in FIG. They are delayed by adding time periods to them.

An alternative solution to synchronization is to change the frequency of the clock pulses instead of changing the number of basic clock pulses. A phase-locked loop controls the VCO and thus the fundamental clock frequency. It is. The generated pulse H8YNC' precedes the synchronizing pulse H5YNC. If so, the duration of period HPER is equal to decreasing the fundamental clock frequency. will be increased. If the generated pulse H3YNC' is time-delayed, the original The present clock frequency is increased so that the duration of period HPER is shortened. .

Pulses H3YNC and H3YNC' are always at the leading edge of pulse H3YNC. be compared. The trailing edge of the deflection pulse H3YNC' is the position of the image on the display panel 39. used to determine location. Clock panel 4XCLK addition/removal is the same. After comparison is made very quickly during one deflection panel, the correction is therefore continued (deflection period H Applies to PER. In this way, all generated by control circuit 35 The control signal is synchronized with the state of the received video signal, and the image is displayed correctly without interference. displayed on the screen at the position.

A simpler alternative method of synchronization is to use H3Y included in the deflection control circuit 43. Set the NC' counter register and set the pulse H5 as shown in Figure 8. After the end of YNC, synchronize H8Y in a controlled manner to operate the counter It uses NC pulses. In this way, the output of the counter is controlled The length is equal to the pulse H3YNC, and the pulse H3YNC' is generated, but the pulse The phase difference between the signals is exactly one period of the clock signal 4xCLK.

As mentioned above, the CPU 32 (from the i-quotient signals H3YNc and VSYNCl, can distinguish between different character modes and interlaced display modes.

interlaced display modes (e.g. used in television) Thus, even and odd lines of the image are generated separately in successive image fields. This mode By detecting the Instead, it immediately generates two 7-digit russ H3YNC', which are shorter than normal, in sequence. , causes the display panel 39 to shift its internal pointer forward by one horizontal line or more. Program the circuit 35 as follows.

In this way, the display device can be operated in interlaced display mode. Ru. Figures 10 and 11 are non-interlaced and interlaced tables, respectively. This shows the generation of pulse H3YNC' in the display mode.

VGA character mode typically has 720 pixels per horizontal line.

Digital table with reasonable image quality capable of displaying 640 pixels per horizontal line To be achieved in the display panel, every ninth pixel must be omitted. stomach. The easiest way to accomplish this is to change the type font via the PC and use V Start using 640 pixel resolution on GA display adapters That's true. However, some operating systems and applications such as O8/2 The application program must be compatible with CRT displays (constant VGA environment). Essential. In the interface device according to the invention, the ninth part of the received video signal Do not digitize every pixel (which makes it more compatible with these programs). It is possible to achieve compatibility. In reality, this pixel contains no information and is Used to separate characters that are different from each other in a plane.

By detecting normal VGA character mode, CPU 32 At the same time, as shown in FIG. Starting from the first pixel after the start of period HAct+vt of HBLANK', the table is rotated to remove the corresponding pulse of the video clock CLOCK on the display panel 39. Program path 35. Low resolution display mode (e.g. 40x25 character mode) ), the corresponding pulses are omitted at the 17th and 18th pixels. As a result, the corresponding display resolution of the display 39 is the initial 720x40 360x400 instead of 0, and the horizontal character size is 1 It is 6 pixels.

In character mode, the image displayed on the display 39 is an interlaced display. Similar to what is associated with modes, for example every ninth by generating one or more additional HSYNC' pulses at the horizontal line. The image is stretched by software in the vertical direction. General VGA character area has 9x16 pixels, so that at least one additional pulse , for example, on every 16th line. In this way, the empty line becomes Generated between character lines in character mode. Additional horizontal synchronization pulse number m and them The lines that are generated are selected depending on the character mode used and the desired stretching effect. Ru. For this purpose, the deflection control circuit 43 uses a control register of the controller 43. line that generates an additional HSYNC' pulse by reaching the value stored in the A counter is provided and the number of additional pulses is determined by another control register of the controller 43. determined by parameters stored in the controller.

An A/D converter 36 used in the device digitizes the video signal. Any converter intended or suitable for. A suitable circuit is Broo Manufactured by ktree Corporation, San Diego, USA Contains Bt252 or Bt254. The former circuit consists of one A/D converter. converter, and the latter is equipped with three parallel A/D converters.

After the A/D converter, digitization to shape the digitized output data A translation memory addressable by the video output is coupled. Conversion memory 3 7 is built-in in the integrated A/D converter circuit (Bt252) or it is A separate memory circuit. The conversion memory 37 converts each output value into digitized data. Contains a lookup table stored for video signal values, the output values of which are stored on the display 3. 9 as a digital video signal.

The conversion memory 37 allows the brightness or contrast to change the contents of the conversion memory 37. It changes on the screen by A/D converter circuit Bt254 is the digitization lower limit and upper limit (quantization reference value) for each video signal R, GSH. Contains six programmable D/A converters set as The brightness change above digitization also allows the size of the voltage range to be digitized to remain unchanged. or by changing the voltage level of the inverter (through the D/A converter 40). control). Changes in contrast keep the lower limit constant , by changing the range. The contrast of the display panel 39 itself is , usually fixed at some value that is difficult to change.

Conversion memory 37 allows brightness and contrast adjustment as well as various panel formats. Changes required by interfaces (various word widths) and software It is possible to perform color correction using a. TFT format LCD panel color Filters typically help CRT displays produce a display quality that is very close to the original image. The same control parameters used to produce a slightly purple image. such a color The error is corrected (gamma correction) by the conversion memory 37, and in addition, the positive image , effect image, etc. can be provided.

Conversion memory 37 is designed for control of LCD panel and VGA display. It can be replaced with a RAMDAC commonly used in adapters. one One such circuit is the GD6 manufactured by Cirrus-Logic. 340, and using this, the number of colors that can be displayed on the display 39 is FRC or by using dithering techniques. In some cases, these technology has advantages over traditional conversion memories due to its high integration level (low external components). It's very convenient.

One such alternative connection is shown in FIG. The above GD6340 circuit The circuit also supports both digital display control and cathode ray tube control. This allows for chaining of display devices.

Digital monochrome display panels (such as Nyab LM64448Z) usually Two blocks that must be addressed (1/240 duty ratio) divided into Figure 14 shows a suitable connection for controlling this type of display panel. , in which case the additional controller 120 and the intermediate memory 121 are the transformation memory 37 and a display panel 39. The controller 120 has an intermediate memory 1 21 stores the digital video data provided by the conversion memory 27; , required by the timing and addressing mechanisms of monochrome displays. The data is read from the intermediate memory 121 using the method described above, and the data is displayed on the display panel 39. supply to.

Furthermore, in the interface device according to the invention, for example The software, as disclosed in patent application No. 914435, Various image adjustments by card or mouse can be made through the communication link 33, or For example, keyboard, control panel, mouse, inverter, controls for manual adjustment Potentiometers, etc. are connected to external device interfaces for control or data transmission. It is possible to incorporate various functions that can be performed by the user through the interface 32A. can.

The alignment of images on the screen is performed, for example, as follows.

The bitmap is stored in the memory of the PC's display adapter and forms a rectangle that follows the outline of the active image on the screen.

By using a keyboard, mouse, or other external device such as a control panel , the image is moved to the right or left (also in the vertical direction) by one 4xCLK clock period. commands by the PC software to displace the image (up or down by one line) By supplying a code to the CPU 32, it is displaced on the screen. The CPU 32 is reprogramming the control registers of the deflection controller 43 of the control circuit 35; displaces the images so that they correspond to the new machine position. This control program Use of a ram requires a more thorough knowledge of the device from the user. On the other hand, the statue is It is positioned with great precision and reliability.

The frequency shift of the frequency synthesizer vCO of the control circuit 35 also affects the display area of the PC. more accurate by storing bitmaps in the adapter's memory; This map forms a grid of dots in the display 39 close to the right edge of the image. do. When the frequency of the voltage controlled frequency generator is changed, the dots in the grid The sampling frequency is the bit rate used by the PC display adapter. When it deviates too much from the audio frequency, it starts to flicker. CPU32 software By alternating the sampling frequency between low and high values by means of The optimal frequency at which no flickering occurs in the image is searched. This adjustment method is very appropriate when the timing does not comply with the implementation standard.

After the images have been aligned in the desired manner, CPU 32 can control timing, if desired. data relating to the memory 34 is commanded to be stored in the memory 34.

In error situations, images can be quickly selected (e.g. by pressing a key on a PC) As a result, the initial position or default value position is restored.

Some display adapter circuits allow the images to be displayed in the same timing mode. Displayed in different positions in different modes. This takes the difference in screen This does not cause problems with CRT displays. However, digital With the tall display panel 39, it displaces the image to the left or right, so that the image Vixels corresponding to the lag in the edge region are not displayed on the screen. delay The display adapter's various internal switching buses in various display modes by. For example, the most widely used VGA character mode 3+ is 720x400 Although the resolution is the same timing as graphic mode 6 (640x200) Use mode. The operation of the display adapter circuitry varies greatly from mode to mode. image, and the image is positioned on the screen in a variety of ways, as described above.

In the device according to the invention, the problem is e.g. The solution is to incorporate communication requests in the device software. communication The request requires the interface device according to the invention to specify the exact display mode to be used. give information. The CPU 32 determines that the image position bone corresponding to this display mode is a parameter. The memory 34 is searched for, and the control circuit 3 is searched in response to these parameters. Program the image adjustment registers of 5. The device software on the PC can be terminated and PC EPROM memory or system memory as resident program (TSR) stored in memory.

In addition, in the software (・ware) of the CPU 32, the user or It is easy to incorporate an integer value that can be changed by the user or by the application. When the /yon is started, it is set aside for use.

The interface according to the invention places a digital display on a computer. applied in testing analog display adapters by changing . During one image field, the video signal of the adapter passes through the interface according to the invention. The total sum (well, calculated from the digitized image information, This summation will be applied to the test image if there is a failure in the display adapter. deviation from the sum calculated by

The drawings and their associated description are intended only to illustrate the invention. the In detail, the analog video interface according to the invention includes an attached frame. Varies within the range of .

FIG.1 FIG. 2 FIG.3 FIG. 5 No clock pulse FIG.9 Special table Hei 7-503327 (10) FIG.6 FIG.7 FIG.8 FIG. 10 11Lahx $-Go] FIG. 11 FIG. 13 FIG. 14 Copy and translation of amendment) Submission (Article 184-8 of the Patent Law) July 29, 1994

Claims (1)

[Claims] 1. at least one analog video camera with combined or separate horizontal and vertical deflection signals; an analog video input (31) for receiving an audio signal; digitizing means (36) for digitizing the analog video signal; a base having a frequency that is at least n times (where n≧1) the desired video frequency; means (41) for generating the main clock signal; Sampling for control signals and digitization means for digital displays and means (41, 43) for generating a clock signal. In an analog video interface for a display, the display In addition, A method for determining the real video frequency of an analog video signal based on the received signal Step (32) and of a frequency that is at least n times (where n≧1) the determined real video frequency. a programmable frequency generator responsive to said determining means for generating a basic clock; said means for generating a basic clock signal comprising nerator means. An analog video interface characterized by: 2. The means (41) for generating the basic clock signal has a programmable frequency. comprising synthesizer means and means (32) for determining the video frequency. Calculate the length of the deflection period of the signal horizontal and/or vertical deflection signal and apply it to a given video. Divide by the number of frequency periods and generate the corresponding n times the basic clock frequency characterized in that it comprises calculation means for programming the frequency synthesizer means. A video interface according to claim 1. 3. The predetermined number of video frequency periods is set automatically or by user action for each received video. Claim 2 characterized in that the device is programmable to correspond to a video signal. Video interface as described. 4. Digital display sampling clock period and/or control clock the period comprises n basic clock periods and the active edge of the sampling pulse is timed to coincide with a stable, invariant point in the analog video signal. , the horizontal deflection period and horizontal sync pulse of the digital video display are programmed the vertical deflection period and the vertical synchronization period. characterized in that the curve is formed by a programmable number of horizontal deflection periods. A video interface according to any one of claims 1, 2 or 3. 5. A control means (35) controls the received horizontal synchronization pulse at the basic clock frequency. Compared to the generated horizontal sync pulse, the leading edge of the generated horizontal sync pulse is the received horizontal sync pulse. If it occurs after or before the leading edge of the horizontal Decrease or increase the number of elementary clock periods included in the synchronization pulse, respectively. According to claim 4, the horizontal synchronization pulses are synchronized by Video interface included. 6. Control means (35) are timed by a basic clock and emit horizontal synchronization pulses. counter means positively controlled by the received horizontal deflection signal to generate a horizontal deflection signal. The video interface according to claim 4 or 5, characterized in that: 7. A control means (35) controls the received horizontal synchronization pulse at the basic clock frequency. By comparing the generated horizontal sync pulse and adjusting the basic clock frequency, According to any one of claims 2 to 6, characterized in that synchronization pulses are synchronized. Video interface included. 8. The incoming analog video signal is in interlaced display mode and each a preceding period characterized in that the raw horizontal deflection period includes two consecutive horizontal synchronization pulses; A video interface according to any one of the claims. 9. The received analog video signal conforms to the character mode and has every k horizontal offset. The horizontal synchronization period generates m additional horizontal sync pulses to achieve the image stretching effect. including, where k and m are programmable parameters. A video interface according to any one of the claims. 10. The resolution of the digital display (39) is N1 pixels per horizontal line. Yes, the incoming analog video signal conforms to character mode, in which case horizontal lines hit There are N2 pixels, where N1<N2, and the control means controls the display. at least every ninth or Claims 4 to 4, characterized in that every 17th and 18th pixel is removed. 9. The video interface according to any one of 9. 11. via the control means or preferably the video input (31), e.g. Data transmission hand for data transmission with computer to input commands According to any one of the preceding claims, characterized in that it comprises a step (33). Video interface included. 12. A video interface provides user input for giving user commands. the control means (32, 34, 35) A device characterized by making desired image adjustments on the screen in response to user commands. A video interface according to any one of the preceding claims. 13. The video interface provides a user interface for inputting user commands. The control means (32, 34, 35) are equipped with an interface (32A), and the control means (32, 34, 35) In order to eliminate the interference caused in the image displayed by the The basic clock frequency is adjusted in response to user commands. A video interface according to any one of the preceding claims. 14. The control means comprises a memory (34), in this case the necessary information for adjusting the image. Preceding claim characterized in that essential information is stored for different display modes A video interface as described in any one of the ranges. 15. Digitizing means (36) digitizes the at least one video signal. The control means (32) comprises an A/D converter for at least The lower digitization voltage level and/or digitization limit of one A/D converter. by changing the size of the voltage range that is applied to the digital display screen. a preceding step characterized by adjusting the brightness and/or contrast level of the Video interface according to any one of the claims. 16. The digitizing means (36) is connected to the digitized video output of the A/D converter. thus addressable and preferably shaped digitized output data an associated transformation memory hand programmable by the control means (32) to generate stage (37) and the conversion memory means are preferably digitally controlled Due to the characteristics of video displays, brightness, control, and A preceding request characterized by last, color, and/or word length correction. A video interface according to any one of the requirements. 17. The digitizing means (36) displays the display color by FRC or dithering technique. digitized video output of the A/D converter to increase the number of The preceding claim is characterized in that it has associated means (110) that can specify a response. A video interface as described in any one of the boxes below. 18. The digital display (39) is connected to two simultaneously addressable blocks. a display divided into blocks, and an intermediate memory for video data. (121) and means for addressing intermediate memory and display (120) ) is digitized to supply video data from intermediate memory to the display. An antecedent characterized in that it is provided between the means (36) and the display (39). A video interface according to any one of the claims. 19. A means for the video interface to chain displays (110 ). interface.