KR100207315B1 - Plate display device - Google Patents

Abstract

The present invention relates to a flat panel display device, which converts a video signal having a resolution different from that of a monitor into a resolution suitable for display on a monitor, and asymmetric when inputting an SVGA mode to an XGA monitor according to the resolution conversion. The function of symmetrically centering the screen's top, bottom, left and right margins, to implement a simplified interface device of the On Screen Display signal, and adding DC voltage to the video signal in addition to the inverter The present invention relates to a flat panel display having a function of adjusting brightness, a contrast function for contrast of a screen, and a function of implementing Display Power Management Signaling (DPMS), which is a power saving mode of a monitor.

Description

Flat panel display device

The present invention relates to a flat panel display device.

More specifically, when a video signal with a resolution different from that of the monitor is input, the function converts the resolution to be suitable for display on the monitor, and when the SVGA mode is input to the XGA monitor according to the resolution conversion, the top, bottom, left and right margins of the screen are symmetrical. The ability to centralize the screen, to implement a simplified interface device for the On Screen Display signal, to adjust the brightness of the screen by adding DC voltage to the video signal in addition to the inverter, The present invention relates to a flat panel display having a contrast function for contrast of a screen and a function for implementing Display Power Management Signaling (DMPS), which is a power saving mode of an LCD monitor.

Currently, many CRTs are used as monitors, but the use of flat panel displays increases due to various advantages of flat panel displays having a fixed dot matrix (DOT MATRIX) structure. The flat panel display apparatus includes a liquid crystal display (LCD), a plasma display panel (PDP), a field emission display (FED), and an EL. In the case of PDP, it is used as a large screen for advertisement, and LCD has less volume and power consumption than CRT and can be attached to the wall. Therefore, the use of LCD in computer, TV, image and text display devices will be further expanded. In accordance with this trend, improvements and studies of flat panel display devices are required.

The present invention is described by taking an LCD monitor as a flat panel display device as an example.

1 is a schematic block diagram of a liquid crystal display monitor according to the prior art.

An amplifier 1 for amplifying a video signal input from a video card of the computer 100 is connected to an analog / digital converter 2 for converting the video signal into a digital signal, and the analog / digital converter 2 is connected to the amplifier 1. The mux 8 is connected, and the mux 8 is connected with a first gate array 9 for setting timings of the horizontal synchronization signal and the vertical synchronization signal.

In the sync signal detector 3 for separately detecting the horizontal sync signal and the vertical sync signal among the video signals input from the video card of the computer 100, sampling the signal in the process of converting the analog / digital converter 2 into the digital signal. The phase-locked loop 4 for setting the clock and timing in the first gate array 9 is connected.

An on-screen display unit 6 for outputting an OSD signal is connected to the microcomputer 5 with a built-in digital / analog converter, and the analog-to-digital converter 7 for converting a digital signal to the on-screen display unit 6 is provided. Is connected, and an analog / digital converter 7 is connected to a mux 8 for musing a video signal and an OSD signal.

The first gate array 9 is connected with a second gate array 10 for storing and converting data so as to be suitable for display on the LCD panel 11, and the second gate array 10 is an LCD panel as a display device. The part 11 is connected.

The operation of the conventional liquid crystal display monitor configured as described above will be described.

The input video signal is amplified by the amplifier 1 and input to the analog-to-digital converter 2. At this time, the synchronization signal detector 3 detects a horizontal synchronization signal and a vertical synchronization signal among the video signals, and the clock frequency set by the phase synchronization loop 4 by using the synchronization signal is used to convert the video signal from the analog / digital converter 2. It is provided at a clock frequency for sampling and is also provided to the first gate array 9 to set output timings of the vertical synchronization signal and the horizontal synchronization signal.

And. The mux 8 connected to the analog-to-digital converter 2 outputs a video signal converted into a digital signal when the OSD function is not used, and when the OSD function is used, a screen using a vertical synchronization signal and a horizontal synchronization signal is used. It has a function to output the OSD function instead of the video signal at a fixed position of.

Here, the peak-peak voltage of the input video signal is 0.7V. In addition, the peak-peak voltage of the OSD function output from the on-screen display unit 6 is 5V. Therefore, when the two signals are switched in the mux 30, since the voltage value is different, signal processing is impossible. To this end, an amplifier 1 was used to amplify the video signal to 5V, the same peak-peak voltage as the OSD signal. The video signal amplified by the amplifier 1 is converted into a digital signal by the analog-to-digital converter 2 and input to the mux 8.

The OSD signal output from the on-screen display unit 6 is converted into a digital signal by the analog-digital converter 7 and input to the mux 8.

The mux 8 outputs a video signal converted into a digital signal when it is not necessary to display a text signal on the screen, and when the text signal is to be displayed on the screen, the mux 8 uses a vertical sync signal and a horizontal sync signal to determine the screen. Outputs an ODS signal instead of a video signal at the position.

The video signal output from the first gate array 9 is stored and converted to be suitable for display on the LCD panel 11 in the second gate array 10 so that the video signal is displayed on the LCD panel 11. do.

In this case, first, various types of resolutions will be described in order to view a screen on which a video signal is displayed. That is, by resolution, VGA (640 480), SVGA (800 600), XGA (1024 768), EWS (SXGA) (1280 1024).

The resolution of the LCD monitor used in the present invention is 1024 as XGA. 768. 1024 resolution 768 means that the monitor displays 1024 pixels horizontally and 768 lines vertically.

When the XGA mode is input to the LCD monitor, the screen is suitable for user viewing as shown in FIG. 2A.

However, when VGA mode is input, the resolution of VGA is 640 Since it is 480, the number of pixels appearing horizontally is 640, and the number of vertical lines is 480, so that the picture is displayed small on the monitor as shown in FIG.

When the SVGA mode is historyed, as in VGA, the number of pixels horizontally displayed as shown in FIG. 2C is displayed on the monitor with 800 vertical lines and 600 pixels.

When the EWS mode is input, the resolution of the EWS is 1280. Since the area of the monitor to display the picture is 1024, only a part of the picture appears on the monitor, and the remaining part does not appear as shown in FIG.

Conventional liquid crystal display device as described above is not suitable for the user's view as shown in 2b, 2c, 2d when the mode with different resolutions such as VGA, SVGA, EWS is input to the XGA LCD monitor. In order to solve this problem, the top, bottom, left and right margins are asymmetrical when inputting SVGA mode even when the input video signal mode is determined and converted to a resolution suitable for the XGA LCD monitor. There was this.

In addition, the interface device of the OSD signal converts the analog video input signal to M bits in the analog / digital converter 2, and converts the OSD signal to M bits in the analog / digital converter 7, M-bit OSD signals are muted to output video signals or OSD signals, so two analog / digital converters must be used, and M-bit video signals and M-bit OSD signals are input to output M-bit signals. There has been a problem of using a complex mux 8 that requires several lines with each number of bits.

In addition, there is an inverter (not shown in the figure) that performs brightness adjustment, but the inverter's variable capacity range was not large enough to satisfy the user's satisfactory brightness adjustment, and there was no contrast function. In addition to the sound, the LCD monitor does not have a power saving mode.

SUMMARY OF THE INVENTION An object of the present invention is to provide a flat panel display device that converts a resolution so as to be suitable for a monitor when a video signal having a different resolution is input to the monitor.

Another object of the present invention is to provide a flat panel display apparatus in which the top, bottom, left and right margins are symmetrical by delaying horizontal and vertical synchronization signals of the asymmetrical top, bottom, left and right margins of the screen when performing the resolution conversion function.

It is still another object of the present invention to provide a flat panel display device which implements a simplified interface device of an OSD signal by muxing an OSD signal and an input video signal before converting the input signal into a digital signal.

Another object of the present invention is to provide a flat panel display device that performs a brightness adjustment function by adding a DC voltage to a video signal input to a clamp.

It is still another object of the present invention to provide a flat panel display device which performs a contrast function that can sharpen contrast by outputting by judging the magnitude of the input video signal by varying the highest voltage of the analog-to-digital converter. have.

It is still another object of the present invention to provide a flat panel display device which can reduce power consumption of a monitor by performing DPMS that shuts off the power of the monitor when there is no input signal from the outside for a predetermined time.

1 is a schematic schematic block diagram of a liquid crystal display monitor according to the prior art.

2A to 2D are views showing display screens when video signals having different resolutions, such as XGA, VGA, SVGA, and EWS modes, are input to XGA liquid crystal display monitors according to the related art.

3 is a block diagram of a liquid crystal display monitor according to the present invention.

4 is a detailed block diagram of FIG.

FIG. 5 is a diagram showing resolutions for each mode, converted resolutions, and vertical, horizontal frequency, dot clock, and division values of two phase locked loops for performing a resolution conversion function of a liquid crystal display monitor according to the present invention.

6 is a diagram illustrating a horizontal synchronization signal, screen information, and an outer signal of a video signal input in performing a resolution conversion function of a liquid crystal display monitor according to the present invention.

7A and 7B illustrate a method of converting vertical lines during resolution conversion in performing a resolution conversion function of a liquid crystal display monitor according to the present invention.

8A and 8B are diagrams showing top, bottom, left and right margins on the monitor when the SVGA mode is input as a result of performing the resolution conversion function of the liquid crystal display monitor according to the present invention.

FIG. 9 is a block diagram for screen center implementation when the SVGA mode is input in the liquid crystal display monitor according to the present invention. FIG.

10 is a block diagram showing an interface device of an on-screen display signal of a liquid crystal display monitor according to the present invention.

11 is a detailed circuit diagram of the clamp shown in FIG.

12 is a detailed circuit diagram of the analog-digital converter shown in FIG.

FIG. 13 is a diagram illustrating input signals and output signals of the analog-digital converter of FIG. 12; FIG.

14 is a flowchart for performing a power saving mode of an LCD monitor in a computer.

15 is a diagram showing the power saving mode steps.

* Explanation of symbols for main parts of the drawings

1: Amplifier 2,7: Analog-to-digital converter

3: sync signal detector 4: phase sync loop

5: microcomputer 6: on-screen display

8,14 mux 9: first gate array

10: second gate array 11: LCD panel portion

13: signal amplitude control unit 15: clamp

16: digital to analog converter 17: LVDS

18: inverter 19: power supply (SMPS)

20: analog / digital converter 21 23: analog to digital converter

30: microcomputer 32: first delay

33: second delay 35: level converter

40: graphic control section 50: R signal memory section

51 53: first to third line memory 60: G signal memory section

61 63: fourth to sixth line memories 70: B signal memory section

71 73: seventh to ninth line memory 80: first phase synchronization loop

81: first phase detector 82: first low pass filter

83: first voltage controlled oscillator 85: first divider

90: second phase synchronizer loop 91: second phase detector

92 second low pass filter 93 second voltage controlled oscillator

95: second divider 100: computer

C1, C1: capacitor R1, R2: resistor

OP1 OP3: Associative amplifier FET: Field effect transistor

SW1 SW6: Switch

According to an aspect of the present invention, there is provided a flat panel display apparatus for receiving a RGB signal and a synchronization signal from a video card of a computer and displaying the same on a panel. A signal amplitude adjusting unit for removing noise and an on-screen display signal output from the on-screen display are converted to be equal to a voltage level of a video signal which is an output signal of the signal amplitude adjusting unit to mute the level-converted on-screen display signal and the RGB signal. A muxing means, a clamp for adjusting the brightness of the video signal output from the mux means, an analog / digital converter for converting the video signal output from the clamp into a digital signal and performing a contrast function for adjusting the contrast; Determines the mode by receiving the sync signal When the microcomputer that controls the overall control of the stem and the mode of the video signal input from the microcomputer is determined, the video signal processor converts the video signal output to a resolution suitable for display on the monitor and converts it to the panel. It is characterized by.

Hereinafter, a flat panel display device of the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram of a liquid crystal display monitor according to the present invention.

In the computer 100 which outputs R, Red, G, and B signals, which are video signals, horizontal and vertical synchronization signals, a signal amplitude control unit 13 for adjusting the amplitude of the RGB signal among the video signals is provided. The signal amplitude control unit 13 is connected to a mux 14 that muxes an RGB signal and an OSD signal.

The OSD signal input to the mux 14 is output from the on-screen display unit 6, and the on-screen display unit 6 is connected to the microcomputer 30 that controls the system as a whole, and the microcomputer 30 The digital to analog converter 16 is connected. The control signal output from the digital / analog converter 16 is applied to the clamp 15 connected to the mux 14 to adjust the brightness of the monitor, and also to the analog / digital converter 20 connected to the clamp 15. Is approved.

The microcomputer 30 receives the horizontal synchronizing signal and the vertical synchronizing signal from the computer 100, determines the resolution, and outputs the result and the data to the graphic controller 40. The RGB signal sampled by the analog / digital converter 20 is also input to the graphic controller 40.

When the resolution of the input video signal is determined by the microcomputer 30, the graphic controller 40 converts the RGB signal output from the analog / digital converter 20 to a resolution suitable for an LCD monitor and outputs the converted signal.

The graphic control unit 40 is connected to the first phase synchronization loop 80 that generates a clock whose phase and frequency are synchronized with the input video signal for the write operation to the graphic control unit 40 using the horizontal synchronization signal. The first phase synchronizer loop 80 is connected with a second divider 85 for adjusting the dividing value so that the input graphic mode is suitable for the LCD monitor.

The graphic control unit 40 is connected to the graphic control unit 40 using a horizontal synchronization signal, and a second phase synchronization loop 90 for generating a clock whose phase and frequency for a read operation are synchronized with the input video signal. The second phase synchronizer loop 90 is connected to a second divider 95 that adjusts the dividing value so that the graphic mode to be input is suitable for the LCD monitor.

In the graphic controller 40, since the video signal processed by the graphic controller 40 is a digital signal, many pins are required on the LCD panel 11 for wiring, and thus, 8-bit signals can be transmitted in one line to compensate for this. Low Voltage Differential Signaling (LVDS) 17 is connected, and the LCD panel 11 is connected to the LVDS 17 to display a video signal whose resolution is converted by the graphic controller 40. The inverter 11 is connected to the inverter 18 for adjusting the brightness. In addition, the power supply unit SMPS 19 for supplying power to the LCD monitor device converts an AC power input from the outside into various DC voltages and outputs the same.

The operation of the liquid crystal display monitor of the present invention configured as described above will be described in detail by function.

(I) If a video signal with a different resolution is input to the XGA LCD monitor, the following describes the process of converting the resolution to suit the LCD monitor.

FIG. 4 is a detailed block diagram of FIG. 3 for explaining performance of a resolution converting function.

Looking at the configuration of the analog-to-digital converter 20 described above in detail, three analog-to-digital converter (21) to process the RGB signal respectively; 23), each analog-to-digital converter (21) The clock frequency and phase of 23) is set to the value of the first divider.

Looking at the configuration of the graphic controller 40 described above, the R signal output from the second analog-to-digital converter 21 is multiplied by the frequency divided by the horizontal frequency of the first divider 85 to the frequency value of the write clock. Thus, three line memories (51) 53). Three line memory (51 53 sequentially stores the R signal in accordance with the control signal of the microcomputer 30. And three line memories 51 The R signal stored in 53) is output to the LVDS 17 according to the frequency value of the read clock, which is a value obtained by multiplying the divided value of the second divider 95 by the horizontal frequency. At this time, three line memories 51 Selecting one line memory 53 is controlled by the horizontal synchronous signal oscillator 45.

Similarly to processing the R signal, the G signal memory section 60 and the B signal memory section 70 also have three line memories 61. 63,71 73).

FIG. 5 is a diagram showing the resolution of each mode, the converted resolution, and the division values of the vertical, horizontal frequency, and phase clock loops of two dot clocks.

The resolution represents the number of pixels displayed horizontally on the monitor and the number of lines displayed vertically.

The total resolution is a number obtained by adding the horizontal sync signal and the outer parts x and x 'to the actual screen information y expressed in the resolution as shown in FIG. That is, the full resolution horizontal value (e.g., 800 in VGA) is represented by the number of pixels shown in the resolution, H Addressable, H Right Border, H Front Porch, H Sync, H Back Porch, and H Left Border signal are added values.

In addition, the vertical value of the full resolution (e.g., 525 in VGA) may include V Addressable, the number of lines shown in the resolution, V Right Border, V Front Porch, The vertical sync signal (V Sync), the vertical signal back margin (V Back Porch), and the vertical signal V Left Border signal are added values.

The conversion resolution is multiplied by the same multiple (1.6, 1.25, 1 as shown in the diagram) horizontally and vertically to or near XGA resolution to convert VGA or SVGA mode to XGA resolution. The parenthesis is the conversion of full resolution.

The horizontal frequency indicates the period of the horizontal synchronization signal, the 'vertical frequency' indicates the period of the vertical synchronization signal.

The dot clock is a write clock for writing a video signal sampled by the analog / digital converter 20 to the RGB signal memories 50, 60, and 70 of the graphic controller 40, and a video signal stored in the memory. 11) shows the frequency of the read clock to read out for output. In terms of a formula,

to be.

The division value of the first phase synchronization loop is set to a horizontal value of the full resolution to be converted in the microcomputer 30 in order to sample the video signal input to the analog / digital converter 20 to the full resolution to be converted.

The divided value of the second phase locked loop is to set a time for reading out the video signal stored in the memory, and the divided value of the first phase locked loop 17 is multiplied by the resolution conversion ratio.

The resolution of the LCD monitor used in the present invention is 1024 XGA 768.

How to convert resolution when video signal such as VGA, SVGA is input to this monitor is as follows.

(i) First, we explain how to convert VGA to XGA.

The microcomputer 30 may determine the resolution of the video signal currently input as the horizontal synchronous signal and the vertical synchronous signal input from the computer 100. 640 if the video signal being input is VGA 480 resolution You need to convert it to 768. Here, since the resolution indicates the number of pixels and the number of lines appearing on the monitor, the outer signal must be included in addition to the screen information appearing in the resolution in the actual signal processing, and thus the description is made using the full resolution.

In order to convert the resolution of an input video signal, the number of pixels of the horizontal signal must be changed to 1280, and the number of vertical lines, 525, must be changed to 840.

i) In order to change the number of pixels of the horizontal signal, the phase and frequency of the clock to be sampled may be changed in the process of converting the analog video signal input to the analog / digital converter 20 into a digital signal. That is, in order to change the 800 horizontal signals to 1280, which is the number of horizontal signals to be converted, the analog / digital conversion unit 20 converts the analog signals to 1280 when the analog signals are converted to digital signals. The clock frequency value of the converter 20 is adjusted.

Here, the method of adjusting the frequency value of the clock of the analog-digital converter 20 is as follows.

The microcomputer 30 receives the horizontal synchronizing signal and the vertical synchronizing signal, and determines the resolution of the video signal that is currently input. If the VGA is VGA, the dividing value of the first divider 85 is set to 1280, and the first divider ( An output value of 85 is determined as a clock frequency value of the analog / digital converter 20.

The analog / digital converter 20 may use three analog / digital converters 21 to sample the RGB signals, respectively. 23).

Three analog-to-digital converters (21 The RGB signal sampled at 23 is input to the graphic controller 40. The R signal output from the first analog-to-digital converter 21 is output to the R signal memory unit 50 of the graphic control unit 40 that stores the R signal. At this time, the R signal memory unit 50 storing the R signal has three line memories 51. 53), which are switched so as to be stored in one line memory one line at a time in accordance with the control signal of the microcomputer 30. The three line memories 61 of the G signal memory section 60, which store the respective signals as well as the R and G signals output from the second and third analog-to-digital converters 22 and 23, are stored. 63 and three line memories 71 of the R signal memory section 70; 73 are stored one line type in sequence according to the control signal of the microcomputer 30.

The speed at which the RGB signal is used in the line memory of the graphic controller 40 is 40.28 MHz, which is a value obtained by multiplying 1280 which is the division value of the first divider 85 by 31.47 KHz, which is a horizontal frequency. All 525 lines are sampled in the above manner and temporarily stored in the memory of the graphic controller 40.

ii) The vertical conversion method is to change the number of lines.

The horizontal resolution conversion of the video signal stored in the graphic control unit 40 is adapted to the LCD monitor mounted using the first phase synchronizer loop 80, but the vertical axis conversion is not suitable. Accordingly, in order to adjust the number of vertical axis lines by using the data stored in the line memory of the graphic controller 40, the video information in one period of the horizontal synchronization signal is regarded as one line, and this line is determined by an appropriate method. Repeat this line or delete one line to output the vertical resolution.

A more detailed description is as follows.

First, 525 lines are changed to 840 lines.

There are many ways to change the number of lines in the vertical conversion, but one example is as follows.

The resolution conversion ratio is 640 1.6 = 1024, 480 As shown in 1.6 = 786, 1.6 (8/5), so converting 5 lines from VGA to XGA converts to 8 lines.

FIG. 7 is a diagram illustrating an example of a method of converting vertical lines during resolution conversion. Referring to FIG. 7A, the first line (a) of VGA is represented by two lines, and the second line (b) is represented by one. The third line (c) is represented by two lines, the fourth line (d) by one line, and the fifth line (e) by two lines.

That is, in the process of outputting the R signal stored in the R signal memory unit 50 of the graphic controller 40 to the monitor, the first line a is read from the first line memory 51 and output to the monitor (1). Outputs the first line (a) of the first line memory 51 once more (2), reads and outputs the second line (b) of the second line memory 52 (3), and the third line The third line c of the memory 53 is read and output (4), the third line c of the third line memory 53 is output once more (5), and the first line memory 51 Reads and outputs the fourth line (d) of (6), reads and outputs the fifth line (e) of the second line memory (52), and outputs the fifth line of the second line memory (52). (e) outputs one more time (8), resulting in five lines representing eight lines. This process is repeated every five lines to convert 525 lines to 840 lines.

As shown in Fig. 7a, the first, third, and fifth lines of the five lines were read twice, and the second and fourth lines were read once and changed to eight lines. However, as another example, any three lines of five lines may be read twice, and the other two lines may be read once and changed to eight lines.

In this way, the line memory is selected as the horizontal synchronous signal oscillator 45 in the graphic control unit 40, and the horizontal synchronous signal oscillator 45 uses the output signal of the second phase synchronous loop 90.

In this case, the speed of reading the video signal stored in the line memory of the graphic controller 40 to display the video signal on the LCD panel 11 should always be constant regardless of the number of lines displayed on the screen. Therefore, since the time for displaying 525 lines and the time for displaying 840 lines should be the same, the speed of reading a video signal from memory should be 1.6 times faster than the recording time, which is a resolution conversion ratio. To this end, the dividing value of the second divider 95 connected to the second phase synchronizer loop 90 is 2048 (1280). 1.6), and the read clock is 64.45 (2048), which is the multiplication value of the second divider 95 multiplied by the horizontal frequency. 31.47KHz) MHz.

The G signal and the B signal also receive the same control signal as the R signal and output the same to the LVDS 17 in the same process.

As a result, the horizontal signal is sampled by the number of horizontal signals of the resolution to be converted, and the number of vertical lines is increased by the number of lines of the resolution to be converted, so that the video signal for VGA mode is suitable for the XGA LCD panel unit 11 as shown in FIG. Displayed at size.

(ii) Second, convert SVGA to XGA.

The microcomputer 30 may determine the resolution of the video signal currently input as the horizontal sync signal and the vertical sync signal. 800 if the current input video signal is SVGA 600 resolution to 1024 You need to convert it to 768.

In order to convert the full resolution of the input video signal, the horizontal pixel number 1024 should be changed to 1280. Since the horizontal signal conversion ratio is 1.25, the vertical line number should be 1.25 times 625 to 625. Should give.

The resolution conversion method is the same as converting VGA to XGA. However, the write clock according to the setting of the first divider 85 value, the read clock according to the setting of the second divider 95 value, and the control signal for reading signals from the line memory are different.

i) In order to change 1024 horizontal signals to 1280, which is the number of horizontal signals to be converted, the microcomputer 30 receives the horizontal synchronous signal and the vertical synchronous signal, and determines the resolution of the currently input video signal. In this case, the dividing value of the first divider 85 is set to 1280, and the output value of the first divider 85 is determined as the clock frequency value of the analog / digital converter 20.

The speed at which the RGB signal is used in the line memory of the graphic controller 40 is 45.00 MHz, multiplied by a horizontal frequency of 35.16 KHz by 1280, which is a divided value of the first divider 85. All 625 lines are sampled in the above manner and temporarily stored in the line memory of the graphic controller 40.

ii) The vertical conversion method is to change the number of lines, converting 625 lines to 781 lines.

Resolution conversion ratio is 800 1.25 = 1000, 600 Since 1.25 (5/4), as shown at 1.25 = 750, 4 lines in SVGA convert to 5 lines when converted to XGA.

There are many ways to change the number of lines that change from 4 lines to 5 lines, but one example is as follows.

Referring to FIG. 7B, the first line (a) is represented by one line, the second line (b) by one line, the third line (c) by one line, and the fourth line (d) by It is represented by two lines.

That is, in the process of outputting the video signal stored in the memory of the graphic controller 40 to the monitor, the first line a is read from the first line memory 51 and output to the monitor (1), and the second line memory ( 52, read the second line b from the third line memory (2), read the third line c from the third line memory 53, and output it (3). The fourth line d is read out and output (4), and the fourth line d is output once more from the first line memory 51 (5). In the end, four lines are represented by five lines. This process is repeated every four lines to convert 625 lines into 781 lines.

In the above description, the fourth line is read twice, and the fourth line is changed to 5 lines, but the first line is read twice and the remaining three lines are read once, or the second line is read twice and the remaining three lines are read. You can change 4 lines to 5 lines by reading the line once, or by reading the third line twice and reading the remaining three lines once.

In this case, the speed of reading the video signal stored in the memory of the graphic controller 40 to display the video signal on the LCD panel 11 should be equal to the time for displaying 625 lines and the time for displaying 781 lines. The speed of reading the video signal from memory should be 1.25 times faster, which is the resolution conversion ratio each time it is written. To this end, the division value of the second divider 95 connected to the second phase synchronizer loop 90 is 1600 (1208). 1.25), and the read clock is 56.26 (1600), which is a value obtained by multiplying the frequency division value of the second divider 95 by the horizontal frequency. 35.16KHz) MHz.

As a result, the horizontal signal is sampled by the number of horizontal signals of the resolution to be converted, and the number of vertical lines is also increased by the number of lines of the resolution to be converted, so that the video signal for SVGA mode is displayed at a size suitable for the XGA LCD panel unit 11. It was.

(II) Second, a description will be given of a screen-centered implementation process in which asymmetric top, bottom, left and right margins are symmetrical when the SVGA mode is input in performing the resolution conversion function.

When SVGA mode is input during the resolution conversion function, the resolution of SVGA mode is 800. 600, 1000 Is converted to 750. In this case, the converted resolution is 1024 which is the resolution of XGA. It is not the same as 768, but almost close. This is 1.28 in the resolution conversion ratio, which is a complex number in various calculations. We decided to convert it to 750.

Therefore, when the SVGA mode is input, the screen is left with 1024-1000 = 24 pixels on the right side as shown in Fig. 8a, and 768-750 = 18 lines on the bottom side. There was a problem that the top, bottom, left and right margins are made asymmetrically.

9 is a block diagram illustrating an apparatus for implementing a screen center upon inputting an SVGA mode in the XGA LCD monitor according to the present invention.

A mode detecting unit 30 for determining a mode by receiving the horizontal synchronizing signal and the vertical synchronizing signal inputted from the video card of the computer 100, and a method for delaying the horizontal synchronizing signal if the mode detecting unit 30 determines SVGA. One delay 32 is connected to the horizontal synchronous signal input of the mode detector 30, and a second delay 33 for delaying the vertical synchronous signal is connected to the vertical synchronous signal input of the mode detector 30.

The mode detection unit 30 outputs the mode determination result of the video signal to the graphic control unit 40 as a microcomputer.

The operation of the screen center implementation when inputting the SVGA mode configured as described above will be described.

The mode detection unit 30 is a microcomputer, and determines a mode using a horizontal synchronization signal and a vertical synchronization signal of an input video signal.

At this time, if the input mode is XGA, the mode detector 30 outputs the detection result to the graphic controller 40 without operating the first and second delays 32 and 33. In the graphic controller 40, since the same resolution mode of the monitor is input, the video signal is immediately output to the LVDS 17 without converting the resolution.

Next, if the input mode is VGA, the resolution is converted to the same as XGA. Therefore, the mode detector 30 outputs the detection result to the graphic controller 40 without operating the first and second delays 32 and 33. do. The graphic controller 40 converts the resolution and outputs a video signal to the LVDS 17.

Finally, when it is determined that the mode input from the mode detector 30 is SVGA, the detection result is output to the graphic controller 40 and the first and second delays 32 and 33 are operated. The graphic controller 40 performs the same operation as when inputting the VGA mode.

The operation of the first delay 32 and the second delay 33 will now be described.

First, in order to implement the screen in the center of the monitor, the margin of the 24 pin cell on the right side as shown in FIG. 8a and the margin of the 18 lines on the lower side should be made equal to the top, bottom, left and right sides as shown in FIG. 8b. To do this, the horizontal and vertical synchronization signals are slightly delayed.

That is, the vertical synchronization signal is delayed by the time when the upper 9 lines of the screen are written and then output through the first delay 32, and the horizontal synchronization signal is delayed by 12 pixels and then output through the second delay 33. . Accordingly, by displaying the video signal output from the graphic controller 40 on the LCD panel 11 in accordance with the synchronization of the output vertical synchronization signal and the horizontal synchronization signal, the screen can be implemented in the center of the monitor as shown in FIG. 8B.

(III) Third, an interface device of the OSD signal will be described.

10 is a block diagram showing an interface device of an on-screen display signal in the liquid crystal display monitor according to the present invention.

The on-screen display unit 6 is connected with a level converter 35 that adjusts the output OSD signal to be equal to the voltage level of the video signal, and muxes the input video signal and the OSD signal output from the level converter 35. The mux 14 is connected to the level converter 35.

The operation of the present invention configured as described above will be described in detail.

As described in the prior art, the peak-peak voltage of the input video signal and the OSD signal are different. In the present invention, the voltage level of the OSD signal is converted to match the magnitude of the video signal without amplifying the magnitude of the video signal. That is, the level converter 35 lowers the OSD signal to 0.7V and outputs it to the mux 14.

The mux 14 outputs only a video signal because there is no OSD signal when the OSD function is not used, and when the OSD function is used, the OSD signal is used instead of the video signal at a fixed position on the screen by using the vertical synchronization signal and the horizontal synchronization signal. Mux it to print.

The mux 14 used in the present invention has a function of muxing an analog signal, and the number of lines is simple to switch the analog signal.

(IV) Fourth, the brightness control function will be described.

11 is a circuit diagram showing in detail the clamp 15 of FIG.

A horizontal synchronous drain is connected to a first capacitor C1 for removing the DC voltage of the video signal input from the mux 14 and a contact a between the first capacitor C1 and the output terminal of the clamp 15. The second capacitor is connected to the field effect transistor (FET) which is turned off when the horizontal synchronous signal is input to the gate so that the control voltage is not added to the gate and the source terminal of the field effect transistor (FET) to charge the DC control voltage. C2) and an operational amplifier connected to the control voltage terminal to transmit the control voltage to the + terminal of the field effect transistor (FET) source terminal and the second capacitor (C2), and perform impedance matching and circuit protection of the input power source ( OP1).

The brightness adjustment function of the clamp configured as described above will be described in detail.

The input video signal is removed from the DC voltage by the DC blocking capacitor C1, and the operational amplifier OP1 connected to the control voltage input terminal transfers the control voltage to the field effect transistor (FET) source terminal and the terminal of the capacitor (C2). do. The operational amplifier OP1 performs impedance matching and circuit protection of the input power.

The control voltage, which is the output signal of the operational amplifier OP1, is charged by the capacitor C2, and the control voltage is transmitted to the source terminal of the field effect transistor FET.

At this time, the horizontal synchronous signal input terminal is connected to the gate of the field effect transistor (FET), so that when the horizontal synchronous signal is input, the field effect transistor (FET) is turned off so as not to add a DC control voltage to the horizontal synchronous signal. do. Therefore, if the horizontal synchronization signal is not input, the DC control voltage is added to the video signal and output.

As the DC signal is added to the video signal, the brightness of the screen displayed on the monitor becomes brighter.

(V) Fifth, the process of performing the contrast function in contrast.

12 is a detailed circuit diagram of the analog / digital converter 20 for explaining the contrast adjustment function.

The analog / digital converter of the analog-to-digital converter 20 converts the video signal input from the clamp 15 into a digital signal. The input terminals V _TOP and V for indicating the highest and the lowest voltages for controlling the operating range. _BOTTON ), and there is a video signal input terminal (V _IN ).

The highest convertible voltage input terminal (V _TOP ) is connected to the output terminal of the operational amplifier (OP2), the control terminal is connected to the non-inverting input terminal (+) of the operational amplifier (OP2), the inverting input terminal ( The output value of the operational amplifier OP2 is fed back to-).

The lowest voltage input terminal V _BOTTOM is connected to the output terminal of the operational amplifier OP3, and a fixed voltage is input to the non-inverting input terminal + of the operational amplifier OP3. The output value of the operational amplifier OP3 is fed back to the inverting input terminal + of the operational amplifier OP3.

The contrast function operation configured in this way will be described in detail.

First, the operation of the analog-to-digital converter is briefly described.

Analog-to-digital converter specifications are expressed in terms of the dynamic range (operating range), the number of conversion bits, and the conversion speed, which are expressed as the highest conversion voltage and the lowest conversion voltage. As the possible conversion speed of the analog / digital converter, that is, the bandwidth of the digital conversion processable input signal, the price of the analog / digital converter is very expensive, and the speed is limited. In LCD monitors, video input signals are high speed, so the cost of analog-to-digital converters is high.

Conventional contrast adjustment does not use the dynamic function built into the analog / digital converter 20, and changes the amplitude of the input video signal by using a high-performance amplifier for a high-speed video signal, thereby outputting the output value of the analog / digital converter. Was adjusted.

In the present invention, the contrast is adjusted using the dynamic function of the analog-to-digital converter.

Adjusting the operating range of the analog-to-digital converter adjusts the highest voltage value while keeping the lowest voltage fixed. At this time, the variable range of the highest voltage value is 2.2V The lowest voltage, which is 3.5V and a fixed voltage, is 0.4V.

When the video signal input to the analog-digital converter 20 is input in the same size as that of FIG. 13a, the user can adjust the maximum voltage value to 3.5V and look at the size of the video signal as follows. When the input video signal is represented as a 4-bit digital value, it is a signal having a size of 0111.

The input video signal does not change, and when the user adjusts the peak voltage value to 2.2V to adjust the contrast value, the video signal input to the analog-to-digital converter has a lower peak voltage value so that the video signal is relatively large. . That is, as shown in FIG. 13B, the input video signal is determined to be 1111 and output from the analog / digital converter.

That is, by adjusting the highest voltage value of the analog-to-digital converter, the size of the video signal can be adjusted without amplifying the input video signal.

(VI) Sixth, the power saving mode execution function will be described.

The microcomputer of the computer (not shown) determines whether or not a signal is input from an external device, that is, from a keyboard or a mouse (S10).

First, a case where a signal is input in the above-described step S10 will be described (S20).

Check whether the current power saving mode or normal mode (S21). If the current power saving mode, the signal is input from the external device to switch to the normal mode (S22). Then, the counter value is set to 0 (S23).

In step S21, if the signal is not input from the external device during the normal mode, the counter value is set to 0 (S23) and the normal mode is performed.

Next, a case where no signal is input in the above-described step S10 will be described (S30).

If a signal is not input from an external device, it is checked whether it is a power saving mode or a normal mode (S31). Since the signal is not input from the external device in the current power saving mode, the device continues to perform the power saving mode and checks for signal input (S10).

If the signal is not input from the external device in the normal state other than the current power saving mode in step S31, the counter value is increased (S32). If the counter value is greater than N, which is a predetermined time (S33), the user does not use the computer, and thus the power saving mode is switched (S34).

In order to perform the power saving mode S34, the computer does not output horizontal and vertical synchronization signals and video signals to the LCD monitor.

The microcomputer 30 of the LCD monitor recognizes the power saving mode when the horizontal and vertical synchronous signals and the video signals are not input from the video card of the computer, and may determine whether the video signals and the horizontal and vertical synchronous signals are input. Leave all the power at 30 and cut off all power.

If the LCD monitor goes into the power saving mode immediately without going through several steps like the CRT monitor, the screen playback time is not long.

CRT monitor takes a long time to refresh the screen when the power is turned off and then on again due to the heating time of the heater. However, LCD monitors rarely take the time to refresh the screen because they are different from CRT monitors.

Therefore, as described above, if a signal from an external device is not input for a predetermined time, the power is immediately turned off.

If a signal is inputted from an external device in the power saving mode, it will return to normal mode.

As described above, according to the flat panel display apparatus of the present invention, when a video signal having a different resolution is input to the monitor, the video signal having a different resolution can be displayed on the flat panel display apparatus by converting the video signal to a resolution suitable for display on the monitor. The screen is displayed at the center of the monitor when the SVGA mode is input by delaying the horizontal sync signal and the vertical sync signal to avoid asymmetrical top, bottom, left and right margins of the monitor as it does not have the same resolution as XGA. By mixing the analog video input signal and the analog OSD signal whose voltage level is converted, the complexity of the structure can be avoided, and the brightness can be more clearly controlled by adding a DC voltage to the input video signal.

In addition, by adjusting the operating range of the analog / digital converter to relatively determine the magnitude of the input video signal, the contrast of the video signal can be adjusted on the monitor. The power consumption can be reduced by performing a power saving mode that cuts off all power of the monitor except the power of the microcomputer that can know the history of the synchronization signal.

Claims (20)

A flat panel display device which receives a R. G. B. signal and a synchronization signal from a video card of a computer and displays the same on a panel, the flat panel display device comprising: a signal amplitude adjusting unit for amplifying an RGB signal output from a computer to a predetermined size and removing noise; Mux means for converting the on-screen display signal output from the on-screen display to be equal to the voltage level of the video signal which is the output signal of the signal amplitude adjusting unit to mux the level-converted on-screen display signal and the RGB signal; A clamp for adjusting the brightness of the video signal output from the mux means; An analog / digital converter for converting the video signal output from the clamp into a digital signal and simultaneously performing a contrast function for adjusting contrast; A microcomputer that receives the sync signal to determine a mode and performs overall control of the system; And a resolution converter configured to convert a video signal output from the video signal processor to a resolution suitable for display on a monitor and to output the output signal to a panel when the mode of the video signal input from the microcomputer is determined. The method of claim 1, wherein the adjusting of the contrast value; When the maximum voltage value of the analog / digital converter is lowered, the input video signal is determined to be a relatively large signal, and the contrast value is increased. When the maximum voltage value is increased, the input video signal is determined to be a relatively small signal and the contrast value is increased. A flat panel display device characterized by being smaller. The flat panel of claim 1, further comprising a digital / analog converter configured to sample the video signal output from the clamp by setting a frequency and a phase of a clock of the output signal of the first divider of the resolution converter. Display device. The apparatus of claim 1, wherein the resolution converter comprises: a graphic controller configured to temporarily store an RGB signal output from the analog / digital converter and output the LV signal to an LVDS; A first phase synchronization loop connected to the graphic control unit and generating a clock in which a phase and a frequency for writing to the graphic control unit are synchronized with an input video signal using a horizontal synchronization signal; A first divider connected to the first phase synchronizer loop to adjust the divided value so that a graphic mode inputted to the monitor is suitable for the monitor; A second phase-locked loop connected to the graphic controller and generating a clock in which a phase and a frequency for a read operation are synchronized to an input video signal by using a horizontal sync signal; And a second divider connected to the second phase synchronizer loop and configured to adjust a division value so that an input graphic mode is suitable for a monitor. The apparatus of claim 4, wherein the graphic controller comprises: an R signal memory unit configured to temporarily store an R signal output from the analog / digital converter; An R signal memory unit for temporarily storing a G signal output from the analog / digital converter; A B signal memory for temporarily storing the B signal output from the analog / digital converter; And a horizontal synchronous signal oscillator. The flat panel display of claim 5, wherein the R signal memory unit, the G signal memory unit, and the B signal memory unit are each composed of three line memories. The flat panel display of claim 6, wherein the writing of the respective RGB signals to each line memory comprises selecting one of three line memories according to a control signal of the microcomputer, and writing the RGB signals. . The flat panel display of claim 7, wherein a frequency value of a write clock for writing the RGB signal to a line memory is set to a value obtained by multiplying a frequency division value of the first divider by a horizontal frequency. The flat panel display of claim 6, wherein the process of reading the RGB signal from each line memory comprises selecting one of three line memories according to a control signal of the horizontal synchronous signal oscillator to read the RGB signal. . 10. The method of claim 9, wherein the RGB signal read operation reads five lines, three lines twice, and two lines at a time, eight lines since the resolution conversion ratio is 1.6 times when converting to XGA during VGA mode input. The number of lines is repeatedly increased every five lines to switch to. When converting to XGA during SVGA mode input, the resolution conversion ratio is 1.25. Therefore, one line out of four lines is read twice, and three lines are read once. And increasing the total number of lines by repeating every four lines to switch to four lines. 10. The flat panel display of claim 9, wherein a frequency value of a read clock at which the RGB signal is read from the line memory is set to a value obtained by multiplying a division frequency of the second divider by a horizontal frequency. 5. The flat panel display of claim 4, wherein the division value of the first divider which sets the frequency and the clock of the analog / digital converter is set to a horizontal signal value of the full resolution to be converted. 5. The flat panel display of claim 4, wherein the dividing value of the second divider is set to a value obtained by multiplying a dividing value of the first divider by a vertical axis conversion ratio of resolution. The method of claim 4, wherein when the SVGA mode is input during the resolution conversion, the mode detector determines the mode of the input video signal, outputs the discrimination result to the graphic controller, and controls the delay time of the first delay and the second delay. The first delay unit connected to the vertical synchronization signal input terminal of the mode detection unit delays and outputs a vertical synchronization signal for a predetermined time according to a control signal of the mode detection unit to adjust the vertical center of the screen. In the second delay connected to the signal input terminal, the horizontal synchronization signal is delayed and output for a predetermined time according to the control signal of the mode detector in order to center the left and right centers of the screen so that the top, bottom, left and right margins of the screen are symmetrical. Flat panel display, characterized in that implemented. The flat panel display of claim 14, wherein the mode detector is a microcomputer. The flat panel display of claim 1, wherein the microcomputer performs a power saving control step of shutting off all power except the microcomputer when a signal for power saving mode is input from the computer. The flat panel display of claim 16, wherein the signal for power saving mode is a signal to which a video signal and a horizontal and vertical synchronization signal are not input from the computer. 24. The method of claim 16 or 23, wherein the computer outputs a signal for power saving mode, the method comprising: determining whether a signal is input from an external device such as a keyboard or a mouse; Performing a normal mode when a signal is input from an external base in the signal input determining step; And performing a power saving mode when a signal is not input from an external device in the signal input determination step. The method of claim 18, wherein the performing of the normal mode comprises: determining whether the current mode is a power saving mode or a normal mode when a signal is input from an external device; Switching to a normal mode if it is a power saving mode in the mode determining step; And setting the counter value to 0 when the current mode is in the normal mode or the normal mode is switched. The method of claim 18, wherein the performing of the power saving mode comprises: determining whether a current power saving mode or a normal mode is present when a signal is not input from an external device; Determining whether the counter value is equal to or greater than N by increasing a counter value in the normal mode in the mode determining step; Performing a power saving mode when the counter value is greater than or equal to a predetermined time N in the counter value determining step; And performing a signal input determination step of checking whether a signal is input from the external device when the counter value is not equal to or greater than N in the power saving mode or the power saving mode in the mode determination step. Flat panel display device.