KR930007011B1 - Video data processing circuit for vga-card and card for high definition - Google Patents

Abstract

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Description

High resolution dedicated card and VGA card video data processing circuit

1 is a block diagram of a high resolution dedicated card and VGA card image data processing circuit according to the present invention.

2 is a block diagram of a decoder unit in the high resolution dedicated card and VGA card image data processing circuit according to the present invention.

* Explanation of symbols for main parts of the drawings

10: VGA card connection part 20: data part

30: buffer 40: selection

50: D / A converter 60: Monitor connection part

70: clock generator 100: clock generator circuit

FF1 ~ FF4: D type flip flop SW1: Switch

The present invention relates to a video card, and more specifically, to VGA (Video Graph).

ics Array) By expanding the video data output of the card to the number of output data bits of the dedicated high resolution card according to the clock signal of the VGA card, one multi-sync monitor can use both VGA and high resolution dedicated cards at the same time. Card and VGA card image data processing circuit.

In order to increase the sharpness of computer graphics, we use the MDA (Monchrome Display Adapter) card developed by IBM company as a starting point (GA (Color Graphics Adapter) card, EGA (Enhamced Graphics Adapter) card, VGA (Video Graphpics Array) card). Currently, high resolution dedicated cards have been put into practice, and these high resolution dedicated cards have a dedicated GSP (Graphic Signal Processor) to perform separate memory configurations and graphics operations. In this case, the MDA, CGA, EGA, and VGA cards are referred to as standard cards. Generally, computers compatible with IBM computers do not use the standard cards. In this state, the high resolution dedicated card cannot be used. It is configured to operate at power-on assuming that the standard card is mounted.

To be more specific, the compatible models of IBM computers check in the self-test part whether the basic input output (Basic Input Output) embedded in their ROM is basically equipped with MDA / CGA or EGA / VGA card. After the MDA / CGA card is installed, the memory of the MDA / CGA is tested, or when the EGA / VGA card is loaded, the program of EPROM configured outside the EGA / VGA card is loaded and the command is executed.

Therefore, if the standard card is not used in the compatible model of the IBM computer, the initial state of the computer and the message output cannot be read and cannot be used.

In order to use a high-definition dedicated card in a compatible model of the IBM computer, there is a problem that the high-definition dedicated card should perform the same or similar operation of the standard card.

In order to solve this problem, conventionally, the ASIC needle of a VGA card is embedded in a high resolution dedicated card.

That is, the conventional solution is configured by combining a high-definition dedicated card and a VGA card into one video card, so that the initial state problem in the compatible models of IBM computers can be solved by the VGA card combined with the video card.

However, in the case of a computer that was originally equipped with a VGA card, such a method is to add another VGA card in order to use a high resolution dedicated card, resulting in an economic burden on the user.

In addition, simultaneously configuring a high-definition dedicated card and VGA card in one video card is very complicated in hardware, which is also a cause of the increase in unit price.

Of course, if the computer is equipped with a VGA card, if the additional high-definition dedicated card is added, the initial state of the computer can be solved, the resolution and frequency of the VGA card resolution and frequency of the high-definition dedicated card is different from the resolution In order to do this, the user must separately install the monitor for the high-definition dedicated card and the monitor for the VGA card, which is also a problem that brings economic burden to the user.

The present invention has been made to solve this problem, and an object of the present invention is to extend the video data of the VGA card applied to the D / A converter to the decoder in the same way as the number of bits of the video data output from the high-definition dedicated card. VG using the monitor

It is to provide high resolution dedicated card and VGA card video data processing circuit that can use A card and high resolution dedicated card.

A feature of the present invention for achieving this object is connected to the VGA card and outputs the video data, clock, blank signal, and horizontal and vertical synchronization signal of the VGA card and: VGA card connection is connected to the A decoder which outputs the video data of the VGA card connection unit by extending the number of bits according to a clock, a buffer connected to a high resolution dedicated card and configured to output the image data output of the high resolution dedicated card, and the VGA card connection unit; And a blank signal horizontal, vertical synchronous signal or a main blanking signal, a main horizontal and a main synchronous signal of the high resolution dedicated card are selectively output as a blanking signal sync signal and a composite synchronous signal according to a selection signal. A selection unit; A clock oscillation circuit for oscillating by selectively inputting a VGA clock or a high resolution clock according to a selection signal to output a load clock and a clock; The decoder is connected to the buffer selector and the clock generation circuit, and the image data of the decoder and the buffer are input according to the load clock of the circuit and the R.G.B. A D / A converter converting the color signal and outputting the color signal according to a clock of the oscillation circuit; A high resolution dedicated card and a VGA card image connected to the selector and the D / A converter, and a monitor connector configured to apply the RGB signal of the D / A converter to the multi-sync monitor according to the composite synchronization signal of the selector. It is in the data processing circuit.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a high-definition dedicated card and VGA card image data processing circuit according to the present invention, the VGA card connection unit 10, decoder unit 20, buffer 30, selector 40, D / A conversion The unit 50, the monitor connection portion 60 and the oscillation arc (100). More specifically, the card connection unit 10 is connected to the VGA card and a cable to match the image data (D1 ~ D7) applied from the dynamic RAM inside the VGA card to the reference clock CK1. Will print.

The VGA card connector 10 is configured to output blank signals BLANK, horizontal and vertical synchronization signals H-SYNC, and V-SYNC of the VGA card. The decoder 20 is connected to the VGA card connecting unit 10 and outputs the image data D0 to D7 of the VGA card connecting unit 10 by extending the number of bits according to the clock CK1. Likewise, it is composed of D type flip flops (FF1 to FF4).

In this case, the D-type flip-flops FF1 to FF4 are driven according to the selection signal SEL1 applied to the terminal 18, and when the first clock is applied to the terminal 17, through the terminals 1 and 8. The input data is output through the terminals 9 and 16 and applied to the terminals 2 and 7. When the second clock is applied to the terminal 18, the D flip-flop FF1 to FF4 outputs the data applied to the terminals 2 and 7 through the terminals 10 and 15. To (3) and (6). The D-type flop flops FF1 to FF2 output data applied to the terminals 3 and 6 through the terminals 11 and 14 when the third clock is applied to the terminal 18. 4) and (5). The D flip-flops FF1 to FF2 output data applied to the terminals 4 and 5 through the terminals 12 and 13 when the fourth clock is applied to the terminal 18. When the fifth clock is applied to the terminal 18, the D-type flip-flops FF1 to FF4 sequentially perform the same process as when the first clock is applied to the terminal 18.

At this time, the decoder 20 causes the data D0 to D7 of the VGA card connection unit 10 to be applied to the terminals 1 and 8 of the flip-flops FF1 to FF4. Then, the buffer 30 is connected to a high resolution dedicated card (not shown) and outputs the image data D0 to D31 waveforms of the high resolution dedicated card. The selection unit 40 is connected to the VGA card connection unit 10 and is driven according to the selection signal SEL1 so that the blank signal BLANK and the horizontal vertical synchronization signal H− of the VGA card connection unit 10 are driven. SYNC), (V-SYNC) or main blank signal (M-BLANK), main horizontal, vertical synchronization signal (MH-SYNC), (M of the high resolution dedicated card.

V-SYNC) is selectively input to output the blank signal BLANK2, the sync signal SYNC, and the composite synchronous signal C-SYNC. The clock generation circuit 100 which oscillates by selectively inputting the VGA clock VGACK or the high resolution clock MAIN CK according to the selection signal SEL1 to output the load clock LK and the clock CK2 is performed. A switch SW1 which is switched according to the selection signal SEL1 and selectively inputs a VGA clock VGA or a high resolution clock MAIN CK, and is connected to the switch SW1, and is connected to the switch SW1. The clock generator 70 outputs the clock CK2 and the load clock LK according to the VGA clock VGA CK or the high resolution clock MAIN CK. In addition, the A / D converter 50 connected to the decoder 20, the buffer 30, the selector 40, and the clock generation circuit 100 is an image of the decoder 20 and the buffer 30. The data D0 to D31 are converted into RGB color signals according to the blank signal BLANK2 and the sync signal SYNC of the selector 40 and output according to the clock CK2 of the clock generation circuit 100. In addition, the monitor connection unit 60 is connected to the selector 40 and the D / A converter 50 to input an RGB color signal of the D / A converter 50 to input the composite synchronous signal of the selector 40. To the multi-sync monitor according to (C-SYNC).

In the high resolution dedicated card and the VGA card image data processing circuit according to the present invention, the selection signal SEL1 is set to a low level so that the VGA mode is basically used, and the selection signal SEL1 is used whenever a high resolution program is used. Is converted to high level and VGA mode will be completed after this process is completed. This is done by a program built into the board. Therefore, in the VGA mode, the VGA card receives the image data D0 to D7, the clock CK1, and the horizontal and vertical synchronization signals H-SYNC and V-SYNC through the VGA card connector 10. Will print. At this time, since the D / A converter 50 configured according to the present invention is configured to input 32-bit image data D0 to D31, the image data D0 to D7 of the VGA card connection unit 10 is expanded to 32 bits. Needs to be. To this end, the present invention constitutes a decoder unit 20. The decoder unit 20 has the data D0 input to the terminal 1 of the flip-flops FF1 to FF4 as shown in the following table. When this is applied, it is output through the terminal 9 and input to the terminal 2. The data D0 input to the terminal 2 is output through the terminal 10 when the second clock CK is applied, and is applied to the terminal 3. The data D0 applied to the terminal 3 is output through the terminal 11 and applied to the terminal 4 when the third clock CK is applied. The data D0 applied to the terminal 4 is outputted through the terminal 12 when the fourth clock CK is applied. At this time, the data D1 applied to the terminals 8 of the flip-flops FF1 to FF4 is output through the terminal 16 when the first clock CK is applied, and is applied to the terminal 7. The data D1 applied to the terminal 7 is output through the terminal 15 when the clock CK is applied to the second clock, and is applied to the terminal 6. Then, the data D1 applied to the terminal 6 is output through the terminal 14 when the third clock K1 is applied, and is applied to the terminal 5. The data D1 applied to the terminal 5 is output through the terminal 13 when the fourth clock CK is applied.

At this time, the table described only the data (D0), (D1) applied to the D-type flip-flop (FF1 ~ FF4), but the data (D2 ~ D7) output from the VGA card connection unit 10 is a D-type flip The decoder 20 applies 8-bit VGA card image data D0 to D7 to 32-bit image data because it is applied to terminals 1 and 8 of the flops FF2 to FF4. Is to expand to (D0 ~ D31). In addition, the selector 40 may include a blank signal BLANK, a horizontal vertical synchronous signal H-SYNC, a V-SYNC, or a high resolution dedicated card of the VGA card connector 10 by a selection signal SEL. After inputting the main blank signal (M-BLANK), horizontal and vertical synchronization signal (MH-SYNC) and (MV-SYNC) selectively, the blank signal (BLANK2), synchronization signal (SYNC) and composite according to the input signal Output the synchronization signal C-SYNC.

At this time, the selection signal SEL1 also affects the switch SW1 so that the switch CW1 is switched in accordance with the selection signal SEL1 to be output from the VGA clock VGACK outputted from the VGA card or the dedicated high resolution card. By selectively transmitting the main clock MAINCK to the rear end, the oscillator 70 connected to the switch SW1 divides (classifies) the frequency according to the clock signal selected by the switch SW1 and load clock LK and The clock SK2 is output. The 32-bit image data D0 to D31 output from the high resolution dedicated card are output after the waveform is shaped in the buffer 30. In addition, the D / A converter 50 connected to the decoder 10 and the buffer 30 may store the 32-bit image data D0 to D31 output from the decoder 10 or the buffer 30. 8 bits are input through the terminals DA, DB, DC, and DD according to the load clock LOAD CK of the clock generator 70. The decoder 50 receives the input image data D0 to D31 from the blank signal BLANK2 sync signal SYNC and the clock signal CK2 of the clock generator 70. By converting the RGB color signal to the monitor connection unit 60.

At this time, the monitor connection unit 60 is a composite synchronous signal (C-SUNC) is applied from the selection unit 4, the monitor connection unit 60 is the RGB color signal according to the composite synchronous signal (C-SYNC) Is applied to the multi-sync monitor. That is, the present invention converts the 8-bit image data D0 to D7 output from the VGA card connection unit 10 into the 32-bit image data D0 to D31 in the detoder unit 20. When the image data D0 to D31 of the decoder unit 20 and the image data D0 to D31 of the high-definition dedicated card are converted into an RGB color signal by the D / A converter 50, the selection is performed. The unit 40 and the clock generation circuit 100 apply the blank signal BLANK2, the sync signal SYNC, the clock CK2, and the load clock LK according to the image data of the VGA card or the high resolution dedicated card. .

In addition, when the RGB color signal of the D / A converter 50 is applied to the multi-sync monitor by the monitor connection unit 60, the composite synchronization signal C-SYNC according to the VGA card or the high-resolution dedicated card of the selector 40. Synchronization is controlled by) so that you can use VGA card and high resolution dedicated card with one multi-sync monitor.

As described above, the high-definition dedicated card and the VGA card image data processing circuit expand the 8-bit image data output from the VGA card to 32-bit image data using the decoder unit. And there is an effect that can use a high-definition dedicated card.

Claims (2)

VGA card connection unit which is connected to the VGA card and outputs the image data D0 to D7, the clock CK1 blank signal BLANK, and the horizontal and vertical synchronization signals H-SYNC and V-SYNC. 10) and a decoder unit 20 connected to the VGA card connection unit 10 for outputting the image data D0 to D of the VGA card connection unit 10 by extending the number of bits according to the clock CK1. And a buffer 30 connected to the high resolution dedicated card and configured to output the image data D0 to D31 of the high resolution dedicated card and the VGA card connecting unit 10 and the VGA card connecting unit 10. Blank signal (BLANK1) of horizontal vertical synchronous signal (H-SYNC), (V-SYNC) or main blank signal (MBLANK), main horizontal, vertical synchronous signal (MH-SYNC) of the high resolution dedicated card A selector 40 which selectively inputs according to SEL) and outputs a blank signal BLANK2, a sync signal SYNC, a MV-SYNC, and a compound synchronous signal C-SYNC, and a select signal A clock generation circuit 100 for selectively outputting a load clock LOADCK and a clock CK2 by selectively inputting a VGA clock VGACK or a high resolution clock MAIN CK according to SEL1, and the decoder 20 Is connected to the buffer 30, the selector 40, and the clock generation circuit 100, and loads the image data D0 to D31 of the decoder 20 and the buffer 30 to the clock generation circuit 100. Input according to the clock LOADCK and convert the RGB color signal according to the blank signal BLANK2 of the selector 4 and the sync signal SYNC and output according to the clock CK2 of the clock generation circuit 100. It is connected to the A converter 50, the selector 40 and the D / A converter 50, and converts the RGB signal of the D / A converter 50 into the composite synchronous signal of the selector 40. High-definition dedicated card and VGA card image data processing circuit, characterized in that consisting of a monitor connection unit 60 applied to the multi-sync monitor according to (C-SYNC). The video data processing circuit of claim 1, wherein the decoder unit comprises one or more D flip-flops for delaying and outputting input data according to a clock signal.

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