CN201623760U

CN201623760U - 3G-SDI high-definition digital video frame synchronizer

Info

Publication number: CN201623760U
Application number: CN2009202884603U
Authority: CN
Inventors: 周春雷; 刘兴华
Original assignee: DALIAN KEDI VIDEO TECHNOLOGY Co Ltd
Current assignee: DALIAN KEDI VIDEO TECHNOLOGY Co Ltd
Priority date: 2009-12-25
Filing date: 2009-12-25
Publication date: 2010-11-03
Anticipated expiration: 2019-12-25

Abstract

The utility model relates to a 3G-SDI high-definition digital video frame synchronizer, comprising a synchronization separator (1), a clock generator (2), a frame memory (3), an FPGA chip (4), an indicating and control unit (5), a serializer (6), a deserializer (7) and a power supply (8), wherein the synchronization separator (1) is connected with the FPGA chip (4) and the clock generator (2); the frame memory (3), the indicating and control unit (5), the serializer (6), the deserializer (7) and the power supply (8) are connected with the FPGA chip (4). The digital video frame synchronizer overcomes the phenomena of time base errors or dithering caused by different signal sources or different transmission paths under the signal transmission rate of 3Gbps, and provides more accurate and more convenient modes to solve the problems of dithering, distortion, asynchronization, unstable station caption superposition and the like in switching video images.

Description

3G-SDI high-definition digital video frame synchronizer

Technical field

The utility model belongs to the video and audio frequency technology applications field in the electronic information field, relates to a kind of digital video frame synchronizer.

Background technology

3G-SDI (serial digital interface of 3Gbps transmission rate) vision signal is the top signal format of main flow in present and even following several years radio and television and the broadcasting media industry, and its signal pattern quality and audio quality can fully satisfy professional radio and television and popular specialty or amusement needs.Meanwhile, the transmission standard of 3G-SDI signal is also much higher than the standard of HD-SDI (serial digital interface of high definition) signal and SD-SDI (serial digital interface of single-definition) signal, its signal transmission rate is 2.97Gbps, being 2 times of transmission rate in the HD-SDI signalling channel, is 11 times of transmission rate in the SD-SDI signalling channel.Because of its signal frequency height, the shake of 3G-SDI video signal generating is difficult to control more, also is difficult to realize the normal shaking phenomenon that produces the video pictures switching because of signal is asynchronous between signal synchronously.

Summary of the invention

The utility model designs a kind of 3G-SDI digital video frame synchronizer at the problems referred to above, and its purpose is intended to utilize the 3G-SDI treatment technology to design a kind of full HD digital video frame synchronizer.It can be proofreaied and correct under the signal transmission rate of 3Gbps because time base error or the shake that different signal source or different transmission paths cause, and provides more accurate, mode solves video image and switches problems such as shake, distortion, asynchronous, station symbol superposition instability more easily.Make and realize multi-channel video signal genlock switching between each signal non-jitter, signal interruption and do not occur black when meeting an urgent need switching.

To achieve these goals, the technical solution of the utility model is: 3G-SDI high-definition digital video frame synchronization system comprises sync separator 1, clock generator 2, frame memory 3, fpga chip 4, indication and control unit 5, serializer 6, deserializer 7 and power supply 8.Sync separator 1 is connected with fpga chip 4 and clock generator 2, and frame memory 3, indication and control unit 5, serializer 6, deserializer 7 and power supply 8 all are connected with fpga chip 4.

Sync Separator Chip 1 is LMH1981; Clock generator 2 is LHM1982 or GS4911; Frame memory 3 is FIFO (first-in first-out) storage chip as the buffer of digital video frame data, SDRAM (Synchronous Dynamic Random Access Memory) or DDR (double-speed internal memory) chip.

The beneficial effects of the utility model are: this digital video signal frame synchronizer is core with FPGA, by writing to its inside IP kernel, can realize frame synchronization process to the 3G-SDI digital video signal, and compatible HD-SDI and SD-SDI signal, can precisely contrast H, the V signal sync rates of reference signal and synchronizing signal, the clock jitter that can keep exporting synchronizing signal reaches the SMPTE required standard less than 0.2UI; FPGA inside has measuring ability, can detect the mistake of data in delegation's vision signal, makes this frame synchronization system can keep stable non-jitter picture output; The signal of exportable multi-mode, multi-format; On the basis of this treatment system, only need simple A/D of increasing and D/A conversion module, just can realize frame synchronization process function analog signal.

Description of drawings

Fig. 1 is the structure chart of 3G-SDI digital video frame synchronizer;

Fig. 2 is the front portion of 3G-SDI digital video frame synchronizer pictorial diagram;

Fig. 3 is the back portion of 3G-SDI digital video frame synchronizer pictorial diagram.

Embodiment

Below in conjunction with the drawings and specific embodiments the utility model is elaborated, but be not limited to embodiment.

As shown in Figure 1,3G-SDI digital video frame synchronizer comprises sync separator 1, clock generator 2, frame memory 3, indication and control unit 5, serializer 6, deserializer 7, power supply 8 and system handles core FPGA chip 4.Sync separator 1 is connected with fpga chip 4 and clock generator 2, and frame memory 3, indication and control unit 5, serializer 6, deserializer 7 and power supply 8 are connected with fpga chip 4.

Below according to Fig. 1, operation principle of the present utility model made specify:

At first, digital video signal is gone here and there the parallel data that conversion process also is converted to multidigit through balanced and deserializer 7 and is inputed to fpga chip 4, fpga chip 4 carries out separated in synchronization to it to be handled, isolate H, V signal, the initial signal of the every two field picture of algorithm identified by inside generates data in view of the above and deposits mechanism in; Fpga chip 4 is according to depositing data mechanism in, deposits vision signal in the frame memory 3 specified address.

Secondly, reference signal inputs to be isolated H, V signal and flows to fpga chip 4 and clock generator 2 respectively in the sync separator 1,2 couples of H of clock generator, V signal carry out phase-locked: its clock is alignd with H, V signal and produce the clock rate of 3 kinds of different frequencies (SD form 27MHz, high-definition format 74.25MHz and 3G form 148.5MHz), and input to fpga chip 4;

Then, in fpga chip 4, for reading mechanism, and from frame memory 3, read vision signal according to the clock rate of sending by clock generator 2 with reference to generating according to the H of reference signal, V signal; At this moment, 4 pairs of video signal detection of reading of fpga chip, SAV (effective video beginning flag) and EAV (effective video end mark) in the digital video signal that reads out by detection, whether judgement mistake occurs in this frame synchronization process process, contrast H, the V signal of supplied with digital signal and reference signal simultaneously, guarantee the accurate of frame synchronization process;

If will carry out relevant treatment to the embedding audio frequency in the digital video signal, fpga chip 4 can this step to the Parallel Digital audio frequency (analogue audio frequency is after the A/D conversion) embed, wipe, relevant treatment such as quiet, mixing, adjustment.

At last, the parallel digital video signal of handling is sent to serializer 6 carries out and go here and there conversion process, finally export the SDI digital video signal.

This processor can carry out frame synchronization process up to the full HD digital video signal of 3Gbps to transmission rate, and compatible HD-SDI and SD-SDI signal, can stablize to keep picture to switch non-jitter.

Sync Separator Chip 1 can be used LMH1981, and the reference signal form that can handle has: composite video signal, the y/c signal of S terminal, the VGA signal of component video signal and computer video interface.

Clock generator 2 can use LHM1982 or GS4911, export the clock rate of 3 kinds of standards simultaneously: the clock rate of the clock rate of SD form 27Mbps, the clock rate of high-definition format 74.25Mbps and 3G form 148.5Mbps, make the clock rate of synchronizing signal more accurate, reduce to minimum with the error of reference signal.

Frame memory 3 can use FIFO (first-in first-out) storage chip as the buffer of digital video frame data, SDRAM (Synchronous Dynamic Random Access Memory) or DDR (double-speed internal memory) chip etc.;

Indication and control unit 5 be system to outer connection part, operating personnel controlling the processing category of whole system, and obtain the feedback of system information by this part by indicating section;

Parallel/serial or the serial/parallel conversion of serializer 6 and 7 pairs of digital video signals of deserializer is handled, can support the chip of 3G-SDI serial signal, and be provided with the logical function of outage ring, if unexpected power down is arranged, digital video signal will directly output on the monitor, improve reliability.

Power supply 8 is whole 3G-SDI digital video frame synchronizer power supply.

The utility model adopts the frame synchronization process of supporting the full HD vision signal of 3Gbps, and compatibility is to the HD-SDI Signal Processing of SD-SDI signal and the 1.485Gbps of 270Mbps, this system supports composite signal or component signal as reference signal, and form that can processing signals has: NTSC, PAL, SECAM, 480i/p, 576i/p, 720p and 1080i/p.

Fig. 2 is the front view of the utility model embodiment outward appearance: behind the power-up initializing, by to 4 directionkeys operations of control panel selection function, press the ENTER key and confirm, press LCOK key lock operation.There are 2 video special function keys in the directionkeys left side, respectively the SDI vision signal is carried out direct control; 1 audio frequency special function keys and 3 status indicator lamps are arranged, show the mode of operation of current this system audio frequency.This system is furnished with the VFD display screen, mode of operation that can the display frame synchronization device.

Fig. 3 is the rear view of the utility model embodiment outward appearance: the input of 1 road 3G-SDI signal is arranged, the output of 1 road 3G-SDI signal loop, the output of 2 road 3G-SDI signals; If unexpected power down, system will directly connect SDI and input in 1 road SDI output, avoid occurring picture and interrupt, and improve reliability more.

Claims

1.3G-SDI high-definition digital video frame synchronizer, it is characterized in that, it comprises sync separator (1), clock generator (2), frame memory (3), fpga chip (4), indication and control unit (5), serializer (6), deserializer (7) and power supply (8), sync separator (1) is connected with fpga chip (4) and clock generator (2), and frame memory (3), indication and control unit (5), serializer (6), deserializer (7) and power supply (8) all are connected with fpga chip (4).

2. 3G-SDI high-definition digital video frame synchronizer according to claim 1 is characterized in that the model of described Sync Separator Chip (1) is LMH1981; The model of described clock generator (2) is LHM1982 or GS4911; Described frame memory (3) is FIFO (first-in first-out) storage chip, SDRAM (Synchronous Dynamic Random Access Memory) or DDR (double-speed internal memory) chip.