CN109039335A - A kind of realization device and implementation method that audio A/D conversion chip array frame clock is synchronous - Google Patents
A kind of realization device and implementation method that audio A/D conversion chip array frame clock is synchronous Download PDFInfo
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- CN109039335A CN109039335A CN201810606617.6A CN201810606617A CN109039335A CN 109039335 A CN109039335 A CN 109039335A CN 201810606617 A CN201810606617 A CN 201810606617A CN 109039335 A CN109039335 A CN 109039335A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
- H03M1/1255—Synchronisation of the sampling frequency or phase to the input frequency or phase
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
- H03M1/1285—Synchronous circular sampling, i.e. using undersampling of periodic input signals
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- Synchronisation In Digital Transmission Systems (AREA)
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Abstract
Present invention discloses a kind of synchronous realization device of audio A/D conversion chip array frame clock and implementation methods, by on the basis of existing audio A/D conversion chip, before chip life's work, by way of multiplexing audio output signal pin and increasing LRCK synchronization frequency division counting processing unit, it realizes the synchronization in array between the inside LRCK signal of each audio ADC chip, and then finally realizes the synchronization between each sound channel of audio ADC chip each in audio ADC chip array.
Description
Technical field
The present invention relates to a kind of audio A/Ds to convert (ADC) chip array, converts core more particularly, to a kind of audio A/D
The synchronous realization device of chip arrays frame clock and implementation method.
Background technique
With the high speed development of speech recognition technology, (Analog-to-digital converter simulates number to audio ADC
Word converter) chip has been more and more widely used in the field.Relatively high speech recognition application field is required some,
The form for needing that multiple audio ADC integrated chips get up to be formed an array (commonly referred to as microphone array), to improve language
The effect of sound identification.
The integration mode of audio ADC chip array is varied, common are two class integration modes.1st class is will be each
The output audio serial data signal line of audio ADC chip is integrated in a shared voiceband data signal line in a manner of tri-state
On, then each audio ADC chip timesharing occupies the shared voiceband data signal line of this root, as shown in fig. la；2nd class is each
Audio ADC chip includes an audio data input signal line and an audio data output signals line, then by previous stage sound
The audio output signal line of frequency ADC chip is connected on the audio input signal line of rear stage audio ADC chip, is passed one by one
It passs down, is passed finally by the audio output data signal line of afterbody audio ADC chip, as shown in figure ib.
Organizational form of each audio ADC channel data on voiceband data signal line be also it is diversified, it is common
There are two class loading modes.1st class is that the audio data of each ADC sound channel is placed on to LRCK (left/right clock) is defeated in the period
Out, it includes to support the data receiver processing circuit of such format that such mode, which requires user's receiving side,；2nd class is an inside
The LRCK period only exports two sound channels, and interface LRCK frequency is the multiple of internal LRCK frequency, and each interface LRCK period is only defeated
Two sound channels out, multiple channel datas of multiple audio ADC chips are according to certain sequence with N number of external interface LRCK time span
It cycles through for the period (N number of external interface LRCK time span length is equal to an internal LRCK cycle length) and is received to user
Side.The advantages of audio ADC chip array of 2nd class multi-channel data organizational form is: user's receiving side does not need special number
According to receiving processing circuit, but use common stereo audio receiving processing circuit.
But for the audio ADC chip array using the 2nd class multi-channel data organizational form, in order to keep in array
The sample-synchronous of each audio ADC chip needs to solve the stationary problem in array between each each sound channel of audio ADC chip,
And the sample-synchronous of each audio ADC chip is to rely on its internal LRCK, so each audio ADC core in array will be solved
Stationary problem between the inside LRCK of piece.
Summary of the invention
It is an object of the invention to overcome the deficiencies of existing technologies, each audio ADC core in a kind of achievable array is provided
The synchronous realization device of synchronous audio A/D conversion chip array frame clock and implementation method between each sound channel of piece.
To achieve the above object, the following technical solutions are proposed: a kind of audio A/D conversion chip array frame clock by the present invention
Synchronous realization device,
Preferably, described device includes multistage connected audio A/D conversion chip, the audio A/D conversion chip packet
It includes:
Configuring interface units, for exporting LRCK synchronous control signal sync_sel；
Synchronous switch is connected with configuring interface units, for being controlled according to the LRCK synchronous control signal sync_sel
Whether the output signal of the synchronous switch is used as the inside LRCK synchronous input signal of LRCK synchronization frequency division counting processing unit
sync_ip；
LRCK synchronization frequency division counts processing unit, is connected with synchronous switch, for what is inputted to audio A/D conversion chip
External LRCK signal frequency split, and the signal after frequency dividing is used as chip interior LRCK signal i_lrck, and for based on the received
The synchronous input signal sync_ip of the synchronous switch exports the inside LRCK synchronism output used for rear stage chip synchronization
Signal sync_op；
The inside LRCK of rear stage audio A/D conversion chip previous stage audio A/D conversion chip based on the received
Synchronization output signal sync_op, it is same according to the internal LRCK as its chip interior LRCK synchronous input signal sync_ip
Input signal sync_ip and the counting target value of itself are walked, the phase of the chip interior LRCK signal i_lrck after adjusting its frequency dividing
Position, believes the chip interior LRCK of other chips in the phase and array of the chip interior LRCK signal i_lrck adjusted
Number i_lrck phase is identical.
Preferably, the audio data output signals line of each audio A/D conversion chip is integrated in a manner of tri-state
On a shared voiceband data signal line.
Preferably, each audio A/D conversion chip includes that an audio data input signal line and an audio data are defeated
Signal wire out, the audio data output signals line and rear stage audio A/D of the previous stage audio A/D conversion chip convert core
The audio data input signal line of piece is connected.
Preferably, the LRCK synchronization frequency division counts processing unit and is divided external LRCK signal according to LRCK frequency division coefficient
Frequently, the counting target value of the chip itself is identical as the LRCK frequency division coefficient.
Preferably, the audio A/D conversion chip further includes adc data processing unit and outlet selector, wherein
The input terminal of the adc data processing unit and configuring interface units and LRCK synchronization frequency division counting processing unit are equal
It is connected, output end is connected with outlet selector, for counting the inside of processing unit output according to LRCK synchronization frequency division
Simulation input audio signal is converted to digital output signal o_adcdat by LRCK signal i_lrck；
The outlet selector and LRCK synchronization frequency division count processing unit, adc data processing unit and configuration interface list
Member is connected, and the output for being exported according to configuring interface units controls signal o_sel, selects LRCK synchronization frequency division counting processing
The digital output signal o_ that inside LRCK synchronization output signal sync_op, the adc data processing unit of unit output export
One of adcdat is used as its output signal adcdat.
Preferably, it is defeated also to receive the digital serial audio that prime chip exports for the input terminal of the adc data processing unit
Signal tdmin and the same level chip analog input signal AIN out, and the outlet selector output end is connected with rear stage chip.
Preferably, the input terminal of the adc data processing unit also receives the same level chip analog input signal AIN, and institute
It states outlet selector output end while being connected with the input terminal of its own synchronous switch and rear stage chip.
Preferably, the audio A/D conversion chip further includes chip status machine and clock-reset unit, wherein
The chip status machine is connected with configuring interface units, for controlling chip at least gradually in reset initial shape
State, LRCK synchronization process working condition and normal operating conditions；
The clock-reset unit is used for after chip electrifying startup, so that chip is in the reset original state,
After external piloting control CPU completes all configurations operation of chip, chip reset is released, so that chip is introduced into LRCK synchronization process
Working condition, after chip completes LRCK synchronization process, chip is switched to normally by external piloting control CPU by configuring interface
Working condition.
A kind of synchronous implementation method of disclosed audio A/D conversion chip array frame clock, the method packet
It includes:
S1, configuring interface units export LRCK synchronous control signal；
S2, synchronous switch control the output signal of the synchronous switch according to the LRCK synchronous control signal sync_sel
Whether the inside LRCK synchronous input signal sync_ip of processing unit is counted as LRCK synchronization frequency division；
S3, LRCK synchronization frequency division count the external LRCK signal frequency split that processing unit inputs audio A/D conversion chip,
And the signal after frequency dividing is used as chip interior LRCK signal i_lrck, and the synchronization for the synchronous switch based on the received
Input signal sync_ip exports the inside LRCK synchronization output signal sync_op used for rear stage chip synchronization；
The inside LRCK of S4, rear stage audio A/D conversion chip previous stage audio A/D conversion chip based on the received are same
Step output signal sync_op, it is synchronous according to the internal LRCK as its chip interior LRCK synchronous input signal sync_ip
Input signal sync_ip and the counting target value of itself, the phase of the chip interior LRCK signal i_lrck after adjusting its frequency dividing,
Make the chip interior LRCK signal of other chips in the phase and array of the chip interior LRCK signal i_lrck adjusted
I_lrck phase is identical.
Preferably, the output signal syn_ip of the synchronous switch is according to the level of the synchronous control signal sync_sel
Carry out corresponding change.
Preferably, the outlet selector controls signal o_sel according to the output that configuring interface units export, and selects LRCK
Synchronization frequency division counts the number of the inside LRCK synchronization output signal sync_op of processing unit output, the output of adc data processing unit
One of word output signal o_adcdat is used as its output signal adcdat
Preferably, the LRCK synchronization frequency division counts processing unit when received synchronous input signal sync_ip is
When high level pulse, then its next input LRCK clock cycle counter is forced to the initial value for counting the period.
The beneficial effects of the present invention are: on the basis of existing audio A/D converts (ADC) chip, in chip life's work
Before, it multiplexing audio output signal pin and by way of increasing LRCK synchronization frequency division counting processing unit, realizes in array
Synchronization between the inside LRCK signal i_lrck of each audio ADC chip, and then finally realize and adopted in audio ADC chip array
Synchronization when with above-mentioned 2nd class output data tissue mode, in array between each each sound channel of audio ADC chip.
Detailed description of the invention
Fig. 1 is the application scenarios of an existing audio ADC chip array, and wherein Fig. 1 a is that multi-chip time division multiplexing is shared
Array chip connection type structural schematic diagram, Fig. 1 b is the array chip connection type structural schematic diagram of tandem formula；
Fig. 2 is the LRCK frequency dividing synchronization principles schematic diagram of audio ADC chip of the present invention, wherein Fig. 2 a is battle array shown in Fig. 1 a
The LRCK of column chip connection type subaudio frequency ADC chip divides synchronizing function schematic diagram；Fig. 2 b show array core shown in Fig. 1 b
The LRCK of piece connection type subaudio frequency ADC chip divides synchronizing function schematic diagram；
Fig. 3 is the synchronization principles schematic diagram that LRCK synchronization frequency division of the present invention counts processing unit, wherein Fig. 3 a is shown point
The LRCK synchronization frequency division that frequency coefficient is set as first order audio ADC chip in 4 array counts the signal of processing unit working principle
Figure, Fig. 3 b show the LRCK synchronization frequency division meter for the audio ADC chip that frequency division coefficient is set as in 4 array in addition to the first order
Number processing unit operation principle schematic diagram；
Fig. 4 is the LRCK frequency dividing synchronization principles schematic diagram of the audio ADC chip of alternative embodiment of the present invention, wherein Fig. 4 a
Synchronizing function schematic diagram is divided for the LRCK of the ADC chip of array chip connection type subaudio frequency shown in Fig. 1 a；Fig. 4 b show figure
The LRCK of the subaudio frequency ADC chip of array chip connection type shown in 1b divides synchronizing function schematic diagram；
Fig. 5 is the structural schematic diagram for the audio ADC chip that the present invention has array synchronization function；
Fig. 6 is the schematic illustration of chip status machine of the present invention.
Specific embodiment
Below in conjunction with attached drawing of the invention, clear, complete description is carried out to the technical solution of the embodiment of the present invention.
The synchronous realization device of disclosed a kind of audio A/D conversion chip array frame clock, including what is be connected
Multistage audio A/D conversion chip, as described in background technique, the connection type of multistage audio A/D conversion chip here
There are two types of general, respectively as seen in figure la and lb, it is suitable for the present invention, which is not described herein again for specific integrated morphology, can refer to
Foregoing description.
Wherein, under array chip connection type shown in Fig. 1 a, the schematic diagram of the LRCK frequency dividing synchronization structure of audio ADC chip
It is corresponding as shown in Figure 2 a, under array chip connection type shown in Fig. 1 b, the signal of the LRCK frequency dividing synchronization structure of audio ADC chip
Figure is corresponding as shown in Figure 2 b, and lower mask body is illustrated for the structure shown in Fig. 2 b.
As shown in Figure 2 b, the revealed a kind of audio A/D conversion chip with array synchronization function of the embodiment of the present invention
It include: that configuring interface units, synchronous switch and LRCK synchronization frequency division count processing unit.
Wherein, configuring interface units send over required for ADC chip operation for receiving external piloting control CPU (not shown)
Configuration information and these information are exported, the configuration information includes LRCK synchronous control signal sync_sel, may be used also certainly
Including other configurations information, such as output control signal o_sel, chip status controls signal, and clock control signal resets control letter
Number and adc data processing unit required for operation control signal etc..
The input terminal of synchronous switch is connected with configuring interface units, and receives digital serial audio output signal simultaneously
Tdmin, output end count processing unit with LRCK synchronization frequency division and are connected, and are used for the synchronization exported by configuring interface units
Whether the output for controlling signal sync_sel control synchronized switching element counts the synchronization of processing unit as LRCK synchronization frequency division
Input signal.Specifically, when synchronous switch is opened, the output signal sync_ip of synchronous switch is as LRCK synchronization frequency division meter
The synchronous input signal of number processing unit；When the switch is closed, the output signal sync_ip of synchronized switching element is synchronous to LRCK
Frequency division counter processing unit is invalid.In the present embodiment, the output signal syn_ip of synchronous switch is according to synchronous control signal sync_
Sel is changed: when synchronous control signal sync_sel is low level, sync_ip remains low level, works as sync_sel
When for high level, sync_ip then keeps identical variation timing with tdmin signal.
The input terminal that LRCK synchronization frequency division counts processing unit is connected with synchronous switch, and its input terminal is also received to audio
The external LRCK signal (i.e. LRCK signal in shown in Fig. 1 a and Fig. 1 b) and LRCK frequency division coefficient of modulus conversion chip input, use
According to the LRCK frequency division coefficient, is exported to external LRCK signal frequency split, and by the signal after frequency dividing, be used as chip interior
LRCK signal i_lrck；Synchronous input signal sync_ip for the output of synchronous switch based on the received simultaneously, output is for latter
The inside LRCK synchronization output signal sync_op, inside LRCK synchronization output signal sync_op here that grade chip synchronization uses
When exporting to rear stage chip, it is equivalent to the digital serial audio output signal tdmin of rear stage chip.Wherein, here
LRCK frequency division coefficient is generally identical as core number, and if chip-count is 4, that LRCK frequency division coefficient is 4.
The original of the synchronization between internal LRCK signal i_lrck is then realized with the array that LRCK frequency division coefficient is set as 4 below
Reason is described in detail.
Wherein, Fig. 3 a show the LRCK synchronization frequency division that frequency division coefficient is set as first order audio ADC chip in 4 array
Count the course of work of processing unit.In figure, LRCK is the input clock (i.e. external LRCK signal) of LRCK frequency division counter,
Lrck_cnt is frequency counter, and i_lrck is the rate signals after frequency dividing.First order audio ADC chip is as synchronous initiation
Side, LRCK synchronous control signal sync_sel are configured to low level, so the inside LRCK synchronous input signal of its output
Sync_ip is always maintained at low level, and lrck_cnt counter is counted according only to its clock according to the LRCK frequency division coefficient of setting, often
When lrck_cnt counter counts count to the value of frequency division coefficient -1 (when counting down to 3), it is (i.e. external to export an input LRCK
LRCK signal) clock cycle LRCK syncout pulse signal sync_op.
Fig. 3 b show frequency division coefficient and is set as other grade of audio ADC chip in 4 array in addition to the first order
The course of work of LRCK synchronization frequency division counting processing unit.Likewise, LRCK is the input clock of LRCK frequency division counter in figure,
Lrck_cnt is frequency counter, and i_lrck is the rate signals after frequency dividing.Non- first order audio ADC chip receives previous stage sound
The synchronization pulse sync_op of frequency ADC chip output, then its synchronous control signal sync_sel passes through configuring interface units quilt
It is configured to high level, so its LRCK synchronous input signal sync_ip and the synchronism output of previous stage audio ADC chip output are believed
Number sync_op is consistent, i.e. synchronous input signal sync_ip in Fig. 3 b and previous stage (as and first order) audio ADC core
The synchronization output signal sync_op of piece output is consistent.
And LRCK synchronization frequency division counts the lrck_cnt counter in processing unit and removes the dividing according to setting according to its clock
Outside frequency coefficient count, when received synchronous input signal sync_ip is high level pulse, then when next input LRCK
Clock cycle rate counter is forced to the initial value for counting the period, such as 0, naturally it is also possible to be 1 or other initial values, in the present embodiment
It is 0, as shown in figure 3b, when lrck_cnt counter counts count to the value of frequency division coefficient -1, exports an input LRCK
The synchronization output signal sync_op of clock cycle.
When synchronization output signal sync_op (the i.e. synchronous input of the same level audio ADC chip of previous stage audio ADC chip
Signal sync_ip) when keep identical changing rule with the synchronization output signal sync_op of the same level audio ADC chip, then
The same level chip LRCK synchronization frequency division counts at i_lrck signal and the prime chip LRCK synchronization frequency division counting of processing unit output
The i_lrck signal then changing rule having the same of unit output is managed, then the chip completes synchronous with prime chip.This
Sample level-by-level completes the synchronization process process of all audio ADC chips in array.
Further, as shown in figures 4 a and 4b, the revealed one kind of the embodiment of the present invention has the function of array synchronization
Audio A/D conversion chip further include: adc data processing unit and outlet selector.Fig. 4 a and Fig. 4 b respectively correspond Fig. 1 a and
The schematic diagram of the LRCK frequency dividing synchronization structure of audio ADC chip under two kinds of array chip connection types of Fig. 1 b.
Adc data processing unit is mainly used for completing simulation input audio signal to the entire place of serial audio digital signal
Reason process, including audio frequency simulation front-end processing, digital audio filtering, audio output format processing etc..
Specifically, as shown in Figure 4 b, the input terminal of adc data processing unit and configuring interface units and LRCK synchronization frequency division
It counts processing unit to be connected, and receives the digital serial audio output signal tdmin signal and the same level core of the output of prime chip
Piece analog input signal AIN, for being configured required for adc data processing unit by configuring interface units according to user demand
Parameter, the same level chip analog input signal AIN is converted into the same level chip digital serial audio output signal, then with come from
Prime chip digital serial audio output signal tdmin merges, and exports as digital serial audio output signal o_adcdat.Its
In, the inside LRCK that the i_lrck that LRCK synchronization frequency division counts processing unit output is then used as adc data processing unit to use believes
Number.
Adc data processing unit shown in Fig. 4 a is similar with adc data processing unit principle shown in Fig. 4 b, input terminal
Processing unit equally is counted with configuring interface units and LRCK synchronization frequency division to be connected, and receives the same level chip analog input signal
AIN, for parameter required for adc data processing unit being configured by configuring interface units, by the same level core according to user demand
Piece analog input signal AIN is converted into the same level chip digital serial audio output signal, exports to export for digital serial audio and believe
Number o_adcdat.
The input terminal of outlet selector counts processing unit, adc data processing unit and configuration with LRCK synchronization frequency division and connects
Mouth unit is connected, and is respectively used to receive internal LRCK synchronization output signal sync_op, digital serial audio output signal o_
Adcdat and output control signal o_sel, output end are connected with the input terminal of its own synchronous switch and rear stage chip simultaneously,
Digital serial audio output signal o_adcdat is exported, as shown in fig. 4 a, or is directly connected with rear stage chip, o_ is exported
Adcdat signal, as shown in Figure 4 b.Its multiplexing function selection for being used to complete audio output signal pin: when chip is in LRCK
When synchronization process working condition, the inside LRCK synchronization output signal sync_ of LRCK synchronization frequency division processing unit output is selected
Input of the op as audio output signal pin；When chip is in normal operating conditions, adc data processor unit is selected
Input of the audio output signal as audio output signal pin.In the present embodiment, when chip is in LRCK synchronization process work
When making state, the output adcdat signal of outlet selector is changed according to output control signal o_sel, and o_sel is worked as in setting
When signal is low level, adcdat signal is equal to the o_adcdat signal in Fig. 4 a and Fig. 4 b, when o_sel signal is high level
When, adcdat signal is equal to the sync_op signal of Fig. 4 a and Fig. 4 b.
Further, as shown in figure 5, a kind of revealed audio mould with array synchronization function of the embodiment of the present invention
Number conversion chip further include: chip status machine and clock-reset unit, wherein as shown in connection with fig. 6, chip status machine connects with configuration
Mouth unit is connected, in chip status machine, including a variety of working conditions, mainly include three working conditions: one resets initially
State, chip operating voltage progressively reaches normal working voltage under this state, and external piloting control CPU completes chip LRCK frequency dividing and synchronizes
Working status parameter setting.One LRCK synchronization process working condition, LRCK frequency dividing synchronous working state parameter configuration have operated
At later, master cpu carries out audio ADC to demultiplex bit manipulation, and chip operation state transition to LRCK divides synchronous working state,
The LRCK for completing other chips in current chip and array under this state divides synchronization process.Until chips all in array are all complete
After dividing synchronization process at LRCK, chip is switched to normal work from LRCK frequency dividing synchronous working state by external piloting control CPU
Make state.
Clock-reset unit is used for after chip electrifying startup, so that chip, which is in, resets original state, and it is main in outside
After controlling all configurations operation that CPU completes chip, chip reset is released, so that chip steps into other working conditions, tool
Body, chip is introduced into LRCK synchronization process working condition, after chip completes LRCK synchronization process, external piloting control
Chip is switched to normal operating conditions by configuring interface by CPU.
In the present embodiment, when chip is in LRCK synchronization frequency division state, two controls letter of configuring interface units output
Number sync_sel signal and o_sel signal are high level, when chip is in normal operating conditions, configuring interface units output
Two control signals sync_sel and o_sel be low level.
It is disclosed based on the synchronous realization device of above-mentioned introduced audio A/D conversion chip array frame clock
A kind of synchronous implementation method of audio A/D conversion chip array frame clock, comprising:
S1, configuring interface units export LRCK synchronous control signal；
S2, synchronous switch control the output signal of the synchronous switch according to the LRCK synchronous control signal sync_sel
Whether the inside LRCK synchronous input signal sync_ip of processing unit is counted as LRCK synchronization frequency division；
S3, LRCK synchronization frequency division count the external LRCK signal frequency split that processing unit inputs audio A/D conversion chip,
And the signal after frequency dividing is used as chip interior LRCK signal i_lrck, and the synchronization for the synchronous switch based on the received
Input signal sync_ip exports the inside LRCK synchronization output signal sync_op used for rear stage chip synchronization；
The inside LRCK of S4, rear stage audio A/D conversion chip previous stage audio A/D conversion chip based on the received are same
Step output signal sync_op, it is synchronous according to the internal LRCK as its chip interior LRCK synchronous input signal sync_ip
Input signal sync_ip and the counting target value of itself, the phase of the chip interior LRCK signal i_lrck after adjusting its frequency dividing,
Make the chip interior LRCK signal of other chips in the phase and array of the chip interior LRCK signal i_lrck adjusted
I_lrck phase is identical.
Technology contents and technical characteristic of the invention have revealed that as above, however those skilled in the art still may base
Make various replacements and modification without departing substantially from spirit of that invention, therefore, the scope of the present invention in teachings of the present invention and announcement
It should be not limited to the revealed content of embodiment, and should include various without departing substantially from replacement and modification of the invention, and be this patent Shen
Please claim covered.
Claims (10)
1. a kind of synchronous realization device of audio A/D conversion chip array frame clock, which is characterized in that described device includes more
The connected audio A/D conversion chip of grade, the audio A/D conversion chip include:
Configuring interface units, for exporting LRCK synchronous control signal sync_sel；
Synchronous switch is connected with configuring interface units, for according to LRCK synchronous control signal sync_sel control
Whether the output signal of synchronous switch is used as the inside LRCK synchronous input signal sync_ of LRCK synchronization frequency division counting processing unit
ip；
LRCK synchronization frequency division counts processing unit, is connected with synchronous switch, the outside for inputting to audio A/D conversion chip
LRCK signal frequency split, and the signal after frequency dividing is used as chip interior LRCK signal i_lrck, and for described based on the received
The synchronous input signal sync_ip of synchronous switch exports the inside LRCK synchronization output signal used for rear stage chip synchronization
sync_op；
The LRCK synchronism output of rear stage audio A/D conversion chip previous stage audio A/D conversion chip based on the received
Signal sync_op inputs letter according to the internal LRCK is synchronous as its chip interior LRCK synchronous input signal sync_ip
Number sync_ip and the counting target value of itself, the phase of the chip interior LRCK signal i_lrck after adjusting its frequency dividing, make to adjust
The phase of the chip interior LRCK signal i_lrck afterwards is identical as previous stage chip interior LRCK signal i_lrck phase.
2. realization device according to claim 1, which is characterized in that the LRCK synchronization frequency division count processing unit according to
LRCK frequency division coefficient will the external LRCK signal frequency split, the counting target value of the chip itself and the LRCK frequency division coefficient
It is identical.
3. realization device according to claim 1, which is characterized in that the audio A/D conversion chip further includes ADC number
According to processing unit and outlet selector, wherein
The input terminal of the adc data processing unit and configuring interface units and LRCK synchronization frequency division counting processing unit are homogeneous
Even, output end is connected with outlet selector, for counting the internal LRCK of processing unit output according to LRCK synchronization frequency division
Simulation input audio signal is converted to digital output signal o_adcdat by signal i_lrck；
The outlet selector and LRCK synchronization frequency division counting processing unit, adc data processing unit and configuring interface units are equal
It is connected, the output for being exported according to configuring interface units controls signal o_sel, and LRCK synchronization frequency division is selected to count processing unit
The inside LRCK synchronization output signal sync_op of output, the output of adc data processing unit digital output signal o_adcdat it
One is used as its output signal adcdat.
4. realization device according to claim 3, which is characterized in that the input terminal of the adc data processing unit also connects
Receive the digital serial audio output signal tdmin and the same level chip analog input signal AIN of the output of prime chip, and the output
Selector output end is connected with rear stage chip.
5. realization device according to claim 3, which is characterized in that the input terminal of the adc data processing unit also connects
Receive the same level chip analog input signal AIN, and the outlet selector output end while the input terminal with its own synchronous switch
And rear stage chip is connected.
6. realization device according to claim 1, which is characterized in that the audio A/D conversion chip further includes shaped like chips
State machine and clock-reset unit, wherein
The chip status machine is connected with configuring interface units, for control chip at least gradually in reset original state,
LRCK synchronization process working condition and normal operating conditions；
The clock-reset unit is used for after chip electrifying startup, so that chip is in the reset original state, in outside
After master cpu completes all configurations operation of chip, chip reset is released, so that chip is introduced into the work of LRCK synchronization process
State, after chip completes LRCK synchronization process, chip is switched to normal work by configuring interface by external piloting control CPU
State.
7. a kind of realization side of the realization device synchronous based on audio A/D conversion chip array frame clock as claimed in claim 3
Method, which is characterized in that the described method includes:
S1, configuring interface units export LRCK synchronous control signal；
S2, synchronous switch according to the LRCK synchronous control signal sync_sel control the synchronous switch output signal whether
The inside LRCK synchronous input signal sync_ip of processing unit is counted as LRCK synchronization frequency division；
S3, LRCK synchronization frequency division count the external LRCK signal frequency split that processing unit inputs audio A/D conversion chip, and will
Signal after frequency dividing is used as chip interior LRCK signal i_lrck, and the synchronous input for the synchronous switch based on the received
Signal sync_ip exports the inside LRCK synchronization output signal sync_op used for rear stage chip synchronization；
S4, the inside LRCK of rear stage audio A/D conversion chip previous stage audio A/D conversion chip based on the received synchronize defeated
Signal sync_op out is inputted as its chip interior LRCK synchronous input signal sync_ip according to the internal LRCK is synchronous
Signal sync_ip and the counting target value of itself, the phase of the chip interior LRCK signal i_lrck after adjusting its frequency dividing, make to adjust
The chip interior LRCK signal i_ of other chips in the phase and array of the chip interior LRCK signal i_lrck after whole
Lrck phase is identical.
8. implementation method according to claim 7, which is characterized in that the output signal syn_ip of the synchronous switch according to
The level of the synchronous control signal sync_sel carries out corresponding variation.
9. implementation method according to claim 7, which is characterized in that the outlet selector is defeated according to configuring interface units
Output out controls signal o_sel, and LRCK synchronization frequency division is selected to count the inside LRCK synchronization output signal of processing unit output
One of sync_op, digital output signal o_adcdat of adc data processing unit output are used as its output signal adcdat.
10. implementation method according to claim 7, which is characterized in that the LRCK synchronization frequency division counts processing unit and works as
When received synchronous input signal sync_ip is high level pulse, then its next input LRCK clock cycle counter
It is forced to the initial value for counting the period.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111327321A (en) * | 2020-04-16 | 2020-06-23 | 苏州顺芯半导体有限公司 | Device and method for realizing real-time synchronization of audio analog-digital conversion chip array |
| CN112019992A (en) * | 2019-05-29 | 2020-12-01 | 瑞昱半导体股份有限公司 | Audio processing circuit supporting multi-channel input function |
| CN113645540A (en) * | 2020-04-24 | 2021-11-12 | 矽统科技股份有限公司 | Digital audio array circuit |
| US11399250B2 (en) | 2020-04-24 | 2022-07-26 | Silicon Integrated Systems Corp. | Digital audio array circuit |
| US20230232152A1 (en) * | 2022-01-18 | 2023-07-20 | Nuvoton Technology Corporation | Microphone array |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20060045172A (en) * | 2004-11-09 | 2006-05-17 | 주식회사 대우일렉트로닉스 | A orthogonal fequency division multiplexing system multiple using dvb-t and dab |
| CN101448315A (en) * | 2008-12-31 | 2009-06-03 | 华为技术有限公司 | Frame clock synchronization method and frame clock synchronization apparatus |
| CN201623760U (en) * | 2009-12-25 | 2010-11-03 | 大连科迪视频技术有限公司 | 3G-SDI high-definition digital video frame synchronizer |
| US20130121505A1 (en) * | 2011-10-09 | 2013-05-16 | VisiSonics Corporation | Microphone array configuration and method for operating the same |
| CN103684375A (en) * | 2013-11-26 | 2014-03-26 | 深圳市芯海科技有限公司 | Clock frequency division switching circuit and clock chip |
| CN104541473A (en) * | 2012-06-01 | 2015-04-22 | 黑莓有限公司 | Universal synchronization engine based on probabilistic methods for guarantee of lock in multiformat audio systems |
| CN106412763A (en) * | 2016-10-11 | 2017-02-15 | 国光电器股份有限公司 | Audio processing method and apparatus |
| CN206790499U (en) * | 2017-04-07 | 2017-12-22 | 深圳市台电实业有限公司 | A kind of audio synchronization system for session discussing system Redundancy Design |
-
2018
- 2018-06-13 CN CN201810606617.6A patent/CN109039335B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20060045172A (en) * | 2004-11-09 | 2006-05-17 | 주식회사 대우일렉트로닉스 | A orthogonal fequency division multiplexing system multiple using dvb-t and dab |
| CN101448315A (en) * | 2008-12-31 | 2009-06-03 | 华为技术有限公司 | Frame clock synchronization method and frame clock synchronization apparatus |
| CN201623760U (en) * | 2009-12-25 | 2010-11-03 | 大连科迪视频技术有限公司 | 3G-SDI high-definition digital video frame synchronizer |
| US20130121505A1 (en) * | 2011-10-09 | 2013-05-16 | VisiSonics Corporation | Microphone array configuration and method for operating the same |
| CN104541473A (en) * | 2012-06-01 | 2015-04-22 | 黑莓有限公司 | Universal synchronization engine based on probabilistic methods for guarantee of lock in multiformat audio systems |
| CN103684375A (en) * | 2013-11-26 | 2014-03-26 | 深圳市芯海科技有限公司 | Clock frequency division switching circuit and clock chip |
| CN106412763A (en) * | 2016-10-11 | 2017-02-15 | 国光电器股份有限公司 | Audio processing method and apparatus |
| CN206790499U (en) * | 2017-04-07 | 2017-12-22 | 深圳市台电实业有限公司 | A kind of audio synchronization system for session discussing system Redundancy Design |
Non-Patent Citations (2)
| Title |
|---|
| MANUEL J等: "A Fully-Digital BIST Wrapper Based on Ternary Test Stimuli for the Dynamic Test of a 40 nm CMOS 18-bit Stereo Audio ΣΔ ADC", 《IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I》 * |
| 常永亮: "基于IP的多路音频实时传输技术研究", 《中国优秀硕士学位论文全文数据库 信息科技辑》 * |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112019992A (en) * | 2019-05-29 | 2020-12-01 | 瑞昱半导体股份有限公司 | Audio processing circuit supporting multi-channel input function |
| CN112019992B (en) * | 2019-05-29 | 2021-07-09 | 瑞昱半导体股份有限公司 | Audio processing circuit supporting multi-channel input function |
| CN111327321A (en) * | 2020-04-16 | 2020-06-23 | 苏州顺芯半导体有限公司 | Device and method for realizing real-time synchronization of audio analog-digital conversion chip array |
| CN111327321B (en) * | 2020-04-16 | 2023-04-25 | 苏州顺芯半导体有限公司 | Device and method for realizing real-time synchronization of audio analog-digital conversion chip array |
| CN113645540A (en) * | 2020-04-24 | 2021-11-12 | 矽统科技股份有限公司 | Digital audio array circuit |
| US11399250B2 (en) | 2020-04-24 | 2022-07-26 | Silicon Integrated Systems Corp. | Digital audio array circuit |
| CN113645540B (en) * | 2020-04-24 | 2022-11-08 | 矽统科技股份有限公司 | Digital audio array circuit |
| US20230232152A1 (en) * | 2022-01-18 | 2023-07-20 | Nuvoton Technology Corporation | Microphone array |
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