CN112306932B - Method and chip for multiplexing interface protocol - Google Patents
Method and chip for multiplexing interface protocol Download PDFInfo
- Publication number
- CN112306932B CN112306932B CN202011351299.7A CN202011351299A CN112306932B CN 112306932 B CN112306932 B CN 112306932B CN 202011351299 A CN202011351299 A CN 202011351299A CN 112306932 B CN112306932 B CN 112306932B
- Authority
- CN
- China
- Prior art keywords
- protocol
- signal
- clock
- input data
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 26
- 238000006243 chemical reaction Methods 0.000 claims abstract description 16
- 238000012545 processing Methods 0.000 claims abstract description 12
- 238000005070 sampling Methods 0.000 claims description 16
- 230000001360 synchronised effect Effects 0.000 claims description 7
- 230000003139 buffering effect Effects 0.000 claims description 3
- 238000013461 design Methods 0.000 abstract description 20
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 238000004891 communication Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 230000005236 sound signal Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Communication Control (AREA)
Abstract
The invention discloses a method and a chip for multiplexing an interface protocol, wherein the method generates clock signals and flag signals corresponding to two protocols respectively through a master clock, a counter, an I2S protocol logic circuit and a TDM protocol logic circuit and transmits the clock signals and the flag signals to a data selector; and then the chip outputs a clock signal and a flag signal of the corresponding protocol through the configuration parameters input to the data selector, and transmits the clock signal and the flag signal to the serial-parallel converter to perform serial-parallel conversion processing on the input data so as to obtain an output result meeting the corresponding protocol. The invention only uses one audio interface, one master clock and one counter to realize the compatibility of the chip to the I2S protocol and the TDM protocol, reduces the consumption of hardware resources and the complexity of circuit design, and can meet the requirements of audio application.
Description
Technical Field
The invention relates to the technical field of audio signal interfaces, in particular to a method and a chip for multiplexing an interface protocol.
Background
The I2S (Inter-IC Sound) protocol is a bus standard established by philips corporation for transmitting audio data between digital audio devices, and is mainly used for transmitting audio data between ICs, such as audio codec and DSP or digital filter. However, the I2S protocol can only transmit 2 channels of data, and another protocol TDM (Time-division multiplexing) can transmit up to 16 channels of data in a Time division multiplexing manner, for example, a multi-microphone matrix of the most popular smart speaker at present generally uses the TDM protocol to transmit data, and can simultaneously transmit 7 channels of microphone inputs and more than 3 channels of audio feedback signals. At present, the two audio protocols are indispensable interfaces in all devices supporting audio, but not all devices simultaneously support the two protocols, and the devices simultaneously supporting the two protocols also have the problems of complex circuit design, confusion in use of a plurality of audio interfaces and the like on the chip design.
Disclosure of Invention
In order to solve the above problems, the present invention provides a method and a chip for multiplexing an interface protocol, which use a minimum of hardware resources to be compatible with an I2S interface and a TDM interface protocol, thereby greatly reducing the complexity of circuit design. The specific technical scheme of the invention is as follows:
a method of interface protocol multiplexing, the method comprising the steps of: s1, a chip acquires an enabling signal to generate a master clock, and a counter starts counting; s2, the chip transmits signals generated by the master clock and the counter to the I2S protocol logic circuit and the TDM protocol logic circuit respectively to generate clock signals and sign signals corresponding to the two protocols respectively, and then the clock signals and the sign signals are transmitted to the data selector; s3, the chip outputs a clock signal and a flag signal of a corresponding protocol through configuration parameters input to the data selector, and then the clock signal and the flag signal are transmitted to the serial-parallel converter; s4, the chip transmits the input data received by the audio interface to the serial-parallel converter, and simultaneously, serial-parallel conversion processing is carried out on the input data by utilizing the clock signal and the flag signal output by the data selector in the step S3, so that an output result meeting the corresponding protocol is obtained. The method of the invention can generate the clock signal and the sign signal which meet the I2S protocol and the TDM protocol by only using one main clock and one counter, thereby designing a chip compatible with two protocols through one audio interface, avoiding confusion on the use of a plurality of audio interfaces, and saving more pins for other modules.
Further, in the step S1, the chip generates a fixed master clock with a frequency 256 times the sampling rate of the input data. A fixed main clock mclk=256×fs is designed, and is used as a working clock of audio interface circuit design and also as a bit clock of a TDM protocol, and other signals of two interface protocols are obtained based on the main clock and a counter, so that synchronous circuit design can be ensured, design complexity and asynchronous problems caused by asynchronous circuit design can be avoided, and circuit design complexity is simplified.
Further, in the step S2, the clock signal generated by the I2S protocol logic circuit includes a bit clock signal and a left-right channel selection signal; the clock signals generated by the TDM protocol logic circuit comprise bit clock signals and frame clock signals; the clock signal is used to dock input data. Different clock signals are generated according to the type of the input data so as to correctly dock the input data, otherwise, errors can occur.
Further, the bit clock signal of the I2S protocol is obtained by taking a value from a counter by the chip every 4 cycles of the master clock, and the frequency of the bit clock signal is 64 times of the sampling rate of the input data, and is used for each bit signal of the corresponding input data; the left and right channel selection signals of the I2S protocol are obtained by taking a value from a counter by a chip every 256 periods of a main clock, and the frequency of the left and right channel selection signals is the same as the sampling rate of the input data and is used for corresponding to the left and right channel signals of the input data.
Further, the bit clock signal of the TDM protocol is obtained by inverting the master clock, and the frequency of the bit clock signal is the same as that of the master clock, and is used for corresponding to each bit signal of the input data; the frame clock signal of the TDM protocol is obtained by taking a value from a counter by a chip every 256 periods of the master clock, and the frequency of the frame clock signal is the same as the sampling rate of the input data, and is used for corresponding to each frame signal of the input data.
Further, in the step S2, the flag signal includes a capture flag signal, a shift left flag signal, and a synchronization flag signal; the capture flag signal is used to synchronize the bit clock signal and the master clock to capture input data, the left shift flag signal is used to synchronize the left and right channel select signal and the master clock or to synchronize the frame clock signal and the master clock to achieve a left shift of the captured data, and the synchronization flag signal is used to capture the left shifted data.
Further, the capture flag signal of the I2S protocol is obtained by taking a value on the counter every 4 cycles of the master clock, the frequency of the capture flag signal is 64 times of the sampling rate of the input data, the left shift flag signal and the synchronization flag signal of the I2S protocol are obtained by taking a value on the counter every 128 cycles of the master clock, and the frequency of the capture flag signal is 2 times of the sampling rate of the input data; the capture flag signal of the TDM protocol is a high level signal, and the left shift flag signal and the synchronization flag signal of the TDM protocol are obtained by taking a value on a counter every 32 cycles of the master clock, and the frequency of the signal is 8 times the sampling rate of the input data. The serial-parallel conversion of the input data can be accurately completed according to the flag signal generated in the set clock period, so that the output result meeting the I2S protocol or the TDM protocol is obtained.
Further, in step S3, the chip compares the input configuration parameters with preset parameters stored in advance, so that the data selector outputs the clock signal and the flag signal of the corresponding protocol.
Further, in the step S4, the serial-parallel conversion processing of the input data includes the following steps: s41, when the enabling signal and the capturing flag signal are at high level, the chip captures input data; s42, the chip sends the captured input data to a register and shifts left, and when a left shift flag signal is at a high level, the chip stops shifting left of the input data; s43, when the synchronous sign signal is at a high level, the chip captures the data after the left shift as an output result meeting the corresponding protocol.
A chip comprising an audio interface, a master clock, a counter, an I2S protocol logic, a TDM protocol logic, a data selector, a serial-to-parallel converter, and a FIFO buffer; the audio interface is compatible with an I2S protocol and a TDM protocol, the combination of the master clock, the counter, the I2S protocol logic circuit and the TDM protocol logic circuit is used for acquiring clock signals and flag signals meeting the I2S protocol or the TDM protocol, the data selector selects and outputs the clock signals and the flag signals of the corresponding protocol according to the configuration parameters, the serial-parallel converter is used for carrying out serial-parallel conversion processing on input data, and the FIFO buffer is used for buffering the data after serial-parallel conversion. The chip of the invention can generate clock signals and flag signals meeting I2S protocol and TDM protocol by only using one master clock and one counter, thereby realizing the design that two protocols can be compatible by only one audio interface, avoiding confusion on the use of a plurality of audio interfaces, and saving more pins for other modules.
The invention has the beneficial effects that: the invention only uses one audio interface, one master clock and one counter to realize the compatibility of the chip to the I2S protocol and the TDM protocol, reduces the consumption of hardware resources and the complexity of circuit design, and can meet the requirements of audio application.
Drawings
Fig. 1 is a flowchart of a method for implementing multiplexing of an I2S interface and a TDM interface protocol according to an embodiment of the present invention.
Fig. 2 is a diagram of a chip architecture for implementing multiplexing of I2S interfaces and TDM interface protocols according to an embodiment of the present invention.
Description of the embodiments
The following describes the technical solution in the embodiment of the present invention in detail with reference to the drawings in the embodiment of the present invention. It should be understood that the following detailed description is merely illustrative of the invention, and is not intended to limit the invention.
As shown in fig. 1, a method for multiplexing an interface protocol, the method includes the following steps: s1, a chip acquires an enable signal en, generates a main clock mclk, and starts counting by a counter divcnt; s2, the chip transmits signals generated by the master clock mclk and the counter divcnt to the I2S protocol logic circuit and the TDM protocol logic circuit respectively to generate clock signals and sign signals corresponding to the two protocols respectively, and then the clock signals and the sign signals are transmitted to the data selector MUX; s3, the chip outputs a clock signal and a flag signal of a corresponding protocol through configuration parameters input to a data selector MUX, and then the clock signal and the flag signal are transmitted to a serial-parallel converter; s4, the chip transmits the input data received by the audio interface to the serial-parallel converter, and simultaneously, serial-parallel conversion processing is carried out on the input data by utilizing the clock signal and the flag signal output by the data selector MUX in the step S3, so that an output result meeting the corresponding protocol is obtained. According to the method, only one main clock mclk and one counter divcnt are used for generating clock signals and flag signals meeting I2S protocol and TDM protocol, so that a chip compatible with two protocols through one audio interface is designed, confusion in use of a plurality of audio interfaces is avoided, and more pins can be saved for other modules to use.
As one example, in the step S1, the chip generates a fixed master clock mclk with a frequency 256 times the sampling rate of the input data. A fixed main clock mclk=256×fs (sampling rate of audio data) is designed, the clock is used as a working clock of audio interface circuit design and also used as a bit clock tdm_scko of a TDM protocol, and other signals of two interface protocols are obtained based on the main clock mclk and a counter divcnt, so that synchronous circuit design can be ensured, design complexity and asynchronous problems caused by asynchronous circuit design are avoided, and circuit design complexity is simplified. In the step S2, the clock signals generated by the I2S protocol logic circuit include a bit clock signal i2s_scko and a left and right channel selection signal i2s_ wso. The bit clock signal i2s_scko of the I2S protocol is obtained by taking a value from a counter divcnt every 4 periods of the master clock mclk, I2 s_scko=divcnt [1] =64×fs, and is used for each bit signal of the corresponding input data; the left and right channel selection signal i2s_ wso of the I2S protocol is obtained by taking the value of the counter divcnt every 256 cycles of the master clock, i2s_ wso =divcnt [7] =fs, for the left and right channel signals corresponding to the input data. The clock signals generated by the TDM protocol logic circuit include a bit clock signal tdm_scko and a frame clock signal tdm_ wso. The bit clock signal tdm_scko of the TDM protocol is obtained by inverting the main clock mclk, and tdm_scko=256×fs, for each bit signal corresponding to the input data; the frame clock signal tdm_ wso of the TDM protocol is obtained from the chip on the counter divcnt every 256 cycles of the master clock mclk, tdm_ wso =fs for each frame signal of the corresponding input data. Different clock signals need to be generated according to the type of the input data to correctly dock the input data, otherwise, errors can occur.
As one embodiment, in the step S2, the flag signal includes a capture flag signal vbit, a shift left flag signal fbit, and a synchronization flag signal lbit. The marking signal is obtained by taking the value of the counter, and different protocols need to take different marking signals. If the protocol is I2S, the chip takes a flag bit on the counter divcnt every time the master clock mclk passes through 4 periods and when divcnt [1:0] =1, so as to form a capture flag signal i2s_vbit of the I2S protocol; every time the main clock passes through 128 periods and when divcnt [6:2] =1, the chip takes a flag bit on the counter, so as to form a left shift flag signal i2s_fbit of the I2S protocol; every time the master clock passes through 128 cycles and when divcnt [6:2] =25, the chip takes one flag bit on the counter, thereby forming a synchronization flag signal i2s_lbit of the I2S protocol. In the case of the TDM protocol, assuming that the TDM protocol employs 4 channels to transmit data, each time the master clock passes through 32 cycles and when divcnt= 8'd1 or divcnt= 8'd33 or divcnt= 8'd65 or divcnt= 8'd97, the chip takes a flag bit on the counter, thereby forming a left shift flag signal tdm_fbit of the TDM protocol; every time the master clock passes 32 cycles and when divcnt= 8'd25 or divcnt= 8'd57 or divcnt= 8'd89 or divcnt= 8'd121, the chip takes a flag bit on the counter, thus forming the synchronization flag signal tdm_lbit of the TDM protocol. Assuming that the TDM protocol employs 6 channels for transmitting data, each time the master clock passes through 32 cycles and when divcnt= 8'd1 or divcnt= 8'd33 or divcnt= 8'd65 or divcnt= 8'd97 or divnt= 8'd129 or divcnt= 8'd161, the chip takes a flag bit on the counter to form a left shift flag signal tdm_fbit of the TDM protocol; the chip takes one flag bit on the counter to form the synchronization flag signal tdm_lbit of the TDM protocol every 32 cycles when the master clock passes and when divcnt= 8'd25 or divcnt= 8'd57 or divcnt= 8'd89 or divcnt= 8'd121 or divnt= 8'd 185. The TDM protocol also supports other different channel numbers to transmit data, and the method for acquiring the flag signal satisfying other channels is not described again. Since the frequency of the bit clock signal tdm_scko of the TDM protocol is the same as that of the main clock mclk, the main clock mclk is directly obtained by inverting and has a phase difference of half a period, and the TDM protocol needs to be just satisfied, and thus synchronous processing is not needed, the capture flag signal tdm_vbit of the TDM protocol is always kept at a high level, that is, a high level signal, which is the same for TDM protocols of different channels. The invention generates the sign signal strictly according to the set clock period and the set time of the counter, thus the serial-parallel conversion of the input data can be accurately completed, and the output result meeting the I2S protocol or the TDM protocol is obtained.
In one embodiment, in step S3, the chip compares the input configuration parameters with preset parameters stored in advance to enable the data selector to output the clock signal and the flag signal of the corresponding protocol. Wherein the preset parameter is set such that one selection bit mux_sel_0 of the data selector MUX is defined as an I2S protocol interface and one selection bit mux_sel_1 is defined as a TDM protocol interface. Assuming that the user-configured parameter information is 0, the chip interior will walk the design route that satisfies the I2S protocol.
As one embodiment, in the step S4, the serial-parallel conversion processing of the input data includes the following steps: s41, when the enable signal en and the capture flag signal vbit are at high level, the chip captures input data; s42, the chip sends the captured input data to the trigger DFF and shifts left when each rising edge of the master clock mclk arrives, and when the left shift flag signal fbit is high level, the chip stops shifting left of the input data; s43, when the synchronous flag signal lbit is at a high level, the chip captures the data after left shift as an output result meeting the corresponding protocol. The output result obtained by serial-parallel conversion is the data meeting the I2S protocol or the TDM protocol, and the chip can transmit the output result to the FIFO buffer memory to wait for the subsequent processing. In the I2S protocol, left channel data is transmitted when the left and right channel selection signals i2s_ wso =0, and right channel data is transmitted when i2s_ wso =1. Assuming that left channel data is currently transmitted, i2s_ wso =0 at this time, an error is made if the left channel data continues for the period i2s_ wso =1. Then a "stop signal" needs to be set, i.e. when the shift left flag signal fbit=1, indicating that reception of the right channel signal is started at this time, the shift left operation of the captured data needs to be forcibly stopped to avoid errors. Assuming that right channel data is currently transmitted, i2s_ wso =1 also requires forced stopping of the left shift operation of the captured data to avoid errors. By repeating the above steps, data of two channels of parallel I2S protocol can be obtained.
As shown in fig. 2, a chip includes an audio interface, a master clock, a counter, an I2S protocol logic circuit, a TDM protocol logic circuit, a data selector, a serial-to-parallel converter, and a FIFO buffer; the audio interface is compatible with an I2S protocol and a TDM protocol, the combination of the master clock, the counter, the I2S protocol logic circuit and the TDM protocol logic circuit is used for acquiring clock signals and flag signals meeting the I2S protocol or the TDM protocol, the data selector selects and outputs the clock signals and the flag signals of the corresponding protocol according to the configuration parameters, the serial-parallel converter is used for carrying out serial-parallel conversion processing on input data, and the FIFO buffer is used for buffering the data after serial-parallel conversion. The chip is used for realizing the multiplexing method of the I2S interface and the TDM interface protocol, and the independent design method is generally adopted in the prior art to be compatible with the two protocols, but the chip can generate clock signals and sign signals meeting the I2S protocol and the TDM protocol by only using one main clock and one counter, thereby realizing the design that the two protocols can be compatible by only one audio interface, avoiding the confusion of the use of a plurality of audio interfaces, saving more pins for other modules, reducing the consumption of hardware resources and the complexity of circuit design, and meeting the requirements of audio application.
In the embodiments provided in the present invention, it should be understood that the disclosed system, apparatus and method may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form. The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.
Claims (8)
1. A method of interface protocol multiplexing, the method comprising the steps of:
s1, a chip acquires an enabling signal to generate a master clock, and a counter starts counting;
s2, the chip transmits signals generated by the master clock and the counter to the I2S protocol logic circuit and the TDM protocol logic circuit respectively to generate clock signals and sign signals corresponding to the two protocols respectively, and then the clock signals and the sign signals are transmitted to the data selector;
s3, the chip outputs a clock signal and a flag signal of a corresponding protocol through configuration parameters input to the data selector, and then the clock signal and the flag signal are transmitted to the serial-parallel converter;
s4, the chip transmits the input data received by the audio interface to the serial-parallel converter, and simultaneously performs serial-parallel conversion processing on the input data by using the clock signal and the flag signal output by the data selector in the step S3 to obtain an output result meeting a corresponding protocol;
wherein the flag signal includes a capture flag signal, a shift left flag signal, and a synchronization flag signal; the capture flag signal is used for synchronizing a bit clock signal and a master clock to capture input data, the left shift flag signal is used for synchronizing a left and right channel selection signal and the master clock or synchronizing a frame clock signal and the master clock to realize left shift of the captured data, and the synchronization flag signal is used for capturing the left shifted data;
the capture flag signal of the I2S protocol is obtained by taking a value on a counter every 4 periods of the main clock, the frequency of the capture flag signal is 64 times of the sampling rate of the input data, the left shift flag signal and the synchronous flag signal of the I2S protocol are obtained by taking a value on the counter every 128 periods of the main clock, and the frequency of the capture flag signal is 2 times of the sampling rate of the input data; the capture flag signal of the TDM protocol is a high level signal, and the left shift flag signal and the synchronization flag signal of the TDM protocol are obtained by taking a value on a counter every 32 cycles of the master clock, and the frequency of the signal is 8 times the sampling rate of the input data.
2. The method according to claim 1, wherein in the step S1, the chip generates a fixed master clock with a frequency 256 times the sampling rate of the input data.
3. The method according to claim 1, wherein in the step S2, the clock signal generated by the I2S protocol logic circuit includes a bit clock signal and a left-right channel selection signal; the clock signals generated by the TDM protocol logic circuit comprise bit clock signals and frame clock signals; the clock signal is used to dock input data.
4. A method according to claim 3, wherein the bit clock signal of the I2S protocol is obtained by taking a value from a counter every 4 cycles of the master clock, the frequency of the value being 64 times the sampling rate of the input data, for each bit signal of the corresponding input data; the left and right channel selection signals of the I2S protocol are obtained by taking a value from a counter by a chip every 256 periods of a main clock, and the frequency of the left and right channel selection signals is the same as the sampling rate of the input data and is used for corresponding to the left and right channel signals of the input data.
5. A method according to claim 3, wherein the bit clock signal of the TDM protocol is obtained by inverting a master clock, and has the same frequency as the master clock, and is used for each bit signal of the corresponding input data; the frame clock signal of the TDM protocol is obtained by taking a value from a counter by a chip every 256 periods of the master clock, and the frequency of the frame clock signal is the same as the sampling rate of the input data, and is used for corresponding to each frame signal of the input data.
6. The method according to claim 1, wherein in the step S3, the chip makes the data selector output the clock signal and the flag signal of the corresponding protocol by comparing the inputted configuration parameters with the preset parameters stored in advance.
7. The method of multiplexing an interface protocol according to claim 1, wherein in the step S4, the serial-parallel conversion processing of the input data includes the steps of:
s41, when the enabling signal and the capturing flag signal are at high level, the chip captures input data;
s42, the chip sends the captured input data to a register and shifts left, and when a left shift flag signal is at a high level, the chip stops shifting left of the input data;
s43, when the synchronous sign signal is at a high level, the chip captures the data after the left shift as an output result meeting the corresponding protocol.
8. A chip for multiplexing an I2S interface and a TDM interface protocol by using the method of any of claims 1 to 7, where the chip includes an audio interface, a master clock, a counter, an I2S protocol logic, a TDM protocol logic, a data selector, a serial-to-parallel converter, and a FIFO buffer; the audio interface is compatible with an I2S protocol and a TDM protocol, the combination of the master clock, the counter, the I2S protocol logic circuit and the TDM protocol logic circuit is used for acquiring clock signals and flag signals meeting the I2S protocol or the TDM protocol, the data selector selects and outputs the clock signals and the flag signals of the corresponding protocol according to the configuration parameters, the serial-parallel converter is used for carrying out serial-parallel conversion processing on input data, and the FIFO buffer is used for buffering the data after serial-parallel conversion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011351299.7A CN112306932B (en) | 2020-11-27 | 2020-11-27 | Method and chip for multiplexing interface protocol |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011351299.7A CN112306932B (en) | 2020-11-27 | 2020-11-27 | Method and chip for multiplexing interface protocol |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112306932A CN112306932A (en) | 2021-02-02 |
| CN112306932B true CN112306932B (en) | 2023-12-01 |
Family
ID=74487738
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011351299.7A Active CN112306932B (en) | 2020-11-27 | 2020-11-27 | Method and chip for multiplexing interface protocol |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112306932B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114253896B (en) * | 2021-12-07 | 2024-06-14 | 苏州上声电子股份有限公司 | For I2Clock generation method and system for S audio bus |
| CN115174305B (en) * | 2022-06-28 | 2023-11-03 | 珠海一微半导体股份有限公司 | IIS interface-based data conversion control system and chip |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102545896A (en) * | 2010-12-17 | 2012-07-04 | 美信集成产品公司 | Adaptive frequency synthesis for a serial data interface |
| CN102929824A (en) * | 2012-10-15 | 2013-02-13 | 天地融科技股份有限公司 | System for multiplexing USB (Universal Serial Bus) interface transmission data |
| CN102946247A (en) * | 2012-11-08 | 2013-02-27 | 东南大学 | Frequency dividing circuit of I2S (inter-IC sound) interface clock circuit |
| CN105607570A (en) * | 2015-12-25 | 2016-05-25 | 清华大学 | Multi-channel signal acquisition system compatible with multiple protocols |
| CN106911987A (en) * | 2017-02-21 | 2017-06-30 | 珠海全志科技股份有限公司 | Main control end, equipment end, the method and system of transmission multichannel audb data |
| CN207198837U (en) * | 2017-09-29 | 2018-04-06 | 深圳市客所思电子科技有限公司 | USB sound cards |
| CN110134625A (en) * | 2019-05-28 | 2019-08-16 | 深圳星联天通科技有限公司 | Voice data serial ports transmission method and device, system, electronic equipment and storage medium |
| CN111586531A (en) * | 2019-02-15 | 2020-08-25 | 矽统科技股份有限公司 | Audio interface detection device and method |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060020718A1 (en) * | 2004-06-28 | 2006-01-26 | Duresky Nicholas E | Resource sharing apparatus, systems, and methods |
| US8433027B2 (en) * | 2009-10-08 | 2013-04-30 | Dialog Semiconductor Gmbh | Digital controller for automatic rate detection and tracking of audio interface clocks |
| US20140115229A1 (en) * | 2012-10-19 | 2014-04-24 | Lsi Corporation | Method and system to reduce system boot loader download time for spi based flash memories |
| US9524759B2 (en) * | 2014-12-16 | 2016-12-20 | Micron Technology, Inc. | Apparatuses and methods for capturing data using a divided clock |
-
2020
- 2020-11-27 CN CN202011351299.7A patent/CN112306932B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102545896A (en) * | 2010-12-17 | 2012-07-04 | 美信集成产品公司 | Adaptive frequency synthesis for a serial data interface |
| CN102929824A (en) * | 2012-10-15 | 2013-02-13 | 天地融科技股份有限公司 | System for multiplexing USB (Universal Serial Bus) interface transmission data |
| CN102946247A (en) * | 2012-11-08 | 2013-02-27 | 东南大学 | Frequency dividing circuit of I2S (inter-IC sound) interface clock circuit |
| CN105607570A (en) * | 2015-12-25 | 2016-05-25 | 清华大学 | Multi-channel signal acquisition system compatible with multiple protocols |
| CN106911987A (en) * | 2017-02-21 | 2017-06-30 | 珠海全志科技股份有限公司 | Main control end, equipment end, the method and system of transmission multichannel audb data |
| CN207198837U (en) * | 2017-09-29 | 2018-04-06 | 深圳市客所思电子科技有限公司 | USB sound cards |
| CN111586531A (en) * | 2019-02-15 | 2020-08-25 | 矽统科技股份有限公司 | Audio interface detection device and method |
| CN110134625A (en) * | 2019-05-28 | 2019-08-16 | 深圳星联天通科技有限公司 | Voice data serial ports transmission method and device, system, electronic equipment and storage medium |
Non-Patent Citations (2)
| Title |
|---|
| 刘辉.《电子技术基础》.北京理工大学出版社,2009,(第ISBN978-7-5640-2841-1版),128. * |
| 胡安•何塞•罗德里格斯•安蒂纳.《FPGA基础、高级功能与工业电子应用》.机械工业出版社,2020,(第ISBN978-7-111-66420-8版),30. * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112306932A (en) | 2021-02-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN112306932B (en) | Method and chip for multiplexing interface protocol | |
| US8913196B2 (en) | Video processing device and video processing method including deserializer | |
| CN107087132B (en) | Receiver and signal transmission method | |
| US10152445B2 (en) | Signal count reduction between semiconductor dies assembled in wafer-level package | |
| CN104050135B (en) | Synchronize the data transfer from core to physical interface | |
| JP4758311B2 (en) | Asynchronous data holding circuit | |
| CN113190291A (en) | Configurable protocol conversion system and method based on network-on-chip data acquisition | |
| JP2001211228A (en) | Telephone terminal | |
| CN112597097A (en) | ADC data acquisition card of PXIE interface, application method and medium thereof | |
| US20190005974A1 (en) | Alignment of bi-directional multi-stream multi-rate i2s audio transmitted between integrated circuits | |
| US8170070B2 (en) | Method and circuit for interleaving, serializing and deserializing camera and keypad data | |
| CN107290736B (en) | Signal processing device and ultrasonic signal processing system | |
| CN101502036A (en) | Semiconductor integrated circuit and transmitter apparatus having the same | |
| CN110221996B (en) | Controller configuration method and device in main control chip | |
| JP2009265024A (en) | Semiconductor device | |
| CN210469595U (en) | Audio and video synchronization device for video embedded digital audio | |
| WO2024146029A1 (en) | Serial communication apparatus, serial communication system and serial communication method | |
| CN110601784B (en) | TDM interface extension method, device, equipment and readable storage medium | |
| CN111338599A (en) | Audio acquisition system and design method thereof | |
| CN115766332B (en) | Serial communication device, serial communication system, and serial communication method | |
| CN110519667B (en) | Method for realizing optical signal line crossing | |
| CN219420840U (en) | Video processing module | |
| JP2001230837A (en) | Telephone terminal | |
| JP2003152898A (en) | Phone terminal equipment | |
| EP2816791A1 (en) | Multi-path speech signal multiplexing circuit, equipment and method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information | ||
| CB02 | Change of applicant information |
Address after: 519000 2706, No. 3000, Huandao East Road, Hengqin new area, Zhuhai, Guangdong Applicant after: Zhuhai Yiwei Semiconductor Co.,Ltd. Address before: Room 105-514, No.6 Baohua Road, Hengqin New District, Zhuhai City, Guangdong Province Applicant before: AMICRO SEMICONDUCTOR Co.,Ltd. |
|
| GR01 | Patent grant | ||
| GR01 | Patent grant |