CN111338599A

CN111338599A - Audio acquisition system and design method thereof

Info

Publication number: CN111338599A
Application number: CN202010239616.XA
Authority: CN
Inventors: 刘天明; 刘永新; 汤顺; 马乾力
Original assignee: Shenzhen Micro & Nano Integrated Circuits And Systems Research Institute
Current assignee: Shenzhen Micro & Nano Integrated Circuits And Systems Research Institute
Priority date: 2020-03-30
Filing date: 2020-03-30
Publication date: 2020-06-26

Abstract

The invention provides an audio acquisition system, which comprises an SOC chip and an ADC series queue, wherein the ADC series queue comprises N ADC chips which are sequentially connected in series; each ADC chip comprises L ADC channels, a first audio interface and a second audio interface, wherein the L ADC channels and the second audio interface are respectively connected to the first audio interface, and N and L are natural numbers larger than 1; the second audio interface of each ADC chip is connected with the first audio interface of the next ADC chip, the second audio interface of each ADC chip is used for receiving the audio digital signal of the next ADC chip, and the first audio interface of each ADC chip is used for transmitting the audio digital signal to the second audio interface of the previous ADC chip; and the ADC chip positioned at the head end of the ADC serial queue is used as a main chip of the ADC serial queue, and the main chip transmits the audio digital signals to the SOC chip through a second audio interface or a serial peripheral interface of the main chip. Compared with the related technology, the invention has the advantages of multiple ADC channels, wide application scene and low cost.

Description

Audio acquisition system and design method thereof

[ technical field ] A method for producing a semiconductor device

The invention relates to the field of data acquisition, in particular to an audio acquisition system and a design method thereof.

[ background of the invention ]

With the development of speech recognition technology, audio ADC chips are more and more widely used in this field, and in some higher-end speech recognition application fields, it is necessary to form an array (often called microphone array) from multiple microphones, and perform sound source localization and other applications through matrix operation analysis.

In the related art, an audio acquisition system includes a microphone, an ADC chip, a digital audio interface, and an SOC chip, which are connected in sequence, wherein one ADC chip may include multiple ADC channels (i.e., ADC digital-to-analog converters), and each ADC channel may be in butt joint with one microphone; the plurality of microphones respectively collect external sounds, the plurality of ADC channels respectively perform digital-to-analog conversion processing on the collected sounds to obtain audio data, each ADC channel is respectively connected to the SOC through a digital audio interface, and each ADC channel sends the audio data to the SOC through the digital audio interface for subsequent coding and decoding processing; in order to ensure that as much audio data as possible is collected, the ADC chip needs to set as many ADC channels as possible.

However, in the related art, since the number of ADC channels designed by a single chip is too large, if a single chip is applied, a large number of ADC channels are not needed, which causes waste, and increases the application cost; on the other hand, if a plurality of ADC chips are connected to the SOC chip at the same time, the large-scale application of the ADC chip is also restricted due to the limited number of digital audio interfaces of the SOC chip.

Therefore, there is a need to provide a new audio acquisition system and a design method thereof to solve the above technical problems.

[ summary of the invention ]

The invention aims to provide an audio acquisition system and a design method thereof, which solve the problems that the application cost is high due to the excessive number of ADC channels designed by a single chip, and the large-scale application of the ADC is limited due to the limited number of digital audio interfaces of an SOC chip.

The invention provides an audio acquisition system, comprising:

the system comprises an SOC chip and a plurality of ADC series queues which are mutually connected in a cascade mode and are respectively connected with the SOC chip, wherein the plurality of ADC series queues are respectively used for collecting audio digital signals, and the SOC chip is used for coding and processing the audio digital signals;

each ADC series queue comprises N ADC chips which are sequentially connected in series, each ADC chip comprises L ADC channels, a first audio interface and a second audio interface, the L ADC channels are respectively used for collecting the audio digital signals, the second audio interface is respectively connected to the first audio interface, and N and L are natural numbers which are larger than 1;

the second audio interface of each ADC chip is connected with the first audio interface of the next ADC chip;

the second audio interface of each ADC chip is configured to receive the audio digital signal collected by the next ADC chip, and the first audio interface of each ADC chip is configured to transmit the audio digital signal collected by the ADC chip and the audio digital signal collected by the next ADC chip to the second audio interface of the previous ADC chip;

the ADC chip at the head end of the ADC serial queue is defined as a main chip of the ADC serial queue, the main chip further comprises serial peripheral interfaces, the serial peripheral interfaces are connected with the L ADC channels of the main chip and the second audio interfaces of the ADC channels, the main chip is connected with the SOC chip through the second audio interfaces and the serial peripheral interfaces of the main chip, and each ADC serial queue transmits the audio digital signals to the SOC chip through the second audio interfaces of the main chip or the serial peripheral interfaces of the main chip.

Preferably, each ADC channel includes a microphone and an analog-to-digital converter respectively connected to the microphone and the first audio interface, the microphone is configured to collect an external sound signal and convert the sound signal into an audio analog signal, the analog-to-digital converter is configured to process and convert the audio analog signal into the audio digital signal, and the analog-to-digital converter of the main chip is further connected to the serial peripheral interface.

Preferably, each ADC chip further comprises a synchronization module for receiving a synchronization signal; in the same ADC series queue, a synchronization module of the main chip is connected with the SOC chip and simultaneously connected with the synchronization module of the next ADC chip, and the synchronization module of the main chip is used for receiving the synchronization signal of the SOC chip and transmitting the synchronization signal to the synchronization module of the next ADC chip.

Preferably, each ADC chip further includes a synchronous serial interface, and the synchronous serial interface is configured to configure each ADC chip to operate in different modes according to the synchronous signal.

The invention also provides a design method of the audio acquisition system based on the invention, which comprises the following steps:

determining the number M of the ADC series queues and the number N of the ADC chips of each ADC series queue according to the number of I2S interfaces or SPI interfaces of the SOC chips;

configuring an ADC chip at the head end of the ADC serial queue as the master chip and configuring the ADC chip at the rear stage of the master chip as a slave chip through the synchronous serial interface;

configuring the main chip through the synchronous serial interface to select the second audio interface or the serial peripheral interface to transmit the audio digital signal to the SOC chip;

configuring an AD sampling rate and an AD sampling precision of the ADC serial queue, the number of ADC channels for collecting the audio digital signals, a transmission mode of the second audio interface or the serial peripheral interface of the main chip, and a transmission rate of the audio digital signals;

configuring the working clock frequency of the ADC series queue;

and controlling the ADC chip of the ADC serial queue to collect audio digital signals through the synchronous serial interface.

Preferably, in the step of serially connecting the ADCs to the queue, the transmission rate of the audio digital signal is greater than or equal to the number × AD sampling precision × AD sampling rate of the ADC channels used for acquiring the audio digital signal.

Preferably, in the step of serially connecting the ADCs, the working clock frequency of the serially connecting ADC queue is greater than or equal to 2 × AD sampling rate × AD sampling precision.

Compared with the prior art, the audio acquisition system has the advantages that a single ADC chip is provided with a plurality of ADC channels, the ADC chips are sequentially connected in series to form an ADC series queue, the ADC series queues are mutually connected in series and are respectively connected to the SOC chip, each ADC series queue can be connected with the digital audio interface of the SOC chip through the first audio interface, each ADC series queue can also be connected with the serial peripheral interface of the SOC chip through the serial peripheral interface, namely, the connection mode between the ADC series queue and the SOC chip is increased, in practical application, different numbers of the ADC series queues in cascade and the numbers of the ADC chips in each ADC series queue in series queue can be flexibly combined according to the number of the digital audio interfaces and the serial peripheral interfaces of the SOC chip according to different types of selection of the SOC chip, so that the number of the ADC channels for acquiring sound is effectively ensured, the method is beneficial to making different application schemes according to different application scenes, widens the application field, reduces the waste of redundant channels of a single chip, and reduces the application cost.

[ description of the drawings ]

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without inventive efforts, wherein:

FIG. 1 is a schematic diagram of an audio acquisition system according to the present invention;

FIG. 2 is a schematic diagram of a single ADC series queue and SOC chip connection according to the present invention;

FIG. 3 is a schematic diagram of a single ADC chip according to the present invention;

FIG. 4 is a schematic flow chart of a design method of an audio acquisition system according to the present invention;

FIG. 5 is a schematic diagram illustrating the audio data transmission between the SOC chip and the ADC serial queue through the I2S interface when the 1 × FS mode is adopted in the present invention;

FIG. 6 is a schematic diagram illustrating the audio data transmission between the SOC chip and the ADC serial queue through the I2S interface when the K × FS mode is adopted in the present invention;

fig. 7 is a schematic diagram illustrating the principle that audio data is transmitted between the SOC chip and the ADC serial queue through the SPI interface when the SCPH is 0 and the SCPOL is 0 modes according to the present invention;

fig. 8 is a schematic diagram illustrating the principle that audio data is transmitted between the SOC chip and the ADC serial queue through the SPI interface when the SCPH is 0 and the SCPOL is 1 modes according to the present invention;

fig. 9 is a schematic diagram illustrating the principle that audio data is transmitted between the SOC chip and the ADC serial queue through the SPI interface when the SCPH 1 and SCPOL 0 modes are adopted in the present invention;

fig. 10 is a schematic diagram illustrating the principle of transmitting audio data between the SOC chip and the ADC serial queue through the SPI interface when the SCPH 1 and SCPOL 1 modes are adopted in the present invention.

[ detailed description ] embodiments

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 1-3, an audio acquisition system 100 according to the present invention includes an ADC serial queue 1 and an SOC chip 2.

The ADC series queue 1 comprises a plurality of ADC series queues 1 which are mutually connected in a cascade mode and are respectively connected with the SOC chip 2, and the ADC series queues 1 are used for collecting audio digital signals and transmitting the audio digital signals to the SOC chip 2.

In the present embodiment, each ADC serial queue 1 includes N ADC chips 11(Analog-to-Digital Converter, chinese called Analog-to-Digital Converter) connected in series in sequence; each ADC chip 11 includes L ADC channels 111, a first audio interface 112, a second audio interface 113, a synchronization module 114, and a synchronous serial interface 115, which are respectively used for acquiring the audio digital signals; wherein N and L are both natural numbers larger than 1.

More specifically, in the same ADC chip 11:

the L ADC channels 111 are respectively connected to the first audio interface 112, each ADC channel 111 includes a microphone and an analog-to-digital converter respectively connected to the microphone and the first audio interface 112, the microphone is configured to collect an external sound signal and convert the sound signal into an audio analog signal, and the analog-to-digital converter is configured to process and convert the audio analog signal into the audio digital signal.

The first audio interface 112 and the second audio interface 113 are both I2S interfaces (Inter-IC Sound, referred to as integrated circuit built-in audio) for audio data transmission, the second audio interface 113 is connected to the first audio interface 112, and the second audio interface 113 can transmit audio data to the first audio interface 112.

The synchronization module 114 is a SYNC signal receiving module for receiving SYNC synchronization signals, the synchronization serial interface 115 is an I2C interface (Inter-Integrated Circuit), the synchronization module 114 is connected to the synchronization serial interface 115, during actual operation, the synchronization module 114 receives SYNC synchronization signals and transmits the SYNC synchronization signals to the synchronization serial interface 115, and the synchronization serial interface 115 receives SYNC synchronization signals and configures each ADC chip 11 to operate in different modes according to the SYNC synchronization signals.

And in the same N ADC chips 11 of the ADC serial queue 1:

the ADC chip 11 at the head end of the ADC serial queue 1 is defined as the main chip of the ADC serial queue 1, that is, the main chip is connected to the SOC chip as the first ADC chip of the ADC serial queue 1, and the other N-1 ADC chips 11 in the ADC serial queue 1 are used as the slave chips of the ADC serial queue 1, that is, the slave chips are used as the lower chips of the main chip.

The main chip further includes a Serial peripheral interface 116 connected to the L ADC channels 111 and the second audio interface 113 of the main chip, respectively, where the Serial peripheral interface 116 is an SPI interface (Serial peripheral interface), the main chip is connected to the SOC chip 2 through the second audio interface 113 and the Serial peripheral interface 116 of the main chip, each ADC Serial queue 1 transmits an audio digital signal to the SOC chip 2 through the second audio interface 113 of the main chip or the Serial peripheral interface 115 of the main chip, and the analog-to-digital converter of the main chip is further connected to the Serial peripheral interface 116.

The second audio interface 113 of each ADC chip 11 is connected to the first audio interface 112 of the next ADC chip, the second audio interface of each ADC chip 11 is configured to receive the audio digital signal of the next ADC chip 11, and the first audio interface 112 of each ADC chip is configured to transmit the audio digital signal collected by the ADC chip 11 and the audio digital signal of the next ADC chip 11 to the second audio interface 113 of the previous ADC chip; the synchronization module 114 of the main chip is connected to the SOC chip and simultaneously connected to the synchronization module of the next stage ADC chip, and the synchronization module 114 of the main chip is configured to receive the synchronization signal of the SOC chip and transmit the synchronization signal to the synchronization module 114 of the next stage ADC chip.

The SOC Chip 2(System-on-a-Chip, chinese called System-on-Chip) is configured to encode and process the audio digital signals, and the SOC Chip 2 is connected to the first audio interface 112 of each main Chip through an I2S interface thereon, or connected to the serial peripheral interface 116 of each main Chip through an SPI interface thereon.

As shown in fig. 4, the present invention further provides a design method of an audio acquisition system according to the present invention, which includes the following steps:

step S1, determining the number M of the ADC serial queues and the number N of the ADC chips of each ADC serial queue according to the number of I2S interfaces or SPI interfaces of the SOC chip.

Step S2, configuring, through the synchronous serial interface, the ADC chip located at the head end of the ADC serial queue as the master chip, and configuring, through the synchronous serial interface, the ADC chip located at the rear stage of the master chip as the slave chip. The SOC chip sends SYNC synchronous signals to each slave chip through the master chip so as to ensure that all the slave chips synchronously acquire audio data with the master chip and ensure that the audio data of the slave chips are synchronously transmitted to the master chip.

Step S3, configuring the main chip through the synchronous serial interface to select the second audio interface or the serial peripheral interface to transmit the audio digital signal to the SOC chip;

step S4, configuring an AD sampling rate and an AD sampling precision of the ADC serial queue, the number of ADC channels for acquiring the audio digital signal, a transmission mode of the second audio interface or the serial peripheral interface of the main chip, and a transmission rate of the audio digital signal.

Specifically, an AD sampling rate, an AD sampling precision and the number of ADC channels for acquiring the audio digital signals can be specifically set according to requirements of practical application, for example, the sampling rate of CD audio is 44.1KHz, namely sound information is sampled at 44100 times per second, in principle, the higher the sampling rate is, the better the sound quality is, the higher the AD sampling precision is, including but not limited to 8bit, 16bit and 24bit, and the like, the higher the AD sampling precision is, the higher the resolution of audio data is, the truer the recorded and played sound is (the finer the sound is), the number of ADC channels for acquiring the audio digital signals is determined according to algorithm requirements, for example, when sound source positioning is required, the larger the number of ADC channels for acquiring the audio digital signals is, the more accurate the result of a plurality of ADC channel array algorithms is, when only simple sound acquisition is required, the transmission mode of the second audio interface or the serial interface of the main chip is optional, the number of ADC channels for acquiring the audio digital signals can be determined according to which serial sampling rate and serial number of ADC channels are not less than or equal to the serial sampling rate 3583, and the serial data transmission mode of the ADC channels for acquiring the audio digital signals is further determined according to the serial data queue.

And step S5, configuring the working clock frequency of the ADC series queue, wherein the working clock frequency of the ADC series queue is more than or equal to 2 × AD sampling rate × AD sampling precision.

And step S6, controlling the ADC chip of the ADC serial queue to collect audio digital signals through the synchronous serial interface.

When the ADC series queue performs audio data transmission with the SOC chip through an I2S interface:

the number of ADC channels of a single ADC Chip is L, audio data collected by each ADC channel is recorded as CH # 0-L-1, each ADC serial queue comprises N ADC chips, the ith Chip is recorded as Chip # i, i is larger than or equal to 0 and smaller than or equal to N-1, N is a positive integer larger than 1, and i is a positive integer.

If the number of the selected I2S interfaces of the SOC chip is greater than or equal to N × L, a 1xFS mode may be adopted, as shown in fig. 5:

1xFS is 1 ADC sampling period, and in this period, Chip # i transmits (i +1) × L pieces of ADC channel data, where CH #0 to CH # i × L-1 are audio data collected by the ADC channels of Chip #0 to Chip # i-1, and CH # i × L to CH # (i +1) × L-1 are audio data of the ADC channel of Chip # i itself.

If the number of the selected I2S interfaces of the SOC chip is less than N × L, only the KxFS mode can be adopted, as shown in fig. 6:

KxFS is 1 ADC sampling period, and in the period, Chip # i transmits (i +1) × L pieces of ADC channel data, wherein CH # 0-CH # i × L-1 are input audio data collected by the ADC channels of the chips # 0-Chip # i-1, and CH # i × L-CH # (i +1) × L-1 are audio data of the ADC channels of the Chip # i.

When the ADC serial queue transmits audio data to the SOC chip through the SPI interface, the audio acquisition system may support four combination modes of SCPH and SCPOL of the SPI protocol, the interval of the effective period of each SPI interface of the SOC chip may be selected from 0, 0.5, or 1 SCK, and CH #0 to CH # N L-1 are N x L pieces of channel data of N DC chips to be connected in series, where:

as can be seen from fig. 7, the principle that the audio acquisition system transmits audio data between the SOC chip and the ADC serial queue through the SPI interface in the SCPH-0 and SCPOL-0 modes.

As can be seen from fig. 8, the principle that the audio acquisition system transmits audio data between the SOC chip and the ADC serial queue through the SPI interface in the SCPH-0 and SCPOL-1 modes.

As can be seen from fig. 9, the principle that the audio acquisition system transmits audio data between the SOC chip and the ADC serial queue through the SPI interface in the SCPH 1 and SCPOL 0 modes.

As can be seen from fig. 10, the principle that the audio acquisition system transmits audio data between the SOC chip and the ADC serial queue through the SPI interface in the SCPH 1 mode and the SCPOL 1 mode.

While the foregoing is directed to embodiments of the present invention, it will be understood by those skilled in the art that various changes may be made without departing from the spirit and scope of the invention.

Claims

1. An audio acquisition system, comprising:

the ADC chip at the head end of the ADC serial queue is defined as a main chip of the ADC serial queue, the main chip further comprises serial peripheral interfaces, the serial peripheral interfaces are respectively connected with the L ADC channels of the main chip and the second audio interfaces of the main chip, the main chip is respectively connected with the SOC chip through the second audio interfaces of the main chip and the serial peripheral interfaces of the main chip, and each ADC serial queue transmits the audio digital signals to the SOC chip through the second audio interfaces of the main chip or the serial peripheral interfaces of the main chip.

2. The audio acquisition system according to claim 1, wherein each ADC channel comprises a microphone and an analog-to-digital converter respectively connected to the microphone and the first audio interface, the microphone is configured to acquire an external sound signal and convert the sound signal into an audio analog signal, the analog-to-digital converter is configured to process and convert the audio analog signal into the audio digital signal, and the analog-to-digital converter of the main chip is further connected to the serial peripheral interface.

3. The audio acquisition system of claim 2 wherein each said ADC chip further comprises a synchronization module for receiving a synchronization signal; in the same ADC series queue, a synchronization module of the main chip is connected with the SOC chip and simultaneously connected with the synchronization module of the next ADC chip, and the synchronization module of the main chip is used for receiving the synchronization signal of the SOC chip and transmitting the synchronization signal to the synchronization module of the next ADC chip.

4. The audio acquisition system of claim 3, wherein each ADC chip further comprises a synchronous serial interface for configuring each ADC chip to operate in different modes according to the synchronization signal.

5. A design method of the audio acquisition system based on claim 4, the method comprising the following steps:

configuring the working clock frequency of the ADC series queue;

6. The method of claim 5, wherein in the step of configuring the AD sampling rate, the AD sampling precision, the number of ADC channels for collecting the audio digital signal, the transmission mode of the second audio interface or the serial peripheral interface of the main chip, and the transmission rate of the audio digital signal, the transmission rate of the audio digital signal is greater than or equal to × AD sampling precision × AD sampling rate of the number of ADC channels for collecting the audio digital signal.

7. The method of claim 5, wherein in the step of configuring the working clock frequency of the ADC series queue, the working clock frequency of the ADC series queue is greater than or equal to 2 × AD sampling rate × AD sampling precision.