CN112506826B

CN112506826B - Communication method, system, master chip and slave chip

Info

Publication number: CN112506826B
Application number: CN202011380538.1A
Authority: CN
Inventors: 李高峰; 纪纲; 李维高
Original assignee: Beijing Baidu Netcom Science and Technology Co Ltd
Current assignee: Beijing Baidu Netcom Science and Technology Co Ltd
Priority date: 2020-11-30
Filing date: 2020-11-30
Publication date: 2023-12-19
Anticipated expiration: 2040-11-30
Also published as: CN112506826A

Abstract

The application provides a communication method, a communication system, a master chip and a slave chip, relates to the technical field of computers, and in particular relates to the technical field of artificial intelligence such as voice technology and deep learning. The specific implementation scheme is as follows: storing the main data to a second data queue through a data bus; receiving an interrupt signal sent by a slave chip through a unidirectional bus; reading slave data from the first data queue through the data bus according to the interrupt signal; the slave chip is provided with a first data queue and a second data queue. The communication method of the embodiment of the application can realize reliable, high-speed and full-duplex communication between the master chip and the slave chip.

Description

Communication method, system, master chip and slave chip

Technical Field

The application relates to the technical field of computers, in particular to the technical field of artificial intelligence such as voice technology and deep learning, and especially relates to a communication method, a communication system, a master chip and a slave chip.

Background

With expansion of the market and application fields of the internet of things, IOT (Internet of Things ) devices are gradually popularized in people's lives, and research and development and application of IOT devices are continuously receiving attention. The application scenario of IOT devices relates to a wide range of fields, such as speech recognition and speech synthesis AIOT (Artificial Intelligence & Internet of Things, artificial intelligence internet of things), and there are usually one to several chips in one device to process different transactions, and the chips each independently operate, but need to communicate at any time to complete a series of interactions.

In each chip, actively generated events and data need to be sent to the opposite terminal at any time, and data and events sent by the opposite terminal need to be monitored at any time. In the related art, conventional inter-chip communication schemes all rely on a single hardware bus, or a special hardware protocol, such as USB (Universal Serial Bus ), etc.

Disclosure of Invention

The application provides a communication method, a communication system, a master chip and a slave chip.

According to an aspect of the present application, there is provided a communication method, in which a master chip and a slave chip communicate with each other through a data bus and a unidirectional bus, the slave chip having a first data queue and a second data queue, the method comprising:

storing main data to the second data queue through the data bus;

receiving an interrupt signal sent by the slave chip through the unidirectional bus; and

reading slave data from the first data queue through the data bus according to the interrupt signal.

According to another aspect of the present application, there is provided a communication method, in which communication is performed between a master chip and a slave chip through a data bus and a unidirectional bus, the slave chip having a first data queue and a second data queue, the method comprising:

Storing slave data to the first data queue via the data bus; and

and sending an interrupt signal to the master chip through the unidirectional bus so that the master chip reads the slave data from the first data queue through the data bus according to the interrupt signal.

According to another aspect of the present application, there is provided a communication system comprising a master chip and a slave chip, the master chip and the slave chip communicating therebetween via a data bus and a unidirectional bus, the slave chip having a first data queue and a second data queue, wherein,

the main chip is used for storing main data to the second data queue through the data bus;

the slave chip is used for sending an interrupt signal to the master chip through the unidirectional bus;

the master chip is further configured to read slave data from the first data queue through the data bus according to the interrupt signal.

According to another aspect of the present application, there is provided a master chip, wherein the master chip is connected to a slave chip through a first master communication interface and a second master communication interface, respectively, the slave chip having a first data queue and a second data queue, the master chip comprising:

A main data transmitting unit for storing main data to the second data queue through the first main communication interface;

the signal receiving unit is used for receiving the interrupt signal sent by the slave chip through the second master communication interface; and

and the slave data reading unit is used for reading slave data from the first data queue through the first main communication interface according to the interrupt signal.

According to another aspect of the present application, there is provided a slave chip, wherein the slave chip is connected to a master chip through a first slave communication interface and a second slave communication interface, respectively, the slave chip having a first data queue and a second data queue, the slave chip comprising:

a slave data transmitting unit for storing slave data to the first data queue through the first slave communication interface; and

and the signal sending unit is used for sending an interrupt signal to the master chip through the second slave communication interface so that the master chip reads the slave data from the first data queue according to the interrupt signal.

According to another aspect of the present application, there is provided an electronic device including:

at least one processor; and

A memory communicatively coupled to the at least one processor; wherein,

the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the communication method of the embodiments of one or more aspects described above.

According to another aspect of the present application, there is provided a non-transitory computer-readable storage medium having stored thereon computer instructions for causing the computer to execute the communication method according to the embodiment of the above aspect or the above another aspect.

According to another aspect of the present application, there is provided a computer program product comprising a computer program which, when executed by a processor, implements the communication method according to the embodiments of the above aspect or the above another aspect.

It should be understood that the description of this section is not intended to identify key or critical features of the embodiments of the application or to delineate the scope of the application. Other features of the present application will become apparent from the description that follows.

Drawings

The drawings are for better understanding of the present solution and do not constitute a limitation of the present application. Wherein:

Fig. 1 is a schematic flow chart of a communication method according to an embodiment of the present application;

fig. 2 is a schematic diagram of data transmission between master and slave chips according to an embodiment of the present application;

fig. 3 is a schematic structural diagram of data in an IO queue according to an embodiment of the present application;

FIG. 4 is a schematic diagram of data usage in IO queues according to an embodiment of the present disclosure;

fig. 5 is a flow chart of another communication method according to an embodiment of the present application;

fig. 6 is a schematic structural diagram of a communication system according to an embodiment of the present application;

fig. 7 is a schematic structural diagram of a main chip according to an embodiment of the present application;

fig. 8 is a schematic structural diagram of a slave chip according to an embodiment of the present application; and

fig. 9 is a block diagram of an electronic device of a communication method according to an embodiment of the present application.

Detailed Description

Exemplary embodiments of the present application are described below in conjunction with the accompanying drawings, which include various details of the embodiments of the present application to facilitate understanding, and should be considered as merely exemplary. Accordingly, one of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the present application. Also, descriptions of well-known functions and constructions are omitted in the following description for clarity and conciseness.

Communication methods, systems, master chips, and slave chips according to embodiments of the present application are described below with reference to the accompanying drawings.

Artificial intelligence is the discipline of studying certain mental processes and intelligent behaviors (e.g., learning, reasoning, thinking, planning, etc.) of a person using a computer, both in the technical field of hardware and in the technical field of software. Artificial intelligence hardware technologies generally include technologies such as sensors, dedicated artificial intelligence chips, cloud computing, distributed storage, big data processing, and the like; the artificial intelligence software technology comprises a computer vision technology, a voice recognition technology, a natural language processing technology, a deep learning technology, a big data processing technology, a knowledge graph technology and the like.

Speech technology refers to the key technologies in the computer field, including automatic speech recognition technology and speech synthesis technology.

Deep learning is a new research direction in the field of machine learning. Deep learning is the inherent regularity and presentation hierarchy of learning sample data, and the information obtained during such learning is helpful in interpreting data such as text, images and sounds. Its final goal is to have the machine have analytical learning capabilities like a person, and to recognize text, image, and sound data. Deep learning is a complex machine learning algorithm that achieves far greater results in terms of speech and image recognition than prior art.

The communication method provided in the embodiments of the present application may be performed by an electronic device, which may be a PC (Personal Computer ) computer, tablet computer, palm computer, smart phone, etc., and is not limited herein.

In an embodiment of the application, the electronic device may be provided with a processing component, a storage component and a driving component. Alternatively, the driving component and the processing component may be integrally provided, and the storage component may store an operating system, an application program, or other program modules, and the processing component implements the communication method provided by the embodiments of the present application by executing the application program stored in the storage component.

Fig. 1 is a flow chart of a communication method according to an embodiment of the present application.

The communication method of the embodiment of the application may be further executed by the master chip provided by the embodiment of the application, where the master chip may be configured in the electronic device to store the master data into the second data queue through the data bus, receive the interrupt signal sent by the slave chip through the unidirectional bus, and read the slave data from the first data queue through the data bus according to the interrupt signal, so as to implement reliable, high-speed and full duplex communication between the master chip and the slave chip.

In the embodiment of the application, the master chip and the slave chip can communicate through a data bus and a unidirectional bus, and the slave chip can be provided with a first data queue and a second data queue.

Specifically, the master chip may be connected to the slave chip through a data bus, and the slave chip may be connected to the master chip through a unidirectional bus. The first data queue may store data transmitted from the slave chip to the master chip, and the second data queue may store data transmitted from the master chip to the slave chip.

To illustrate the above embodiment clearly, in one embodiment of the present application, the data bus may be a serial peripheral interface SPI (Serial Peripheral Interface ) bus, and the unidirectional bus may be a general purpose input/output port GPIO (General Purpose Input Output, general purpose input/output port) bus.

It should be noted that, the SPI bus described in the above embodiment may be a high-speed, full duplex, synchronous communication bus, which has advantages of supporting full duplex communication, simple communication, and data transmission rate block, and has characteristics of high-speed, synchronous, full duplex, non-differential, bus type, and master-slave communication modes.

The GPIO bus described in the above embodiments may be a single serial line (i.e., GPIO hop delay interrupt line).

The first data queue and the second data queue described in the above embodiments may both be opened up on a slave chip, and may be collectively referred to as an IO (Input/Output) queue, which may implement a buffer function similar to a TCP (Transmission Control Protocol ) protocol stack, without any limitation herein. The Input (Input) queue in the IO queue refers to a queue for transmitting data from the chip to the master chip and corresponds to a first data queue, and the Output (Output) queue in the IO queue refers to a queue for transmitting data from the master chip to the slave chip and corresponds to a second data queue.

In this embodiment of the present application, the SPI bus needs to have one master (master) end and slave (slave) end, based on which the slave chip can be operated in the slave mode and the master chip is operated in the master mode, so that the master chip and the slave chip can initiate high-speed bidirectional communication by the master chip (i.e., the master end), and note that only the master chip (i.e., the master end) can initiate communication when only the SPI bus is used. The data communicated can be binary data on the SPI bus, and the data can be used for transmitting only the indiscriminate data blocks without differentiating the service, so that the universality of data transmission is realized.

The GPIO bus is used as a single serial line, can register as a master chip end jump delay interrupt, and can receive an interrupt signal by pulling up or pulling down an electrical frequency from the slave chip end, and only the interrupt signal can play an essential role in the communication method of the embodiment of the application. This is an indiscriminate synchronization signal that enables high-speed communication initiated by the slave chip (i.e., the slave) in conjunction with the SPI bus, IO queuing, etc. described above. The interrupt signal can also have software fault tolerance in design, 1-n signals can be provided without corresponding to one signal in each communication, and the software protocol controls the safety and reliability of data. Where n may be a positive integer.

As shown in fig. 1, the communication method may include:

step 101, storing the main data to the second data queue through the data bus. It should be noted that the main data described in this embodiment may be a binary data.

In embodiments of the present application, IO queues (i.e., first and second data queues) may be created during the slave chip software initialization phase.

For example, it is assumed that the communication method of the embodiment of the present application is applied to a smart sound, where after the smart sound is powered on, the master chip and the slave chip may be controlled to perform software initialization, so that the slave chip creates an IO queue in the software initialization stage. During operation of the smart stereo, the master chip may store master data to the second data queue via a data bus (e.g., an SPI bus) for subsequent retrieval of the data from the chip.

Step 102, receiving an interrupt signal sent from the chip through the unidirectional bus.

For example, it is assumed that the communication method of the embodiments of the present application is applied to a smart sound, where during the operation of the smart sound, the slave chip may generate an interrupt signal by pulling up or pulling down an electrical frequency, and send the interrupt signal to the master chip through a unidirectional bus (e.g., a GPIO bus).

Step 103, reading the slave data from the first data queue through the data bus according to the interrupt signal. It should be noted that the slave data described in this embodiment may also be binary data.

For example, it is assumed that the communication method of the embodiment of the present application is applied to the smart sound, where if the master chip receives the interrupt signal sent by the slave chip through the unidirectional bus during the operation of the smart sound, the slave data may be read from the first data queue through the data bus according to the interrupt signal.

In the embodiment of the application, the main data is stored into the second data queue through the data bus, the interrupt signal sent by the slave chip through the unidirectional bus is received, and the slave data is read from the first data queue through the data bus according to the interrupt signal, so that reliable, high-speed and full-duplex communication between the master chip and the slave chip can be realized.

To clearly illustrate the above embodiment, in one embodiment of the present application, the second data queue may correspond to a second synchronization counter, wherein after storing the main data to the second data queue through the data bus, updating a second count value of the second synchronization counter may be further included, wherein the slave chip reads the main data from the second data queue according to the second count value of the second synchronization counter.

It should be noted that the second synchronous counter in this embodiment may be a register, which is mainly used for counting, and since the setting of the queues is directional, one queue always reads from one end and writes to the other end, and the same register only has one end, and when one data is stored in the queue, the register is incremented by one.

For example, referring to fig. 2, it is assumed that the communication method of the embodiment of the present application is applied to the smart sound, where after the master chip stores the master data into the second data queue through the data bus during the operation of the smart sound, a count control command may also be sent to the slave chip through the data bus, so that the slave chip controls the second synchronization counter to increment by one according to the count control command, and generates the second count value, that is, updates the second count value of the second synchronization counter. Then, the slave chip may acquire a second count value from among the second synchronous counters, and may generate an offset address according to the second count value, and read the master data from among the second data queues according to the offset address. Therefore, the master chip can send data to the slave chip only through the data bus, and the data transmission device has the advantages of simple structure and simple logic control, and can realize reliable and high-speed data transmission.

To clearly illustrate the above embodiment, in one embodiment of the present application, the first data queue may correspond to a first synchronization counter, updating a first count value of the first synchronization counter after the slave chip stores the slave data into the first data queue through the data bus, reading the slave data from the first data queue through the data bus according to the interrupt signal may include reading the first count value from the first synchronization counter according to the interrupt signal, generating an offset address according to the first count value, and reading the slave data from the first data queue according to the offset address.

It should be noted that, the first synchronization counter described in this embodiment may also be a register, which is mainly used for counting, and since the setting of the queues is directional, one queue always reads from and writes to the other, and each register only has one write, when one data is stored in the queue, the register is incremented, so that the synchronization of the data can be achieved.

For example, referring to fig. 2, it is assumed that the communication method of the embodiment of the present application is applied to the smart sound, where during the operation of the smart sound, the slave chip may store slave data into the first data queue through the data bus, and then may read the value in the first synchronization counter, increment the value, and then re-write the value into the first synchronization counter, that is, update the first count value of the first synchronization counter. The slave chip then sends an interrupt signal (e.g., a GPIO interrupt signal) to the master chip over the unidirectional bus. After receiving the interrupt signal, the master chip can read a first count value from the first synchronous counter according to the interrupt signal, generate an offset address according to the first count value, and read slave data from the first data queue according to the offset address. Further, the master chip may be represented by the formula: w= (Y% 128) Z, where W may be an offset address, Y may be a first count value, and Z may be a size of data in the first data queue. Therefore, the slave chip can send data to the master chip through the data bus and the unidirectional bus, the problem that in the related art, the master chip can only send data to the slave chip through the master chip between the master chip and the slave chip is solved, meanwhile, full duplex communication between the master chip and the slave chip is realized, communication and service can be decoupled, and research and development efficiency and product stability are greatly improved.

It should be noted that, the first synchronization counter (e.g., register) described in this embodiment may be 32 bits (bit) in size, and may start from 0 after the count overflows, and the size of the total data in the first data queue is limited, which may depend on the slave chip memory, for example, may be currently set to 128 queue capacities according to the slave chip memory.

For clarity of illustration of the above embodiment, in the embodiment of the present application, the structure of data in the IO queue may be as shown in fig. 3, and each data may be 16Byte (Byte) content.

Wherein, the ID can represent a unique identification of the session, such as once identified as a session; TYPE may represent data TYPE, such as data transferred, control commands; IDX may represent a packet of data, such as 1200, for which one protocol packet is not complete, and idx=1, idx=2, idx=3. LEN may represent the actual length of the data in the queue, and LEN may be 0 if a control command is transmitted; REMAIN may be a 6Byte reserved field for alignment, and may also be used for protocol extensions; the POINT may be a 4Byte data address pointing to the actual data, and may be read and written through the SPI bus, and if LEN is 0, it is indicated that a control command is transmitted, and the POINT content may not be considered.

Specifically, referring to fig. 4, when DATA is sent between the master chip and the slave chip, if the DATA len is greater than 4Byte, writing a len value of the DATA sent by 4Byte in a DATA segment, after receiving the DATA, allocating a writable address according to len, and replying that type_dsp_data_tx (i.e. independently defined TYPE) carries the writable address, wherein id must be the id when requested; the sending end sends corresponding data after receiving the writable address. If len is smaller than 4Byte, the data to be transmitted is written in the data segment and directly transmitted. The type of communication can be defined independently according to the service requirement.

It should be noted that, the id described in this embodiment may be automatically generated according to a preset generation algorithm during session generation, where the preset generation algorithm may be calibrated according to an actual situation.

Fig. 5 is a flow chart of another communication method according to an embodiment of the present application.

The communication method of the embodiment of the application can be further executed by the slave chip provided by the embodiment of the application, and the slave chip can be configured in the electronic device to store the slave data into the first data queue through the data bus and send the interrupt signal to the master chip through the unidirectional bus, so that the master chip reads the slave data from the first data queue through the data bus according to the interrupt signal, and reliable, high-speed and full-duplex communication between the master chip and the slave chip is realized.

To clearly illustrate the above embodiment, in one embodiment of the present application, the data bus may be a serial peripheral interface SPI bus, and the unidirectional bus may be a general purpose input/output GPIO bus.

The first data queue and the second data queue described in the above embodiments may both be opened up on the slave chip, and may be collectively referred to as an IO queue, which may implement a buffer function similar to a TCP protocol stack, without any limitation herein. The Input (Input) queue in the IO queue refers to a queue for transmitting data from the chip to the master chip and corresponds to a first data queue, and the Output (Output) queue in the IO queue refers to a queue for transmitting data from the master chip to the slave chip and corresponds to a second data queue.

As shown in fig. 5, the communication method may include:

step 501, store slave data to a first data queue via a data bus. It should be noted that the slave data described in this embodiment may be binary data.

For example, it is assumed that the communication method of the embodiment of the present application is applied to a smart sound, where after the smart sound is powered on, the master chip and the slave chip may be controlled to perform software initialization, so that the slave chip creates an IO queue in the software initialization stage. During smart sound operation, the slave chip may store slave data to the first data queue via a data bus (e.g., SPI bus) for subsequent master chips to acquire the data.

Step 502, an interrupt signal is sent to the master chip through the unidirectional bus, so that the master chip reads the slave data from the first data queue through the data bus according to the interrupt signal.

For example, it is assumed that the communication method of the embodiments of the present application is applied to a smart sound, where during the operation of the smart sound, the slave chip may generate an interrupt signal by pulling up or pulling down an electrical frequency, and send the interrupt signal to the master chip through a unidirectional bus (e.g., a GPIO bus). After receiving the interrupt signal, the master chip can read the slave data from the first data queue through the data bus according to the interrupt signal.

In the embodiment of the application, the slave data is stored into the first data queue through the data bus, and the interrupt signal is sent to the master chip through the unidirectional bus, so that the master chip reads the slave data from the first data queue through the data bus according to the interrupt signal, and therefore reliable, high-speed and full-duplex communication between the master chip and the slave chip can be achieved.

In an embodiment of the present application, the second data queue corresponds to a second synchronization counter, and the second count value of the second synchronization counter is updated after the main chip stores the main data into the second data queue through the data bus, and the communication method may further include reading the main data from the second data queue according to the second count value of the second synchronization counter.

In one embodiment of the present application, the first data queue corresponds to a first synchronization counter, where after the slave data is stored into the first data queue through the data bus, a first count value of the first synchronization counter is updated, so that the master chip reads the first count value from the first synchronization counter according to the interrupt signal; and generating an offset address according to the first count value, and reading the slave data from the first data queue according to the offset address.

It should be noted that the foregoing explanation of the communication method embodiment is also applicable to the communication method of this embodiment, and will not be repeated here.

According to the communication method, the slave data are stored into the first data queue through the data bus, and the interrupt signal is sent to the master chip through the unidirectional bus, so that the master chip reads the slave data from the first data queue through the data bus according to the interrupt signal, and therefore reliable, high-speed and full-duplex communication between the master chip and the slave chip can be achieved.

Fig. 6 is a schematic structural diagram of a communication system according to an embodiment of the present application.

The communication system of the embodiment of the application can be configured in the electronic equipment to realize that the master chip stores the master data into the second data queue through the data bus, the slave chip sends an interrupt signal to the master chip through the unidirectional bus, and the master chip reads the slave data from the first data queue through the data bus according to the interrupt signal.

As shown in fig. 6, the communication system 600 may include: a master chip 610 and a slave chip 620.

In the embodiment of the present application, the master chip 610 and the slave chip 620 may communicate with each other through a data bus and a unidirectional bus, and the slave chip 620 may have a first data queue and a second data queue.

Specifically, the master chip 610 may be connected to the slave chip 620 through a data bus, and the slave chip 620 may be connected to the master chip 610 through a unidirectional bus. The first data queue may store data transmitted from the chip 620 to the master chip 610 and the second data queue may store data transmitted from the master chip 610 to the slave chip 620.

The first data queue and the second data queue described in the above embodiments may both be opened up on the slave chip 620, and may be collectively referred to as an IO queue, which may implement a buffer function similar to a TCP protocol stack, without any limitation herein. Where Input (Input) queues in the IO queues refer to queues that send data from the chip 620 to the master chip 610 correspond to a first data queue, and Output (Output) queues in the IO queues refer to queues that the master chip 610 sends data to the slave chip 620 correspond to a second data queue.

In this embodiment, the SPI bus communication needs to have a master (master) at one end and a slave (slave) at the other end, based on which the slave chip 620 can be operated in the slave mode and the master chip 610 can be operated in the master mode, so that the master-slave chip can initiate high-speed bidirectional communication by the master chip 610 (i.e., the master), and note that only the master chip 610 (i.e., the master) can initiate communication when only the SPI bus is used. The data communicated can be binary data on the SPI bus, and the data can be used for transmitting only the indiscriminate data blocks without differentiating the service, so that the universality of data transmission is realized.

The GPIO bus, as a single serial line, may be registered as a master chip 610 end hop delay interrupt, and an electrical frequency is pulled up or down from a slave chip 620 end, where the master chip 610 (i.e., the master end) may receive an interrupt signal, and only the interrupt signal may play an essential role in the communication system of the embodiment of the present application. This is an indiscriminate synchronization signal that enables high-speed communication initiated by the slave chip 620 (i.e., the slave) in conjunction with the SPI bus, IO queuing, etc., described above. The interrupt signal can also have software fault tolerance in design, 1-n signals can be provided without corresponding to one signal in each communication, and the software protocol controls the safety and reliability of data. Where n may be a positive integer.

The main chip 610 is configured to store main data to the second data queue through the data bus. It should be noted that the main data described in this embodiment may be a binary data.

In embodiments of the present application, IO queues (i.e., first and second data queues) may be created during the slave chip 620 software initialization phase.

For example, it is assumed that the communication system 600 of the embodiment of the present application is applied to a smart sound device, where after the smart sound device is powered on, the master-slave chip may be controlled to perform software initialization, so that the slave chip 620 creates an IO queue during the software initialization stage. During smart sound operation, the master chip 610 may store master data to the second data queue via a data bus (e.g., an SPI bus) for subsequent retrieval of the data from the chip 620.

The slave chip 620 is used to send an interrupt signal to the master chip 610 via a unidirectional bus.

For example, it is assumed that the communication system 600 of the present embodiment is applied to a smart sound device, where during the operation of the smart sound device, the slave chip 620 may generate an interrupt signal by pulling up or pulling down an electrical frequency, and send the interrupt signal to the master chip 610 through a unidirectional bus (e.g., a GPIO bus).

The master chip 610 is further configured to read slave data from the first data queue through the data bus according to the interrupt signal. It should be noted that the slave data described in this embodiment may also be binary data.

For example, it is assumed that the communication system 600 of the embodiment of the present application is applied to a smart sound, where, during the operation of the smart sound, if the master chip 610 receives an interrupt signal sent by the slave chip 620 through the unidirectional bus, the master chip 610 may read the slave data from the first data queue through the data bus according to the interrupt signal.

In the embodiment of the application, the master chip stores the master data into the second data queue through the data bus, the slave chip sends the interrupt signal to the master chip through the unidirectional bus, and the master chip reads the slave data from the first data queue through the data bus according to the interrupt signal. Thus, reliable, high-speed and full duplex communication between the master chip and the slave chip can be realized.

In one embodiment of the present application, the second data queue corresponds to a second synchronization counter, wherein the master chip 610 is further configured to update a second count value of the second synchronization counter after storing the master data to the second data queue through the data bus; the slave chip 620 is further configured to read the master data from the second data queue according to the second count value of the second synchronization counter.

In one embodiment of the present application, the first data queue corresponds to a first synchronization counter, where the slave chip 620 is further configured to store slave data to the first data queue through the data bus, and update a first count value of the first synchronization counter; the main chip 610 specifically serves to: reading a first count value from the first synchronous counter according to the interrupt signal; and generating an offset address according to the first count value, and reading the slave data from the first data queue according to the offset address.

It should be noted that the foregoing explanation of the communication method embodiment is also applicable to the communication system of this embodiment, and will not be repeated here.

According to the communication system of the embodiment of the application, the master chip stores the master data into the second data queue through the data bus, the slave chip sends the interrupt signal to the master chip through the unidirectional bus, and the master chip reads the slave data from the first data queue through the data bus according to the interrupt signal. Thus, reliable, high-speed, full duplex communication between the master and slave chips can be realized.

Fig. 7 is a schematic structural diagram of a main chip according to an embodiment of the present application.

The master chip of the embodiment of the application can be configured in the electronic device so as to realize that the master data transmitting unit stores the master data into the second data queue through the first master communication interface, the signal receiving unit receives the interrupt signal sent by the slave chip through the second master communication interface, and the slave data reading unit reads the slave data from the first data queue through the first master communication interface according to the interrupt signal.

In this embodiment of the present application, the master chip may be connected to the slave chip through the first master communication interface and the second master communication interface, and the slave chip may have a first data queue and a second data queue, where data sent from the slave chip to the master chip may be stored in the first data queue, and data sent from the master chip to the slave chip may be stored in the second data queue.

The first main communication interface is connected with the slave chip through a data bus, the second main communication interface is connected with the slave chip through a unidirectional bus, wherein the data bus can be a serial peripheral interface SPI bus, and the unidirectional bus can be a general purpose input/output port GPIO bus.

As shown in fig. 7, the main chip 700 may include: a master data transmitting unit 710, a signal receiving unit 720, and a slave data reading unit 730.

Wherein the main data transmitting unit 710 is configured to store main data to the second data queue through the first main communication interface. It should be noted that the main data described in this embodiment may be a binary data.

For example, it is assumed that the master chip 700 of the embodiment of the present application is applied to a smart sound, where the master data transmitting unit 710 may store master data to the second data queue through the first master communication interface during the operation of the smart sound, so as to obtain the data from the chip later.

The signal receiving unit 720 is configured to receive an interrupt signal sent from the slave chip through the second master communication interface.

For example, it is assumed that the master chip 700 of the embodiment of the present application is applied to a smart sound, where the signal receiving unit 720 may receive an interrupt signal sent from the chip through the second master communication interface during the operation of the smart sound, where the interrupt signal may be generated by pulling up or pulling down an electrical frequency from the chip.

The slave data reading unit 730 is configured to read slave data from the first data queue through the first master communication interface according to the interrupt signal. It should be noted that the slave data described in this embodiment may also be binary data.

For example, it is assumed that the master chip 700 of the embodiment of the present application is applied to a smart sound, where, during the operation of the smart sound, if the signal receiving unit 720 receives an interrupt signal sent by the slave chip through the unidirectional bus, the slave data reading unit 730 may read the slave data from the first data queue through the first master communication interface according to the interrupt signal.

In the embodiment of the application, the master data transmitting unit stores master data into the second data queue through the first master communication interface, the signal receiving unit receives an interrupt signal sent by the slave chip through the second master communication interface, and the slave data reading unit reads slave data from the first data queue through the first master communication interface according to the interrupt signal. Thus, reliable, high-speed and full duplex communication between the master chip and the slave chip can be realized.

In one embodiment of the present application, the second data queue corresponds to a second synchronization counter, as shown in fig. 7, the master chip 700 may further include an updating unit 740, where the updating unit 740 is configured to update a second count value of the second synchronization counter after the master data transmitting unit 710 stores the master data into the second data queue through the first master communication interface, and the slave chip reads the master data from the second data queue according to the second count value of the second synchronization counter.

In one embodiment of the present application, the first data queue corresponds to a first synchronization counter, and the slave data reading unit 730 is specifically configured to read the first count value from the first synchronization counter according to the interrupt signal, where the first count value of the first synchronization counter is updated after the slave chip stores the slave data into the first data queue; and generating an offset address according to the first count value, and reading the slave data from the first data queue according to the offset address.

It should be noted that the foregoing explanation of the communication method embodiment is also applicable to the main chip of this embodiment, and will not be repeated here.

According to the master chip of the embodiment of the application, the master data transmitting unit stores master data into the second data queue through the first master communication interface, the signal receiving unit receives an interrupt signal transmitted by the slave chip through the second master communication interface, and the slave data reading unit reads slave data from the first data queue through the first master communication interface according to the interrupt signal. Thus, reliable, high-speed and full duplex communication between the master chip and the slave chip can be realized.

Fig. 8 is a schematic structural diagram of a slave chip according to an embodiment of the present application.

The slave chip of the embodiment of the application can be configured in the electronic device so as to enable the slave data sending unit to store the slave data into the first data queue through the first slave communication interface, and the signal sending unit sends the interrupt signal to the master chip through the second slave communication interface, so that the master chip reads the slave data from the first data queue according to the interrupt signal.

In this embodiment of the present application, the slave chip may be connected to the master chip through the first slave communication interface and the second slave communication interface, respectively, and the slave chip may have a first data queue and a second data queue, where data sent from the slave chip to the master chip may be stored in the first data queue, and data sent from the master chip to the slave chip may be stored in the second data queue.

The first slave communication interface can be connected with the main chip through a data bus, the second slave communication interface can be connected with the main chip through a unidirectional bus, wherein the data bus can be a serial peripheral interface SPI bus, and the unidirectional bus can be a general purpose input/output GPIO bus.

As shown in fig. 8, the slave chip 800 may include: a slave data transmission unit 810 and a signal transmission unit 820.

Wherein the slave data transmitting unit 810 is configured to store slave data to the first data queue through the first slave communication interface. It should be noted that the slave data described in this embodiment may be binary data.

For example, it is assumed that the slave chip 800 of the embodiment of the present application is applied to a smart sound device, where after the smart sound device is powered on, the master chip and the slave chip may be controlled to perform software initialization, so that the slave chip 800 creates an IO queue during the software initialization stage. During operation of the smart stereo, the slave data transmitting unit 810 may store slave data to the first data queue through the first slave communication interface so that the subsequent master chip can acquire the data.

The signal transmitting unit 820 is configured to transmit an interrupt signal to the master chip through the second slave communication interface, so that the master chip reads the slave data from the first data queue according to the interrupt signal.

For example, it is assumed that the slave chip 800 of the embodiment of the present application is applied to a smart sound, where the signal transmitting unit 820 may generate an interrupt signal by pulling up or pulling down an electrical frequency during the operation of the smart sound, and transmit the interrupt signal to the master chip through the second slave communication interface. After receiving the interrupt signal, the master chip can read the slave data from the first data queue through the data bus according to the interrupt signal.

In the embodiment of the application, the slave data transmitting unit stores the slave data into the first data queue through the first slave communication interface, and the signal transmitting unit transmits the interrupt signal to the master chip through the second slave communication interface, so that the master chip reads the slave data from the first data queue according to the interrupt signal. Thus, reliable, high-speed and full duplex communication between the master chip and the slave chip can be realized.

In one embodiment of the present application, the second data queue corresponds to a second synchronization counter, and the slave chip 800 may further include a master data reading unit 830 for reading the master data from the second data queue according to the second count value of the second synchronization counter, as shown in fig. 8, after the master chip stores the master data to the second data queue.

In one embodiment of the present application, the slave chip 800 may further include an updating unit 840 as shown in fig. 8, wherein the updating unit 840 is configured to update the first count value of the first synchronization counter after the slave data transmitting unit 810 stores the slave data into the first data queue through the first slave communication interface, so that the master chip reads the first count value from the first synchronization counter according to the interrupt signal; and generating an offset address according to the first count value, and reading the slave data from the first data queue according to the offset address.

It should be noted that the foregoing explanation of the communication method embodiment is also applicable to the slave chip of this embodiment, and will not be repeated here.

According to the slave chip of the embodiment of the application, the slave data sending unit stores slave data into the first data queue through the first slave communication interface, and the signal sending unit sends an interrupt signal to the master chip through the second slave communication interface, so that the master chip reads the slave data from the first data queue according to the interrupt signal. Thus, reliable, high-speed and full duplex communication between the master chip and the slave chip can be realized.

According to embodiments of the present disclosure, the present disclosure also provides an electronic device, a readable storage medium and a computer program product.

Fig. 9 shows a schematic block diagram of an example electronic device 900 that may be used to implement embodiments of the present disclosure. Electronic devices are intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The electronic device may also represent various forms of mobile devices, such as personal digital processing, cellular telephones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the disclosure described and/or claimed herein.

As shown in fig. 9, the apparatus 900 includes a computing unit 901 that can perform various appropriate actions and processes according to a computer program stored in a Read Only Memory (ROM) 902 or a computer program loaded from a storage unit 908 into a Random Access Memory (RAM) 903. In the RAM 903, various programs and data required for the operation of the device 900 can also be stored. The computing unit 901, the ROM 902, and the RAM 903 are connected to each other by a bus 904. An input/output (I/O) interface 905 is also connected to the bus 904.

Various components in device 900 are connected to I/O interface 905, including: an input unit 906 such as a keyboard, a mouse, or the like; an output unit 907 such as various types of displays, speakers, and the like; a storage unit 908 such as a magnetic disk, an optical disk, or the like; and a communication unit 909 such as a network card, modem, wireless communication transceiver, or the like. The communication unit 909 allows the device 900 to exchange information/data with other devices through a computer network such as the internet and/or various telecommunications networks.

The computing unit 901 may be a variety of general and/or special purpose processing components having processing and computing capabilities. Some examples of computing unit 901 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various specialized Artificial Intelligence (AI) computing chips, various computing units running machine learning model algorithms, a Digital Signal Processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 901 performs the respective methods and processes described above, such as a communication method. For example, in some embodiments, the communication method may be implemented as a computer software program tangibly embodied on a machine-readable medium, such as the storage unit 908. In some embodiments, part or all of the computer program may be loaded and/or installed onto the device 900 via the ROM 902 and/or the communication unit 909. When the computer program is loaded into the RAM 903 and executed by the computing unit 901, one or more steps of the communication method described above may be performed. Alternatively, in other embodiments, the computing unit 901 may be configured to perform the communication method by any other suitable means (e.g. by means of firmware).

Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuit systems, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), systems On Chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs, the one or more computer programs may be executed and/or interpreted on a programmable system including at least one programmable processor, which may be a special purpose or general-purpose programmable processor, that may receive data and instructions from, and transmit data and instructions to, a storage system, at least one input device, and at least one output device.

Program code for carrying out methods of the present disclosure may be written in any combination of one or more programming languages. These program code may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus such that the program code, when executed by the processor or controller, causes the functions/operations specified in the flowchart and/or block diagram to be implemented. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.

In the context of this disclosure, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. The machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and pointing device (e.g., a mouse or trackball) by which a user can provide input to the computer. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic input, speech input, or tactile input.

The systems and techniques described here can be implemented in a computing system that includes a background component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such background, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), the internet, and blockchain networks.

The computer system may include a client and a server. The client and server are typically remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server can be a cloud server, also called a cloud computing server or a cloud host, and is a host product in a cloud computing service system, so that the defects of high management difficulty and weak service expansibility in the traditional physical hosts and VPS service ("Virtual Private Server" or simply "VPS") are overcome. The server may also be a server of a distributed system or a server that incorporates a blockchain.

It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps recited in the present disclosure may be performed in parallel or sequentially or in a different order, provided that the desired results of the technical solutions of the present disclosure are achieved, and are not limited herein.

The above detailed description should not be taken as limiting the scope of the present disclosure. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present disclosure are intended to be included within the scope of the present disclosure.

Claims

1. A communication method in which a master chip and a slave chip communicate with each other via a data bus and a unidirectional bus, the master chip being connected to the slave chip via the data bus, and the slave chip being connected to the master chip via the unidirectional bus, the slave chip having a first data queue corresponding to a first synchronous counter and a second data queue corresponding to a second synchronous counter, the method comprising:

Storing main data to the second data queue through the data bus, and updating a second count value of the second synchronous counter, wherein the slave chip reads the main data from the second data queue according to the second count value of the second synchronous counter;

updating a first count value of the first synchronization counter after the slave chip stores slave data to the first data queue through the data bus;

reading the first count value from among the first synchronous counters according to the interrupt signal;

and generating an offset address according to the first count value, and reading slave data from the first data queue according to the offset address.

2. The communication method of claim 1, wherein the first data queue stores therein data transmitted from the slave chip to the master chip, and the second data queue stores therein data transmitted from the master chip to the slave chip.

3. A communication method according to any of claims 1-2, wherein the data bus is a serial peripheral interface, SPI, bus and the unidirectional bus is a general purpose input/output, GPIO, bus.

4. A communication method in which a master chip and a slave chip communicate with each other via a data bus and a unidirectional bus, the master chip being connected to the slave chip via the data bus, and the slave chip being connected to the master chip via the unidirectional bus, the slave chip having a first data queue corresponding to a first synchronous counter and a second data queue corresponding to a second synchronous counter, the method comprising:

storing slave data to the first data queue via the data bus, updating a first count value of the first synchronization counter; and

transmitting an interrupt signal to the main chip through the unidirectional bus so that the main chip reads the first count value from the first synchronous counter according to the interrupt signal; generating an offset address according to the first count value, and reading the slave data from the first data queue according to the offset address;

updating a second count value of the second synchronization counter after the master chip stores master data to the second data queue through the data bus;

The slave chip reads the main data from the second data queue according to the second count value of the second synchronous counter.

5. The communication method of claim 4, wherein the first data queue stores therein data transmitted from the slave chip to the master chip, and the second data queue stores therein data transmitted from the master chip to the slave chip.

6. A communication method according to any of claims 4-5, wherein the data bus is a serial peripheral interface, SPI, bus and the unidirectional bus is a general purpose input/output, GPIO, bus.

7. A communication system comprising a master chip and a slave chip, the master chip and the slave chip communicating via a data bus and a unidirectional bus, the master chip being connected to the slave chip via the data bus and the slave chip being connected to the master chip via the unidirectional bus, the slave chip having a first data queue and a second data queue, the first data queue corresponding to a first synchronization counter, the second data queue corresponding to a second synchronization counter, wherein,

the main chip is further used for reading slave data from the first data queue through the data bus according to the interrupt signal;

the master chip is further configured to update a second count value of the second synchronization counter after storing master data to the second data queue through the data bus;

the slave chip is further configured to read the master data from the second data queue according to a second count value of the second synchronization counter;

the slave chip is further configured to store the slave data to the first data queue through the data bus, and update a first count value of the first synchronization counter;

the main chip is specifically used for:

reading the first count value from among the first synchronous counters according to the interrupt signal; and

and generating an offset address according to the first count value, and reading the slave data from the first data queue according to the offset address.

8. The communication system of claim 7, wherein the first data queue stores therein data transmitted from the slave chip to the master chip, and the second data queue stores therein data transmitted from the master chip to the slave chip.

9. A communication system as claimed in any one of claims 7 to 8, wherein the data bus is a serial peripheral interface, SPI, bus and the unidirectional bus is a general purpose input/output, GPIO, bus.

10. A master chip, wherein the master chip is connected to a slave chip through a first master communication interface and a second master communication interface, respectively, the slave chip has a first data queue and a second data queue, the first data queue corresponds to a first synchronization counter, the second data queue corresponds to a second synchronization counter, the master chip comprises:

a slave data reading unit for reading slave data from the first data queue through the first master communication interface according to the interrupt signal;

an updating unit, configured to update a second count value of the second synchronization counter after the main data transmitting unit stores main data into the second data queue through the first main communication interface, where the slave chip reads the main data from the second data queue according to the second count value of the second synchronization counter;

Updating a first count value of the first synchronization counter after the slave chip stores the slave data into the first data queue, wherein the slave data reading unit is specifically configured to:

11. The master chip of claim 10, wherein the first data queue stores therein data transmitted from the slave chip to the master chip and the second data queue stores therein data transmitted from the master chip to the slave chip.

12. A slave chip, wherein the slave chip is connected to a master chip through a first slave communication interface and a second slave communication interface, respectively, the slave chip having a first data queue and a second data queue, the first data queue corresponding to a first synchronization counter and the second data queue corresponding to a second synchronization counter, the slave chip comprising:

A signal transmitting unit, configured to transmit an interrupt signal to the master chip through the second slave communication interface, so that the master chip reads the slave data from the first data queue according to the interrupt signal;

an updating unit, configured to update a first count value of the first synchronization counter after the slave data transmitting unit stores slave data to the first data queue through the first slave communication interface, so that the master chip reads the first count value from the first synchronization counter according to the interrupt signal; generating an offset address according to the first count value, and reading the slave data from the first data queue according to the offset address;

updating a second count value of the second synchronization counter after the master chip stores master data to the second data queue, the slave chip further comprising:

and the main data reading unit is used for reading the main data from the second data queue according to the second count value of the second synchronous counter.

13. The slave chip of claim 12, wherein the first data queue stores therein data transmitted from the slave chip to the master chip, and the second data queue stores therein data transmitted from the master chip to the slave chip.

14. An electronic device, comprising:

at least one processor; and

a memory communicatively coupled to the at least one processor; wherein,

the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the communication method of any one of claims 1-3 or 4-6.

15. A non-transitory computer readable storage medium storing computer instructions for causing the computer to perform the communication method of any one of claims 1-3 or 4-6.