CN115145859A - Data transmission method and device, electronic equipment and storage medium - Google Patents
Data transmission method and device, electronic equipment and storage medium Download PDFInfo
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Abstract
The invention discloses a data transmission method, a data transmission device, electronic equipment and a storage medium, wherein the method comprises the following steps: constructing a first message unit according to a first target instruction to be transmitted; the first message unit comprises a message header and a message body, wherein the message header comprises a command field of a first target instruction and a structure identifier of the message body, and the message body comprises a data field of the first target instruction; sending the first message unit to the first memory so as to transmit the first message unit to other processors through the first memory; the number of data bits of the message header in the first message unit is the same as the bit width of the first memory. The technical scheme of the embodiment of the invention improves the data transmission efficiency among the processors, simplifies the data transmission logic among the processors, avoids the occurrence of data read-write errors and improves the accuracy of data transmission.
Description
Technical Field
The present invention relates to the field of communication technologies and chip technologies, and in particular, to a data transmission method and apparatus, an electronic device, and a storage medium.
Background
In a system on chip, information often needs to be transferred between multiple processors (e.g., central processing units) to cooperate to complete a specific task, and therefore, the efficiency of communication between the processors directly affects the operating efficiency of the system on chip.
Since the software of the soc usually runs on the bare core and there is no communication mechanism such as shared memory, pipeline, socket, etc. provided by the os, the communication between the processors generally needs to be implemented based on specific hardware (e.g. storage), and the transmission efficiency between the processors and the storage directly determines the communication efficiency between the processors in the soc.
In the prior art, the transmission of commands and data between processors is usually performed through different memories to realize the differential transmission of commands and data, but such a transmission mode has low information transmission efficiency between processors and excessively complex transmission logic, which further results in poor system performance of the system on chip.
Disclosure of Invention
The invention provides a data transmission method, a data transmission device, electronic equipment and a storage medium, and aims to solve the problem of low data transmission efficiency among processors in a system on chip.
According to an aspect of the present invention, a data transmission method includes:
constructing a first message unit according to a first target instruction to be transmitted; wherein the first message unit comprises a message header and a message body, the message header comprises a command field of the first target instruction and a structure identifier of the message body, and the message body comprises a data field of the first target instruction;
sending the first message unit to a first memory to transmit the first message unit to other processors through the first memory; wherein, the data bit number of the message header in the first message unit is the same as the bit width of the first memory.
The constructing a first message unit according to the first target instruction to be transmitted further includes: judging whether the data bit number of the message body is an integral multiple of the bit width of the first memory; if the data bit number of the message body is not an integral multiple of the bit width of the first memory, adding placeholder data in the message body so as to enable the data bit number of the message body to be an integral multiple of the bit width of the first memory. The data read by the first memory each time are from the same message unit, so that read-write errors caused by the fact that the data in different message units are mixed by the first memory are avoided, and the accuracy of data transmission is improved.
The constructing a first message unit according to the first target instruction to be transmitted further includes: acquiring a first receiver identifier matched with a first target instruction to be transmitted; constructing a first message unit according to the first target instruction and the first receiver identification; wherein the header of the first message unit includes the first recipient identification. The method and the device realize the sending of the directional instruction based on the shared memory, save the hardware resources of the memory and ensure the ordered sending of the directional instruction.
The method further comprises the following steps: in response to the second message unit being acquired through the second memory, the second message unit is analyzed to acquire a message header and a message body of the second message unit; wherein the second message unit is constructed based on a second target instruction; and executing the second target instruction according to the message header and the message body of the second message unit. The first processor respectively realizes data transmission and data reception through different memories, and the functionality of the first processor is greatly expanded.
The responding to the second message unit acquired through the second memory, analyzing the second message unit to acquire the message header and the message body of the second message unit includes: responding to a hardware arbitration mechanism based on a bus, acquiring a second message unit through a second memory, and analyzing the second message unit to acquire a message header and a message body of the second message unit; judging whether a second receiver identifier in the second message unit is the same as the identifier of the first processor or not; and if the second receiver identification in the second message unit is the same as the identification of the first processor, continuing to acquire the message body in the second message unit. The hardware arbitration mechanism based on the on-chip bus realizes natural mutual exclusion, and avoids communication conflict among the processors on the premise of not influencing the system performance.
After judging whether the second receiver identifier in the second message unit is the same as the identifier of the first processor, the method further comprises the following steps: if the second receiver identification in the second message unit is different from the identification of the first processor, judging whether a special memory exists between the first processor and the second receiver according to the second receiver matched with the second receiver identification; if the first processor and the second receiver are determined to have a special memory, sending the second message unit to the special memory so as to transmit the second message unit to the second receiver through the special memory; and if the fact that the special memory does not exist between the first processor and the second receiver is determined, the second message unit is sent to the second memory, so that the second message unit is continuously transmitted to the second receiver through the second memory. The transmission is carried out by the shared channel and the dedicated channel, so that the transmission efficiency of the message unit is improved.
Said sending said second message unit to said private store for transmission to said second recipient via said private store, comprising: and adjusting the data structure of the second message unit according to the bit width of the special memory, so that the data bit number of a message header in the second message unit is the same as the bit width of the special memory, and the data bit number of a message body in the second message unit is an integral multiple of the bit width of the special memory. When the first processor transmits the second message unit through the special memory, the data structure of the second message unit is adjusted to adapt to the bit width of the special memory, and the data transmission efficiency between the first processor and the special memory is further improved.
According to another aspect of the present invention, there is provided a data transmission apparatus including:
the message unit construction module is used for constructing a first message unit according to a first target instruction to be transmitted; wherein the first message unit comprises a message header and a message body, the message header comprises a command field of the first target instruction and a structure identifier of the message body, and the message body comprises a data field of the first target instruction;
the message unit sending module is used for sending the first message unit to a first memory so as to transmit the first message unit to other processors through the first memory; wherein the number of data bits of a message header in the first message unit is the same as the bit width of the first memory.
According to another aspect of the present invention, there is provided an electronic device, the electronic device including:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein the content of the first and second substances,
the memory stores a computer program executable by the at least one processor, the computer program being executable by the at least one processor to enable the at least one processor to perform the data transmission method according to any of the embodiments of the invention.
According to another aspect of the present invention, there is provided a computer-readable storage medium storing computer instructions for causing a processor to implement the data transmission method according to any one of the embodiments of the present invention when the computer instructions are executed.
According to the technical scheme of the embodiment of the invention, after the first message unit is constructed according to the first target instruction to be transmitted, the command field and the data field of the first target instruction are respectively stored in the message header and the message body, and then the first message unit is transmitted to other processors through the first memory, so that the information transmission efficiency among the processors is improved, the data transmission logic among the processors is simplified, meanwhile, the data bit number of the message header in the first message unit is the same as the bit width of the first memory, so that the first memory can obtain the complete message header through one-time reading, all data read by the first memory at this time are from the message header, the occurrence of data read-write errors is avoided, and the accuracy of data transmission is improved.
It should be understood that the statements in this section are not intended to identify key or critical features of the embodiments of the present invention, nor are they intended to limit the scope of the invention. Other features of the present invention will become apparent from the following description.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1A is a flowchart of a data transmission method according to an embodiment of the present invention;
fig. 1B is a schematic flowchart of a data transmission method according to an embodiment of the present invention;
fig. 1C is a schematic flowchart of a data transmission method according to an embodiment of the present invention;
fig. 2 is a flowchart of a data transmission method according to a second embodiment of the present invention;
fig. 3 is a schematic structural diagram of a data transmission apparatus according to a third embodiment of the present invention;
fig. 4 is a schematic structural diagram of an electronic device implementing the data transmission method according to the embodiment of the present invention;
Detailed Description
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Example one
Fig. 1A is a flowchart of a data transmission method according to an embodiment of the present invention, where the embodiment is applicable to data transmission through a memory based on a constructed message unit, the method may be executed by a data transmission device, the data transmission device may be implemented in a form of hardware and/or software, the data transmission device may be configured in a chip, and the chip may be integrated in an electronic device. As shown in fig. 1A, the method includes:
s101, constructing a first message unit according to a first target instruction to be transmitted; the first message unit comprises a message header and a message body, wherein the message header comprises a command field of the first target instruction and a structure identification of the message body, and the message body comprises a data field of the first target instruction.
The instruction transmitted between the processors consists of a command field and a data field; the command field indicates the type of operation to be performed by the instruction, that is, indicates what kind of operation should be performed by the instruction, for example, a read operation, a write operation, a disk partition operation, and the like, and different command fields are indicated by different binary codes; the data field is an action entity of the command field, and represents parameter information such as an execution object, an execution basis or a specific digital operand of the command field, for example, for a read operation, the data field may include a read object and a read speed; for a write operation, the data field may include a write object and a write speed; for disk partitioning operations, the data fields may include disk location and disk capacity; in the embodiment of the present invention, the types of the command field and the data field are not particularly limited.
The message body stores the data field of the first target instruction, and the data field can be directly used as the message body according to the actual number of bits of the data field, namely the number of bits of the data of the message body is consistent with the number of bits of the data field. In the message unit, the message head is positioned in front of the message body, the message head not only comprises a command field in the instruction, but also marks the structural composition of the message body through specific identification information; for example, if only the data field is included in the message body, the message header may identify the actual number of bits representing the data field by the number of bits in the message body; if the message body comprises other data besides the data field, the message header can represent the specific bit of the data field through the bit identifier of the data field, and then represent the initial position of the data field in the message body through the initial bit identifier, and further determine the data field in the message body according to the initial position and the specific bit; or the end position of the data field in the message body is represented by the end bit identifier, and the data field is determined according to the end position and the specific digit; the specific location of the data field in the message body can also be indicated according to the data field start bit identifier and the data field end bit identifier.
The data bit number of the message header is consistent with the data transmission bit width of the first memory, so that when the message header is written into the first memory, the first memory can obtain a complete message header through one-time reading, and all data read by the first memory at this time are from the message header, for example, the data transmission bit width of the first memory is 32 bits, 0-15 bits of the message header store a command field of a first target instruction, and 16-31 bits of the message header store a structure identifier of the message body; in particular, in order to ensure the normalization and consistency of the various elements on the chip, the memories on the chip used to implement shared communication between processors are generally the same type of memory, and therefore the bit width of each memory is generally the same; after the first processor acquires the first target instruction to be transmitted, a message header with a specified bit number can be constructed according to the fixed bit width; if the bit widths of the memories used for realizing the shared communication among the processors on the chip are different, after the first processor acquires the first target instruction, the first processor determines the memory between the first processor and the receiver according to the receiver of the first target instruction, and the memory is used as the data bit number of the constructed message header according to the bit width of the memory. The Memory in the embodiment of the present invention may include a Display Data Random Access Memory (DDRAM), a Static Random Access Memory (SRAM), a First-in First-out (FIFO) Memory, and the like.
Optionally, in an embodiment of the present invention, the constructing a first message unit according to the first target instruction to be transmitted further includes: judging whether the data bit number of the message body is an integral multiple of the bit width of the first memory; if the data bit number of the message body is not an integral multiple of the bit width of the first memory, adding placeholder data in the message body so as to enable the data bit number of the message body to be an integral multiple of the bit width of the first memory.
Specifically, if the data bit number of the message body constructed according to the data field is exactly an integral multiple of the bit width of the first memory, it is obvious that the message body is directly put into the message unit; if the data bit number of the message body constructed according to the data field is not an integral multiple of the bit width of the first memory, the data bit number of the message body is ensured to be an integral multiple of the bit width of the first memory by adding placeholder data (for example, a 0 value) at the tail end in the message body, and the structure identification of the message body in the message header indicates the respective positions of valid data (namely, the data field) and invalid data (namely, the placeholder data); for example, the width of the first memory is 4 bytes (i.e. 32 bits), the current data bit number of the message body is 60 bits, and then 4 bits of place-occupying data (e.g. binary "0000") are added at the rear end of the message body, so that it is ensured that data read by the first memory each time are from the same message unit, thereby avoiding that the first memory confuses data in different message units, resulting in read-write errors, and improving the accuracy of data transmission.
S102, sending the first message unit to a first memory so as to transmit the first message unit to other processors through the first memory; wherein, the data bit number of the message header in the first message unit is the same as the bit width of the first memory.
Because hardware resources of the system on chip are limited, in order to save memory resources, in the embodiment of the present invention, each memory may be used as a shared memory among three or more processors, as shown in fig. 1B, a plurality of processors are used as data senders of the first memory (in this case, a data receiver may be one or more), or as shown in fig. 1C, a plurality of processors are used as data receivers of the first memory (in this case, a data sender may be one or more); when the first processor is used as a data sending party of the first memory, if the first target instruction is a non-directional instruction, the first target instruction can be executed by any other processor, and even if the first memory corresponds to a plurality of data receiving parties, the first processor can directly construct a first message unit according to the first target instruction; if the first target instruction is a directive instruction, i.e., executed by the designated one or more processors, the first processor needs to designate the identity information of the recipient in the first message unit when the first memory corresponds to the plurality of data recipients.
Optionally, in an embodiment of the present invention, the constructing a first message unit according to the first target instruction to be transmitted further includes: acquiring a first receiver identifier matched with a first target instruction to be transmitted; constructing a first message unit according to the first target instruction and the first receiver identification; wherein the header of the first message unit includes the first recipient identification. Specifically, after the first target instruction is acquired, if it is determined that the instruction needs to be executed by a specific one or more processors, the first processor needs to acquire a receiver identifier (i.e., a first receiver identifier) of the instruction first, and add the receiver identifier to a message header of the first message unit, so that when other processors acquire the message unit, receiver information can be determined through the receiver identifier, and thus directional instruction transmission based on a shared memory is realized, and while memory hardware resources are saved, orderly transmission of directional instructions is ensured.
Optionally, in an embodiment of the present invention, the method further includes: in response to the second message unit being acquired through the second memory, the second message unit is analyzed to acquire a message header and a message body of the second message unit; wherein the second message unit is constructed based on a second target instruction; and executing the second target instruction according to the message header and the message body of the second message unit. The first processor can be used as a data sending party and sends instructions to other processors through the first memory, and also can be used as a data receiving party and receives the instructions sent by other processors through the second memory; when a second message unit sent by other processors is acquired through a second memory, a message header and a message body in the message unit are acquired through the analysis of the second message unit, then a command field is acquired through the message header, a data field is extracted from the message body based on the structure identification of the message body in the message header, the response to a second target instruction is realized based on the command field and the data field, and the first processor realizes data transmission and reception through different memories respectively, so that the functionality of the first processor is greatly expanded.
According to the technical scheme of the embodiment of the invention, after the first message unit is constructed according to the first target instruction to be transmitted, the command field and the data field of the first target instruction are respectively stored in the message header and the message body, and then the first message unit is transmitted to other processors through the first memory, so that the information transmission efficiency among the processors is improved, the data transmission logic among the processors is simplified, meanwhile, the data bit number of the message header in the first message unit is the same as the bit width of the first memory, so that the first memory can obtain the complete message header through one-time reading, all data read by the first memory at this time are from the message header, the occurrence of data read-write errors is avoided, and the accuracy of data transmission is improved.
Example two
Fig. 2 is a flowchart of a data transmission method according to a second embodiment of the present invention, where on the basis of the foregoing embodiment, in this embodiment, after a second message unit is obtained, it is determined whether a receiver of the second message unit is a first processor. As shown in fig. 2, the method includes:
s201, responding to a hardware arbitration mechanism based on a bus, acquiring a second message unit through a second memory, and analyzing the second message unit to acquire a message header and a message body of the second message unit; s202 is performed.
When the second storage corresponds to a plurality of data receivers or a plurality of data senders, if shared communication is realized through communication mechanisms such as a software shared memory, a pipeline or a socket, in order to avoid that a plurality of processors receive messages or send messages simultaneously, the conflict needs to be avoided by writing a mutual exclusion lock in a software form, however, the mutual exclusion operation brings great loss to the system performance; in the application, each processor is connected with the memory through the bus no matter as a data receiving party or a data sending party of the memory, natural mutual exclusion is realized through a hardware arbitration mechanism based on the on-chip bus, and communication conflict among the processors is avoided on the premise of not influencing system performance.
S202, judging whether a second receiver identifier in the second message unit is the same as the identifier of the first processor or not; if yes, go to S203; if not, executing S204.
S203, continuing to acquire the message body in the second message unit.
S204, judging whether a special memory exists between the first processor and a second receiver according to the second receiver matched with the second receiver identifier; if yes, go to S205; if not, go to S206.
S205, sending the second message unit to the special memory, so as to transmit the second message unit to the second receiver through the special memory.
The first processor acquires the second message unit, and a receiver of the second message unit is not the first processor, and obviously the second memory at least comprises two data receivers, so that the second memory is a shared memory of three or more processors, and when the message unit is transmitted in the shared memory, the second message unit cannot be acquired by the second receiver in time, and can also be acquired by other receivers first.
Optionally, in an embodiment of the present invention, the sending the second message unit to the private memory, so as to transmit the second message unit to the second recipient through the private memory, includes: and adjusting the data structure of the second message unit according to the bit width of the special memory, so that the data bit number of a message header in the second message unit is the same as the bit width of the special memory, and the data bit number of a message body in the second message unit is an integral multiple of the bit width of the special memory. And meanwhile, because the special memory is a special transmission channel between the first processor and a second receiver, the second receiver identifier in the message header of the second message unit can be deleted to reduce the data volume in the message header, and the data bits after the data is deleted can be filled by the occupied data.
S206, sending the second message unit to the second memory, so as to continuously transmit the second message unit to the second receiver through the second memory.
If no unshared private memory exists between the first processor and the second recipient, the second message unit is returned to the second memory so that the second recipient retrieves the message unit via the second memory.
According to the technical scheme of the embodiment of the invention, the natural mutual exclusion among the processors is realized based on a hardware arbitration mechanism of the on-chip bus, communication conflict among the processors is avoided on the premise of not influencing the system performance, meanwhile, the message head and the message body are obtained by analyzing the second message unit, and when the identification of the second receiver is judged not to be matched with the second receiver, the second message unit is transmitted to the second receiver through the special memory, so that the transmission efficiency of the message unit is further improved.
EXAMPLE III
Fig. 3 is a schematic structural diagram of a data transmission device according to a third embodiment of the present invention. As shown in fig. 3, the apparatus includes:
a message unit constructing module 301, configured to construct a first message unit according to a first target instruction to be transmitted; wherein the first message unit comprises a message header and a message body, the message header comprises a command field of the first target instruction and a structure identifier of the message body, and the message body comprises a data field of the first target instruction;
a message unit sending module 302, configured to send the first message unit to a first memory, so as to transmit the first message unit to other processors through the first memory; wherein, the data bit number of the message header in the first message unit is the same as the bit width of the first memory.
According to the technical scheme of the embodiment of the invention, after the first message unit is constructed according to the first target instruction to be transmitted, the command field and the data field of the first target instruction are respectively stored in the message header and the message body, and then the first message unit is transmitted to other processors through the first memory, so that the information transmission efficiency among the processors is improved, the data transmission logic among the processors is simplified, meanwhile, the data bit number of the message header in the first message unit is the same as the bit width of the first memory, so that the first memory can obtain the complete message header through one-time reading, all data read by the first memory at this time are from the message header, the occurrence of data read-write errors is avoided, and the accuracy of data transmission is improved.
Optionally, the message unit constructing module 301 is specifically configured to determine whether the data bit number of the message body is an integer multiple of the bit width of the first memory; if the data bit number of the message body is not an integral multiple of the bit width of the first memory, adding placeholder data in the message body so as to enable the data bit number of the message body to be an integral multiple of the bit width of the first memory.
Optionally, the message unit constructing module 301 is further specifically configured to obtain a first receiver identifier matched with the first target instruction to be transmitted; constructing a first message unit according to the first target instruction and the first receiver identification; wherein the header of the first message unit includes the first recipient identification.
Optionally, the data transmission device further includes:
the message unit acquisition module is used for responding to the acquisition of a second message unit through a second memory and analyzing the second message unit to acquire a message head and a message body of the second message unit; wherein the second message unit is constructed based on a second target instruction;
and the message unit execution module is used for executing the second target instruction according to the message header and the message body of the second message unit.
Optionally, the message unit obtaining module specifically includes:
a message unit obtaining unit, configured to, in response to a bus-based hardware arbitration mechanism, obtain a second message unit through a second memory, and analyze the second message unit to obtain a message header and a message body of the second message unit;
a receiver identifier determining unit, configured to determine whether a second receiver identifier in the second message unit is the same as the identifier of the first processor;
and the message body acquisition unit is used for continuously acquiring the message body in the second message unit if the identifier of the second receiver in the second message unit is the same as the identifier of the first processor.
Optionally, the message unit obtaining module further includes:
a dedicated memory determining unit, configured to determine, if a second receiver identifier in the second message unit is different from the identifier of the first processor, whether a dedicated memory exists between the first processor and the second receiver according to a second receiver identifier matching the second receiver identifier;
a dedicated memory forwarding unit, configured to send the second message unit to the dedicated memory if it is determined that a dedicated memory exists between the first processor and the second recipient, so as to transmit the second message unit to the second recipient through the dedicated memory;
a second memory returning unit, configured to send the second message unit to the second memory if it is determined that the dedicated memory does not exist between the first processor and the second receiver, so as to continue to transmit the second message unit to the second receiver through the second memory.
Optionally, the dedicated memory forwarding unit is specifically configured to adjust a data structure of the second message unit according to the bit width of the dedicated memory, so that the data bit number of the message header in the second message unit is the same as the bit width of the dedicated memory, and the data bit number of the message body in the second message unit is an integer multiple of the bit width of the dedicated memory.
The data transmission device provided by the embodiment of the invention can execute the data transmission method provided by any embodiment of the invention, and has corresponding functional modules and beneficial effects of the execution method.
Example four
FIG. 4 shows a schematic block diagram of an electronic device 10 that may be used to implement an embodiment of the invention. Electronic devices are intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The electronic device may also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smart phones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the inventions described and/or claimed herein.
As shown in fig. 4, the electronic device 10 includes at least one processor 11, and a memory communicatively connected to the at least one processor 11, such as a Read Only Memory (ROM) 12, a Random Access Memory (RAM) 13, and the like, wherein the memory stores a computer program executable by the at least one processor, and the processor 11 can perform various suitable actions and processes according to the computer program stored in the Read Only Memory (ROM) 12 or the computer program loaded from a storage unit 18 into the Random Access Memory (RAM) 13. In the RAM 13, various programs and data necessary for the operation of the electronic apparatus 10 may also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other via a bus 14. An input/output (I/O) interface 15 is also connected to the bus 14.
A number of components in the electronic device 10 are connected to the I/O interface 15, including: an input unit 16 such as a keyboard, a mouse, or the like; an output unit 17 such as various types of displays, speakers, and the like; a storage unit 18 such as a magnetic disk, an optical disk, or the like; and a communication unit 19 such as a network card, modem, wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information/data with other devices via a computer network such as the internet and/or various telecommunication networks.
In some embodiments, the data transfer method may be implemented as a computer program tangibly embodied in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and/or installed onto the electronic device 10 via the ROM 12 and/or the communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the data transmission method described above may be performed. Alternatively, in other embodiments, the processor 11 may be configured to perform the data transfer method by any other suitable means (e.g., by means of firmware).
Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuitry, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), system on a chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs that are executable and/or interpretable on a programmable system including at least one programmable processor, which may be special or general purpose, receiving data and instructions from, and transmitting data and instructions to, a storage system, at least one input device, and at least one output device.
A computer program for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the computer programs, when executed by the processor, cause the functions/acts specified in the flowchart and/or block diagram block or blocks to be performed. A computer program can execute entirely on a machine, partly on a machine, as a stand-alone software package partly on a machine and partly on a remote machine or entirely on a remote machine or server.
In the context of the present invention, a computer-readable storage medium may be a tangible medium that can contain, or store a computer program for use by or in connection with an instruction execution system, apparatus, or device. A computer readable storage medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. Alternatively, the computer readable storage medium may be a machine readable signal medium. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
To provide for interaction with a user, the systems and techniques described here can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and a pointing device (e.g., a mouse or a trackball) by which a user can provide input to the electronic device. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form, including acoustic, speech, or tactile input.
The systems and techniques described here can be implemented in a computing system that includes a back-end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such back-end, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), blockchain networks, and the Internet.
The computing system may include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server can be a cloud server, also called a cloud computing server or a cloud host, and is a host product in a cloud computing service system, so that the defects of high management difficulty and weak service expansibility in the traditional physical host and VPS service are overcome.
It should be understood that various forms of the flows shown above may be used, with steps reordered, added, or deleted. For example, the steps described in the present invention may be executed in parallel, sequentially, or in different orders, and are not limited herein as long as the desired results of the technical solution of the present invention can be achieved.
The above-described embodiments should not be construed as limiting the scope of the invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions may be made in accordance with design requirements and other factors. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A data transmission method, applied to a first processor, comprising:
constructing a first message unit according to a first target instruction to be transmitted; wherein the first message unit comprises a message header and a message body, the message header comprises a command field of the first target instruction and a structure identifier of the message body, and the message body comprises a data field of the first target instruction;
sending the first message unit to a first memory for transmission to other processors via the first memory; wherein the number of data bits of a message header in the first message unit is the same as the bit width of the first memory.
2. The method of claim 1, wherein constructing the first message unit according to the first target instruction to be transmitted further comprises:
judging whether the data bit number of the message body is an integral multiple of the bit width of the first memory;
if the data bit number of the message body is not an integral multiple of the bit width of the first memory, adding placeholder data in the message body so as to enable the data bit number of the message body to be an integral multiple of the bit width of the first memory.
3. The method of claim 1, wherein constructing the first message unit according to the first target instruction to be transmitted further comprises:
acquiring a first receiver identifier matched with a first target instruction to be transmitted;
constructing a first message unit according to the first target instruction and the first receiver identification; wherein the header of the first message unit includes the first recipient identification.
4. The method of claim 1, further comprising:
in response to the second message unit being acquired through the second memory, the second message unit is analyzed to acquire a message header and a message body of the second message unit; wherein the second message unit is constructed based on a second target instruction;
and executing the second target instruction according to the message header and the message body of the second message unit.
5. The method of claim 4, wherein parsing the second message unit to obtain the message header and the message body of the second message unit in response to obtaining the second message unit through the second memory comprises:
responding to a hardware arbitration mechanism based on a bus, acquiring a second message unit through a second memory, and analyzing the second message unit to acquire a message header and a message body of the second message unit;
judging whether a second receiver identifier in the second message unit is the same as the identifier of the first processor or not;
and if the second receiver identification in the second message unit is the same as the identification of the first processor, continuing to acquire the message body in the second message unit.
6. The method of claim 5, after determining whether the second recipient identifier in the second message unit is the same as the identifier of the first processor, further comprising:
if the second receiver identification in the second message unit is different from the identification of the first processor, judging whether a special memory exists between the first processor and the second receiver according to the second receiver matched with the second receiver identification;
if the first processor and the second receiver are determined to have a special memory, sending the second message unit to the special memory so as to transmit the second message unit to the second receiver through the special memory;
and if the fact that the special memory does not exist between the first processor and the second receiver is determined, the second message unit is sent to the second memory, so that the second message unit is continuously transmitted to the second receiver through the second memory.
7. The method of claim 6, wherein sending the second message unit to the private memory for transmission to the second recipient via the private memory comprises:
and adjusting the data structure of the second message unit according to the bit width of the special memory, so that the data bit number of a message header in the second message unit is the same as the bit width of the special memory, and the data bit number of a message body in the second message unit is an integral multiple of the bit width of the special memory.
8. A data transmission apparatus for use in a first processor, comprising:
the message unit construction module is used for constructing a first message unit according to a first target instruction to be transmitted; wherein the first message unit comprises a message header and a message body, the message header comprises a command field of the first target instruction and a structure identifier of the message body, and the message body comprises a data field of the first target instruction;
the message unit sending module is used for sending the first message unit to a first memory so as to transmit the first message unit to other processors through the first memory; wherein the number of data bits of a message header in the first message unit is the same as the bit width of the first memory.
9. An electronic device, characterized in that the electronic device comprises:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein the content of the first and second substances,
the memory stores a computer program executable by the at least one processor, the computer program being executable by the at least one processor to enable the at least one processor to perform the data transfer method of any one of claims 1-7.
10. A computer-readable storage medium storing computer instructions for causing a processor to perform the data transmission method of any one of claims 1 to 7 when executed.
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