CN116450554A - Interrupt processing method, root complex device and electronic device - Google Patents

Interrupt processing method, root complex device and electronic device Download PDF

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Publication number
CN116450554A
CN116450554A CN202310420992.2A CN202310420992A CN116450554A CN 116450554 A CN116450554 A CN 116450554A CN 202310420992 A CN202310420992 A CN 202310420992A CN 116450554 A CN116450554 A CN 116450554A
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China
Prior art keywords
interrupt
controller
packet
root complex
pcie
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CN202310420992.2A
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Chinese (zh)
Inventor
王少虎
郑德金
张力航
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Shenzhen Lichi Semiconductor Technology Co ltd
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Shenzhen Lichi Semiconductor Technology Co ltd
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Priority to CN202310420992.2A priority Critical patent/CN116450554A/en
Publication of CN116450554A publication Critical patent/CN116450554A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The application provides an interrupt processing method, root complex equipment and electronic equipment; the method comprises the following steps: the first chip of the root complex device receives an interrupt packet corresponding to any interrupt type sent by the second chip of the endpoint device through a Peripheral Component Interconnect (PCIE) bus; analyzing the interrupt packet to obtain an analysis result of the interrupt packet; determining an interrupt request signal matching an interrupt controller in the root complex device based on the parsing result; triggering a first transmission bus in the PCIE bus to communicate with the interrupt controller, and sending the interrupt request signal to the interrupt controller based on the first transmission bus; the first transmission bus is a transmission bus matched with the type of the interrupt controller.

Description

Interrupt processing method, root complex device and electronic device
Technical Field
The present application relates to computer architecture technology, and in particular, to an interrupt processing method, a root complex device, and an electronic device.
Background
The peripheral bus interconnection (Peripheral Component Interconnect Express, PCIE) bus is used as an interconnection bus of the motherboard stage, and connects the processor in the Root Complex (RC) with various integrated external devices, so that the storage space, the computing capacity and the network communication bandwidth of the Root Complex are expanded. The integrated external Device may also be referred to as an endpoint Device (EP).
A system based on PCIE bus connection may be referred to as a PCIE system, where an important performance of the PCIE system is sending and processing interrupt packets; specifically, a peripheral bus interconnection controller in the root complex device receives an interrupt packet sent by the endpoint device, and converts the interrupt packet into an interrupt message and sends the interrupt message to an interrupt controller in the root complex device. Since different interrupt packets may correspond to different interrupt mechanisms or interrupt types, the interrupt controller cannot support all interrupt mechanisms or interrupt types, and if the interrupt packet received by the root complex device is not an interrupt mechanism or interrupt type supported by the interrupt controller in the root complex device, the root complex device cannot process the interrupt packet. Therefore, how to implement fast and concise processing of interrupt packets of different interrupt mechanisms or interrupt types is a constantly pursued goal in the field of interrupt packet transmission technology.
Disclosure of Invention
The embodiment of the application provides an interrupt processing method, root complex equipment and electronic equipment, which can realize the rapid and concise processing of interrupt packets with different interrupt mechanisms.
The technical scheme of the embodiment of the application is realized as follows:
in a first aspect, an embodiment of the present application provides an interrupt processing method, including: the method is applied to a root complex device, the method comprising:
The first chip of the root complex device receives an interrupt packet corresponding to any interrupt type sent by the second chip of the endpoint device through the PCIE bus;
analyzing the interrupt packet to obtain an analysis result of the interrupt packet;
determining an interrupt request signal matching a type of an interrupt controller in the root complex device based on the parsing result;
triggering a first transmission bus in the PCIE bus to communicate with the interrupt controller, and sending the interrupt request signal to the interrupt controller based on the first transmission bus; the first transmission bus is a transmission bus matched with the type of the interrupt controller.
In some embodiments, the determining an interrupt request signal matching an interrupt controller in the root complex device based on the parsing result includes:
determining interrupt types supported by the interrupt controller;
and generating an interrupt request signal matched with the interrupt type supported by the interrupt controller based on the analysis result.
In some embodiments, after the first chip of the root complex device interconnects the PCIE bus through the peripheral component, and receives an interrupt packet corresponding to any interrupt type sent by the second chip of the endpoint device, the method further includes:
Obtaining interrupt state information corresponding to the interrupt packet;
and storing the interrupt state information to the root complex device.
In some embodiments, the obtaining the interrupt status information corresponding to the interrupt packet includes:
and actively reading interrupt state information corresponding to the interrupt packet from the endpoint device by utilizing a read-write remote access engine in the root complex device.
In some embodiments, after the obtaining the interrupt status information corresponding to the interrupt packet, the method further includes:
determining a function of interrupt service to be executed based on the interrupt vector in the interrupt state information;
and calling an interrupt processing program corresponding to the function to execute interrupt service on the function.
In some embodiments, after the saving of the interrupt status information to the root complex device, the method further comprises:
reading the stored interrupt state information;
based on the interrupt status information, an interrupt receipt status register in the endpoint device is cleared.
In some embodiments, after the saving of the interrupt status information to the root complex device, the method further comprises:
Reading the stored interrupt state information;
based on the interrupt status information, enabling the PCIE interrupt of the endpoint device again.
In a second aspect, embodiments of the present application provide a root complex device, the root complex device comprising:
the acquisition module is used for receiving an interrupt packet corresponding to any interrupt type sent by the second chip of the endpoint device through the PCIE bus;
the analysis module is used for analyzing the interrupt packet to obtain an analysis result of the interrupt packet;
a determining module, configured to determine an interrupt request signal that matches an interrupt controller in the root complex device based on the parsing result;
and the sending module is used for sending the interrupt request signal to the interrupt controller by using a PCIE bus.
In some embodiments, the root complex device further comprises:
the processing module is used for acquiring interrupt state information corresponding to the interrupt packet;
and storing the interrupt state information to the root complex device.
In some embodiments, the processing module is configured to actively read, by using a read-write remote access engine in the root complex device, interrupt status information corresponding to the interrupt packet from the endpoint device.
In some embodiments, the processing module is further configured to determine a function of interrupt service to be performed based on an interrupt vector in the interrupt status information;
and calling an interrupt processing program corresponding to the function to execute interrupt service on the function.
In some embodiments, the processing module is further configured to read the saved interrupt status information;
based on the interrupt status information, an interrupt receipt status register in the endpoint device is cleared.
In some embodiments, the processing module is further configured to read the saved interrupt status information;
based on the interrupt status information, enabling the PCIE interrupt of the endpoint device again.
In a third aspect, an embodiment of the present application provides an electronic device, including: at least one processor; and a memory communicatively coupled to the at least one processor; wherein, the liquid crystal display device comprises a liquid crystal display device,
the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the interrupt handling method described above.
In a fourth aspect, embodiments of the present application provide a computer readable storage medium storing executable instructions for implementing a method provided by embodiments of the present application when executed by a processor.
In a fifth aspect, embodiments of the present application provide a computer program product, characterized in that the computer program product comprises a computer program/instruction which, when executed by a processor, implements the method described above.
According to the interrupt processing method provided by the embodiment of the application, the first chip of the root complex device receives an interrupt packet corresponding to any interrupt type sent by the second chip of the endpoint device through the PCIE bus; analyzing the interrupt packet to obtain an analysis result of the interrupt packet; determining the type of an interrupt controller for processing the interrupt packet based on the analysis result; determining an interrupt request signal matched with the type of the interrupt controller based on the analysis result; and triggering a first transmission bus in the PCIE bus to be communicated with the interrupt controller, and sending the interrupt request signal to the interrupt controller based on the first transmission bus. Thus, in the embodiment of the present application, no matter what interrupt type is supported by the interrupt controller, there is no need to configure or change the interface for the interrupt mechanism multiple times, and there is no need to write multiple sets of interrupt processing programs for different interrupt mechanisms, so that the root complex device can process the received interrupt packet, and obtain an interrupt request signal matched with the interrupt type supported by the interrupt controller; in the embodiment of the application, the PCIE bus includes a plurality of different transmission buses, the different transmission buses are used for transmitting interrupt request signals to interrupt controllers of different types, and the transmission buses matched with the types of the interrupt controllers are triggered to communicate, so that the root complex device sends the interrupt request signals to the interrupt controllers through the transmission buses, and the interrupt controllers process interrupt packets based on the interrupt request signals; the method and the device realize quick and concise processing of interrupt packets with different interrupt types.
Drawings
FIG. 1 is a schematic diagram of an alternative processing flow of an interrupt handling method according to an embodiment of the present application;
FIG. 2 is a schematic diagram of another alternative processing flow of the interrupt handling method provided in an embodiment of the present application;
FIG. 3 is a schematic diagram of an alternative process flow of the interrupt handling method according to an embodiment of the present application;
FIG. 4 is a schematic diagram of an alternative process flow of the interrupt handling method according to the embodiment of the present application;
FIG. 5 is a schematic diagram of a processing flow for processing Legacy interrupt packets according to an interrupt processing method provided in an embodiment of the present application;
FIG. 6 is a schematic diagram of a prior art processing flow for processing Legacy interrupt packets;
fig. 7 is a schematic structural diagram of a PCIE controller provided in an embodiment of the present application;
fig. 8 is a schematic diagram of a component structure of a PCIE controller in the prior art;
fig. 9 is a schematic diagram of a PCIE system provided in an embodiment of the present application;
FIG. 10 is a schematic diagram of the composition and structure of a root complex device provided in an embodiment of the present application;
fig. 11 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the present application will be described in further detail with reference to the accompanying drawings, and the described embodiments should not be construed as limiting the present application, and all other embodiments obtained by those skilled in the art without making any inventive effort are within the scope of the present application.
In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is to be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with one another without conflict.
In the following description, the terms "first", "second", and the like are merely used to distinguish between similar objects and do not represent a particular ordering of the objects, it being understood that the "first", "second", or the like may be interchanged with a particular order or precedence, as permitted, to enable embodiments of the present application described herein to be implemented in an order other than that illustrated or described herein.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of the present application only and is not intended to be limiting of the present application.
It should be understood that, in various embodiments of the present application, the size of the sequence number of each implementation process does not mean that the execution sequence of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.
Before further describing embodiments of the present application in detail, the terms and expressions that are referred to in the embodiments of the present application are described, and are suitable for the following explanation.
1) The root complex device, also called RC (Root Complex) end device, the processor in the root complex device performs transmission and processing of interrupt packets with the end device through the interrupt controller and PCIE controller.
2) The device that sends the interrupt packet to the root complex device is called an EP device, which may be a device containing a PCIe interface, such as a graphics card, a network card, or a sound card.
3) PCIE bus, a high-speed serial computer expansion bus, has very wide application in cloud computing, internet of things (Internet of Things, ioT) and mobile devices.
With the explosion of cloud technology and the evolution of virtual technology, more and more Interrupt mechanisms are applied, such as Legacy Interrupt mechanism (Legacy Interrupt), MSI (Message Signaled Interrupt) Interrupt mechanism, and MSI-X Interrupt mechanism. Wherein the Legacy interrupt mechanism supports 4 interrupt vectors, the MSI interrupt mechanism supports 32 interrupt vectors, and the MSI-X interrupt mechanism does not limit the number of interrupt vectors.
And the PCIE controller of the root complex device receives the interrupt packet sent by the other devices, converts the interrupt packet into an interrupt message and sends the interrupt message to the interrupt controller in the root complex device. However, the interrupt controller usually only supports an interrupt message of one interrupt type, or the interrupt controller usually only supports one interrupt mechanism, so that when the external device sends an interrupt packet to the interrupt controller, the interrupt controller can only parse the interrupt packet corresponding to the interrupt mechanism supported by the interrupt controller, and cannot parse the interrupt packets corresponding to all interrupt mechanisms, which also severely limits the types of external devices that the root complex device can adapt to.
For example, if the interrupt controller supports the Legacy interrupt mechanism and the interrupt packet received by the PCIE controller corresponds to the MSI interrupt mechanism or the MSI-X interrupt mechanism, the PCIE controller cannot parse the received interrupt packet and cannot convert the interrupt packet into an interrupt message to be sent to the interrupt controller. If the interrupt controller supports the MSI interrupt mechanism and the interrupt packet received by the PCIE controller corresponds to the Legacy interrupt mechanism or the MSI-X interrupt mechanism, the PCIE controller cannot parse the received interrupt packet and cannot convert the interrupt packet into an interrupt message to be sent to the interrupt controller. If the interrupt controller supports the MSI-X interrupt mechanism and the interrupt packet received by the PCIE controller corresponds to the Legacy interrupt mechanism or the MSI interrupt mechanism, the PCIE controller cannot parse the received interrupt packet and cannot convert the interrupt packet into an interrupt message to be sent to the interrupt controller.
The interfaces of PCIE controllers for different interrupt mechanisms are typically independent, requiring reconfiguration or modification of the interfaces as the different interrupt mechanisms change in the root complex device. At the software level, it is also necessary to register interrupt programs separately for different interrupt mechanisms, and write separate interrupt handling functions separately for each interrupt mechanism. These all result in more complex interrupt handling procedures.
An optional process flow of the interrupt processing method provided in the embodiment of the present application, as shown in fig. 1, at least includes the following steps:
step S101, a first chip of a root complex device receives, through a PCIE bus, an interrupt packet corresponding to any interrupt type sent by a second chip of an endpoint device.
In some embodiments, a first chip in the root complex device receives an interrupt packet sent by the endpoint device through the PCIE bus. The first chip may be a chip in a PCIE controller, where the PCIE controller is a device in the root complex device. The interrupt packet may be any one of a Legacy interrupt packet corresponding to a Legacy interrupt type, an MSI interrupt packet corresponding to an MSI interrupt type, and an MSI-X interrupt packet corresponding to an MSI-X interrupt type.
In the embodiment of the application, the data transmission between the endpoint device and the root complex device is a chip-to-chip transmission.
Step S102, analyzing the interrupt packet to obtain an analysis result of the interrupt packet.
In some embodiments, by parsing the interrupt packet, a message code (message code) in the interrupt packet or an address field (address field) in the interrupt packet can be obtained.
Step S103, determining an interrupt request signal matching the interrupt controller in the root complex device based on the parsing result.
In some embodiments, determining an interrupt request signal matching the interrupt controller based on the parsing result includes: determining interrupt types supported by the interrupt controller; and generating an interrupt request signal matched with the interrupt type supported by the interrupt controller based on the analysis result.
In some embodiments, the interrupt type to which the interrupt packet corresponds can be determined based on the parsing result. If the interrupt packet is a message packet, whether the interrupt packet is a Legacy interrupt packet can be determined according to a message code obtained by parsing the message packet. If the interrupt packet is a message write packet, determining whether an address defined in a System on Chip (SoC) of the root complex device exists in the address field according to the address field obtained by analyzing the message write packet, and determining that the interrupt packet is an MSI interrupt packet or an MSI-X interrupt packet according to address information in the address field.
Step S104, a first transmission bus in the PCIE bus is triggered to communicate with the interrupt controller, and the interrupt request signal is sent to the interrupt controller based on the first transmission bus.
In the embodiment of the application, PCIE buses in the root complex device may be adapted to different types of interrupt controllers. Specifically, the PCIE bus may include three types of transmission buses, such as a Legacy inter-mounted type transmission bus, an MSI type transmission bus, and an MSI-X type transmission bus. If the Interrupt type supported by the Interrupt controller is the Legacy Interrupt type, triggering a transmission bus of the Legacy Interrupt type in the PCIE bus to communicate with the Interrupt controller; if the interrupt type supported by the interrupt controller is MSI type, triggering the transmission bus of MSI type in PCIE bus to communicate with the interrupt controller; if the interrupt type supported by the interrupt controller is MSI-X type, the transmission bus of MSI-X type in PCIE bus is triggered to communicate with the interrupt controller.
In specific implementation, multiple interface types can be configured for the PCIE controller through software, for example, a Legacy inter-mount type interface, an MSI type interface, and an MSI-X type interface are configured for the PCIE controller. If the Legacy Interrupt type transmission bus in the PCIE bus is triggered to communicate with the Interrupt controller, transmitting data with the Interrupt controller through a Legacy Interrupt type interface in the PCIE controller; if the MSI type transmission bus in the PCIE bus is triggered to be communicated with the interrupt controller, transmitting data with the interrupt controller through the MSI type interface in the PCIE controller; if the MSI-X type transmission bus in the PCIE bus is triggered to be communicated with the interrupt controller, data is transmitted through the MSI-X type interface in the PCIE controller and the interrupt controller.
Steps S103 to S104 are described below for a scenario in which the interrupt controller supports different interrupt types, respectively.
1. The interrupt type supported by the interrupt controller is MSI-X interrupt type, and correspondingly, the system Bus (SoC Bus) is MSI-X transmission Bus (MSI-X transmission Bus).
In some embodiments, if the interrupt packet received by the PCIE controller is a Legacy interrupt packet, the PCIE controller converts a message code in the Legacy interrupt packet through a preset mapping table, and sends the converted data to the interrupt controller through the SoC Bus. As an example, the message code in the Legacy interrupt packet may be converted through a preset lookup table, the 4-bit message code is converted into 32-bit information, and the converted 32-bit information is sent to the SoC bus. Soc_bus.wdata (write data) is fixed to 0. In this scenario, the interrupt request signal sent to the interrupt controller includes at least the converted 32-bit information.
In other embodiments, if the interrupt packet received by the PCIE controller is an MSI interrupt packet, the PCIE controller sends the msi_tlp.address to the soc_bus.write_transaction.address (a specific address of the MSI). MSI_TLP.Data is sent to SoC_Bus_Write_Transaction.WDATA (write data). In this scenario, the interrupt request signal sent to the interrupt controller includes at least msi_tlp.address and msi_tlp.data.
In still other embodiments, if the interrupt packet received by the PCIE controller is an MSI-X interrupt packet, the PCIE controller directly sends the MSI-x_tlp.address to the soc_bus.address, and sends the MSI-x_tlp.data to the soc_bus.wdata (write data). In this scenario, the interrupt request signal sent to the interrupt controller includes at least MSI-X_TLP.Address and MSI-X_TLP.Data.
2. The interrupt types supported by the interrupt controller are MSI interrupt types, which, accordingly, the system Bus (SoC Bus) is an MSI transmission Bus (MSI transmit Bus). The configuration of the MSI transmit Bus may include:
1) msi_int_rcvd is used to provide an interrupt valid flag.
2) msi_int_reqid [15:0] for providing an interrupt source ID; the interrupt source ID may be a b.d.f-bus.device.function number defined by PCIE protocol.
3) msi_int_data [15:0] for providing an interrupt vector (vector).
In some embodiments, if the interrupt packet received by the PCIE controller is a Legacy interrupt packet, the PCIE controller converts a message code in the Legacy interrupt packet through a preset mapping table, and sends the converted data to the interrupt controller through the SoC Bus. As an example, the message code in the Legacy interrupt packet may be converted through a preset lookup table, 4-bit message code may be converted into 32-bit information, and the converted 32-bit information may be sent to msi_int_data (Legacy interrupt map data); msi_int_reqid is fixed to 0. In this scenario, the interrupt request signal sent to the interrupt controller includes at least the converted 32-bit information.
In other embodiments, if the interrupt packet received by the PCIE controller is an MSI-X interrupt packet, the PCIE controller sends an msi_tlp.reqid to the msi_int_reqid; and converting MSI-XTLP.address/data according to the table, and transmitting the data converted by the table to msi_int_data. In this scenario, the interrupt request signal sent to the interrupt controller includes at least the data converted by the wakeup table and msi_tlp.reqid.
In still other embodiments, if the interrupt packet received by the PCIE controller is an MSI interrupt packet, the PCIE controller directly sends the msi_tlp.reqid to msi_int_reqid and sends the msi_tlp.data to msi_int_data.
3. The interrupt type supported by the interrupt controller is Legacy interrupt type, and correspondingly, the system Bus (SoC Bus) is an MSI transmission Bus (MSI transmission Bus).
In some embodiments, if the interrupt packet received by the PCIE controller is a Legacy interrupt packet, the PCIE controller stores legacy_tlp/Type/message_code information to a PCIE Interrupt Status module in the root complex device, and sets an output value of the pcie_interrupt to 1. If all interrupts are cleared (write-one-clear), the value of pcie_interrupt is set to 0.
In other embodiments, if the interrupt packet received by the PCIE controller is an MSI interrupt packet, the PCIE controller stores msi_tlp/fmt/Type/REQID/DATA information to a PCIE Interrupt Status module in the root complex device, and sets an output value of the pcie_interrupt to 1. If all interrupts are cleared (write-one-clear), the value of pcie_interrupt is set to 0.
In still other embodiments, if the interrupt packet received by the PCIE controller is an MSI-X interrupt packet, the PCIE controller stores msi_tlp/Type/REQID/ADDRESS/DATA information to a PCIE Interrupt Status module in the root complex device and sets an output value of pcie_interrupt to 1. If all interrupts are cleared (write-one-clear), the value of pcie_interrupt is set to 0.
To simplify the design of an interrupt controller, it is common for an interrupt controller to only support one or two particular interrupt types, and therefore, the interrupt controller can only handle interrupt packets of the interrupt type supported by the interrupt controller. In the embodiment of the application, whether the received interrupt packet is of the interrupt type supported by the interrupt controller or not, the interrupt controller can process the interrupt packet. Specifically, the received interrupt packet is analyzed, and an interrupt request signal matched with the interrupt controller is determined according to an analysis result obtained by analysis, so that the interrupt request signal received by the interrupt controller is matched with the interrupt type supported by the interrupt controller, the interrupt controller can directly process the interrupt request signal, the quick and concise processing of the interrupt packet is realized, and the root complex device can adapt to various types of external devices. According to the embodiment of the application, aiming at interrupt packets of different types, interfaces do not need to be reconfigured or changed, interrupt programs do not need to be registered for the interrupt packets of different interrupt types respectively, independent interrupt processing shout does not need to be written for each interrupt type respectively, and interrupt processing flow is simplified.
An alternative process flow of the interrupt processing method provided in the embodiment of the present application, as shown in fig. 2, at least includes the following steps:
in step S201, the first chip of the root complex device receives, through the PCIE bus, an interrupt packet corresponding to any interrupt type sent by the second chip of the endpoint device.
In some embodiments, the process of receiving the interrupt packet by the root complex device and the description of the interrupt packet are the same as step S101, and are not described here again.
Step S202, obtaining interrupt state information corresponding to the interrupt packet, and storing the interrupt state information to the root complex device.
In some embodiments, the specific implementation procedure for obtaining the interrupt status information of the interrupt packet may be: and actively reading interrupt state information corresponding to the interrupt packet from the endpoint device by utilizing a read-write remote access engine in the root complex device.
In some embodiments, interrupt state information may be saved to a state register within the root complex device.
In the embodiment of the application, the read-write remote access engine in the root complex device actively reads the interrupt state information of the interrupt packet from the device and stores the interrupt state information to the root complex device, so that the interrupt state information in the device is prevented from being remotely read when the root complex device performs interrupt processing, the interrupt state information can be directly obtained locally from the root complex device, and the interrupt processing efficiency is improved.
And step S203, analyzing the interrupt packet to obtain an analysis result of the interrupt packet.
Step S204, determining an interrupt request signal matching the interrupt controller in the root complex device based on the parsing result.
In step S205, a first transmission bus in the PCIE bus is triggered to communicate with the interrupt controller, and the interrupt request signal is sent to the interrupt controller based on the first transmission bus.
In the embodiment of the present application, the processing procedure from step S203 to step S205 is the same as that from step S102 to step S104, and will not be repeated here.
As shown in FIG. 3, another optional processing flow of the interrupt processing method provided in the embodiment of the present application at least includes the following steps:
in step S301, the first chip of the root complex device receives, via the PCIE bus, an interrupt packet corresponding to any interrupt type sent by the second chip of the endpoint device.
In some embodiments, the process of obtaining the interrupt packet and the description of the interrupt packet are the same as step S101, and are not described here again.
Step S302, obtaining interrupt state information corresponding to the interrupt packet, and storing the interrupt state information to the root complex device.
In some embodiments, the specific implementation procedure for obtaining the interrupt status information of the interrupt packet may be: and actively reading interrupt state information corresponding to the interrupt packet from the endpoint device by utilizing a read-write remote access engine in the root complex device.
In the embodiment of the application, the read-write remote access engine in the root complex device actively reads the interrupt state information of the interrupt packet from the device and stores the interrupt state information to the root complex device, so that the interrupt state information in the device is prevented from being remotely read when the root complex device performs interrupt processing, the interrupt state information can be directly obtained locally from the root complex device, and the interrupt processing efficiency is improved.
Step S303, analyzing the interrupt packet to obtain an analysis result of the interrupt packet.
Step S304, determining an interrupt request signal matching the interrupt controller in the root complex device based on the parsing result.
In step S305, a first transmission bus in the PCIE bus is triggered to communicate with the interrupt controller, and the interrupt request signal is sent to the interrupt controller based on the first transmission bus.
In the embodiment of the present application, the processing procedure from step S303 to step S305 is the same as that from step S102 to step S104, and will not be repeated here.
Step S306, determining the function of interrupt service to be executed based on the interrupt vector in the interrupt status information; and calling an interrupt processing program corresponding to the function to execute interrupt service on the function.
In some embodiments, each interrupt vector corresponds to M bits of interrupt information from which a function of interrupt service to be performed can be determined. The interrupt controller calls the interrupt processing program corresponding to the function, and executes interrupt service by using the interrupt processing program corresponding to the interrupt function. The interrupt handler corresponding to the function may be a USB function interrupt handler.
As shown in FIG. 4, another alternative process flow of the interrupt processing method provided in the embodiment of the present application at least includes the following steps:
in step S401, the first chip of the root complex device receives, through the PCIE bus, an interrupt packet corresponding to any interrupt type sent by the second chip of the endpoint device.
Step S402, obtaining interrupt state information corresponding to the interrupt packet, and storing the interrupt state information to the root complex device.
In some embodiments, the specific implementation procedure for obtaining the interrupt status information of the interrupt packet may be: and actively reading interrupt state information corresponding to the interrupt packet from the endpoint device by utilizing a read-write remote access engine in the root complex device.
In some embodiments, the interrupt status information may be an interrupt vector Number (Function Number).
In the embodiment of the application, the read-write remote access engine in the root complex device actively reads the interrupt state information of the interrupt packet from the device and stores the interrupt state information to the root complex device, so that the interrupt state information in the device is prevented from being remotely read when the root complex device performs interrupt processing, the interrupt state information can be directly obtained locally from the root complex device, and the interrupt processing efficiency is improved.
Step S403, analyzing the interrupt packet to obtain an analysis result of the interrupt packet.
In step S404, and determining an interrupt request signal matched with an interrupt controller in the root complex device based on the analysis result.
In step S405, a first transmission bus in the PCIE bus is triggered to communicate with the interrupt controller, and the interrupt request signal is sent to the interrupt controller based on the first transmission bus.
Step S406, determining the function of interrupt service to be executed based on the interrupt vector in the interrupt status information; and calling an interrupt processing program corresponding to the function to execute interrupt service on the function.
In the embodiment of the present application, the processing procedure from step S401 to step S406 is the same as that from step S301 to step S306, and will not be repeated here.
Step S407, reading the saved interrupt status information, and clearing an interrupt receiving status register in the endpoint device based on the interrupt status information.
In some embodiments, the PCIE controller reads interrupt status information from the root complex device locally, and clears the interrupt receipt status register local to the root complex device according to the interrupt status information; and synchronizing the interrupt receipt status register in the endpoint device by the read-write remote access engine such that the information of the interrupt receipt status register in the device is consistent with the information of the interrupt receipt status register in the root complex device. Clearing the interrupt receipt status register refers to: the corresponding bit in the interrupt receive status register is written from 1 to 0. The corresponding bit in the interrupt receive status register is 0, indicating that the root complex device has processed an interrupt packet. Specifically, the interrupt status information may be read locally from the root complex device using a read-write remote access engine in the PCIE controller.
Step S408, based on the interrupt status information, enabling PCIE interrupt of the endpoint device again.
In some embodiments, if PCIE interrupts are enabled, after receiving the interrupt packet, the PCIE controller sends the interrupt packet to the interrupt controller of the root complex device, and then the interrupt controller sends the interrupt packet to the root complex device system. If the PCIE interrupt is not enabled, the PCIE controller does not send the interrupt packet to the interrupt controller of the root complex device after receiving the interrupt packet.
In some embodiments, the root complex device first enables PCIE interrupts of the root complex device itself, and then synchronizes PCIE interrupts in the endpoint device through the read-write remote access engine.
In some embodiments, step S407 and step S408 may be performed either or both.
It should be noted that, the read-write remote access engine and the interrupt receiving status register in the embodiments described above may be located in the PCIE controller.
The following describes an interrupt processing method provided in the embodiment of the present application, taking a Legacy interrupt packet as an example.
The processing flow for processing the Legacy interrupt packet based on the interrupt processing method provided in the embodiment of the present application, as shown in fig. 5, at least includes the following steps:
in step S501, the EP device sends a Legacy interrupt packet to the PCIE controller at the RC end.
In some embodiments, the Legacy interrupt packet may include INTX_ASSERT and INTX_DEASSERT; wherein INTX stands for INTA, INTB, INTC and INTD for four different Legacy interrupts, ASSERT stands for Legacy interrupt to become active, DEASSERT stands for Legacy interrupt to become inactive.
In step S502, the PCIE controller parses the Legacy interrupt packet and determines an interrupt request signal that matches the interrupt controller.
In some embodiments, the specific implementation procedure of determining the interrupt request signal matched with the interrupt controller is the same as the detailed description of step S103 to step S104, and will not be repeated here.
In this embodiment of the present application, no matter what interrupt type is supported by the interrupt controller, the PCIE controller can determine a corresponding interrupt request signal according to the received interrupt packet.
In step S503, an interrupt request signal is sent to the interrupt controller.
In some embodiments, the PCIE controller sends the interrupt request signal to the interrupt transmission unit, where the interrupt transmission unit includes an interface corresponding to each interrupt type, and is capable of sending the request signal corresponding to any interrupt type to the interrupt transmission unit, and the interrupt transmission unit sends the interrupt request signal to the interrupt controller.
Step S504, obtaining interrupt state information corresponding to the Legacy interrupt packet, and storing the interrupt state information to the root complex device.
In some embodiments, the processing procedure of obtaining the interrupt status information corresponding to the Legacy interrupt packet and storing the interrupt status information to the root complex device is the same as the processing procedure in step S402, and will not be described herein.
Wherein the interrupt status information may be an interrupt vector number.
In step S505, the RC-side device invokes an interrupt service routine.
In step S506, the RC-side device clears the PCIE interrupt of the EP-side device through the local access.
In step S507, the RC terminal device obtains the current interrupt vector number by locally accessing and reading the interrupt receiving status register of the EP terminal device.
In some embodiments, the current interrupt vector number is used to determine which interrupt source is currently being INTA-INTD.
In step S508, the RC-terminal device determines the function through local access, and invokes a corresponding interrupt handler.
In some embodiments, the RC-side device reads the interrupt sending register state of the EP-side device corresponding to the current interrupt source through local access, so as to determine the function of sending the interrupt packet. The interrupt handler may be a USB Function interrupt handler.
In some embodiments, the mapping between Interrupt sources and all functions may be recorded by traversing the inter Pin field in the function configuration space register.
In step S509, the RC terminal device clears the interrupt receiving status register of the EP terminal device by local access.
In step S510, the RC terminal device enables the PCIE interrupt of the EP terminal device again through the local access.
Fig. 5 is a processing flow of processing a Legacy interrupt packet according to the interrupt processing method provided in the embodiment of the present application, where the processing flow of processing a Legacy interrupt packet in the prior art, as shown in fig. 6, may at least include:
in step S601, the EP end device sends a Legacy interrupt packet to the PCIE controller of the RC end device.
In some embodiments, the Legacy interrupt packet may include INTX_ASSERT and INTX_DEASSERT; wherein INTX stands for INTA, INTB, INTC and INTD for four different Legacy interrupts, ASSERT stands for Legacy interrupt to become active, DEASSERT stands for Legacy interrupt to become inactive.
If the interrupt type supported by the interrupt controller in the EP terminal device is a Legacy interrupt type, executing step S602; if the interrupt controller in the EP end device does not support the Legacy interrupt type, ending the interrupt processing flow.
In step S602, the RC-terminal device invokes an interrupt service routine.
In step S603, the RC terminal device clears the PCIE interrupt enable of the EP terminal device through remote access.
In step S604, the RC-terminal device determines the function through remote access, and invokes a corresponding interrupt handler.
In step S605, the RC terminal device clears the interrupt receiving status register of the EP terminal device by remote access.
In step S606, the RC terminal device enables the PCIE interrupt of the EP terminal device again through the remote access.
Based on fig. 5 and fig. 6, it can be determined that, in the interrupt processing method provided by the embodiment of the present application, no matter what interrupt type is supported by the interrupt controller, no multiple configuration or modification of interfaces for interrupt mechanisms is required, and no multiple sets of interrupt processing programs for different interrupt mechanisms are required to be written, so that the RC terminal device can process the interrupt packet from the EP terminal device; the method and the device realize quick and concise processing of interrupt packets with different interrupt types. In the embodiment of the application, the interrupt receiving status register of the EP terminal equipment is cleared, and the PCIE interrupt of the EP terminal equipment is enabled again through local access, so that the PCIE interrupt processing flow is simplified.
The interrupt processing method provided by the embodiment of the application can be realized by a PCIE controller in the root complex device. The structural schematic diagram of the PCIE controller provided in the embodiment of the present application, as shown in fig. 7, includes: a PCIE local controller (PCIE native controller) and a PCIE interrupt shadow module (PCIE shadow module); the PCIE interrupt shadow module includes: a read-write remote access engine (PCIE Remote access engine), an interrupt decode unit (PCIE Interrupt decode), a status register (PCIE Interrupt state), and an interrupt transfer unit (PCIE Interrupt transmitter). The status registers may include an interrupt status receiving register and/or an interrupt status transmitting register, among others.
In this embodiment, a specific workflow of the PCIE controller includes: the PCIE local controller receives any type of interrupt packet such as Legacy interrupt type, MSI interrupt type, and MSI-X interrupt type. And the PCIE local controller sends the received interrupt packet to an interrupt decoding unit, the interrupt decoding unit analyzes the interrupt packet, and determines an interrupt request signal matched with the interrupt controller of the root complex device according to an analysis result. The read-write remote access engine reads interrupt state information corresponding to the interrupt packet from the EP terminal equipment in a remote mode and sends the interrupt state information to the state register; the read-write remote access engine can also synchronize interrupt status information of a status register in the RC-side device to a status register in the EP-side device. The state register stores interrupt state information and sends the interrupt state information and an interrupt request signal to the interrupt transmission unit; the interrupt transmission unit transmits an interrupt request signal to the interrupt controller, and the interrupt controller interacts with the processor of the root complex device according to the interrupt request signal to execute an interrupt flow. The interrupt transmission unit supports transmission buses and transmission interfaces corresponding to different interrupt types. The read-write remote access engine can clear the interrupt receiving status register of the EP end device by means of local access and enable the PCIE interrupt of the EP end device again.
The above description is based on fig. 7, which illustrates the structure of the PCIE controller and a specific workflow of the PCIE controller according to the embodiment of the present application. The following describes the structure of a PCIE controller in the prior art and a specific workflow of the PCIE controller. The prior art PCIE controller includes a PCIE local controller (PCIE native controller) and an interrupt decoding unit (PCIE Interrupt decode), as shown in fig. 8. The PCIE local controller receives any type of interrupt packet such as Legacy interrupt type, MSI interrupt type, and MSI-X interrupt type. The PCIE local controller sends the received interrupt packet to an interrupt decoding unit, the interrupt decoding unit analyzes the interrupt packet and judges whether the interrupt type of the received interrupt packet is consistent with the interrupt type supported by the interrupt controller; if the interrupt type of the received interrupt packet is consistent with the interrupt type supported by the interrupt controller, sending an interrupt request signal corresponding to the interrupt packet to the interrupt controller. The interrupt controller interacts with the processor of the root complex device according to the interrupt request signal to execute an interrupt flow. If the interrupt type of the received interrupt packet is inconsistent with the interrupt type supported by the interrupt controller, ending the interrupt flow, and not processing the interrupt packet.
Based on fig. 7 and fig. 8, it can be determined that, no matter what interrupt type is supported by the PCIE controller, the PCIE controller provided by the embodiment of the present application can process the received interrupt packet without configuring or changing the interface for the interrupt mechanism multiple times, and without writing multiple sets of interrupt handlers for different interrupt mechanisms. According to the PCIE controller provided by the embodiment of the invention, the read-write remote access engine can clear the interrupt receiving state register of the EP end device and enable the PCIE interrupt of the EP end device again in a local access mode, so that the PCIE interrupt processing flow is simplified.
The schematic diagram of a PCIE system in which an RC end device of the PCIE controller shown in fig. 7 interacts with an EP end device, as shown in fig. 9, where the RC end device and the EP end device perform data transmission based on PCIE switches, and the RC end device includes a PCIE controller, an interrupt controller, a processor, a PCIE port, and a PCIE transmission bus; the number of the EP end devices transmitted by the RC end device can be multiple, and different EP end devices can send interrupt packets of different types; EP end device 1 sends Legacy type interrupt packets, EP end device 2 sends MSI type interrupt packets, and EP end device 3 sends MSI-X type interrupt packets as in fig. 9. The interrupt packet sent by the EP terminal equipment is sent to the PCIE controller through the PCIE port; the PCIE controller analyzes the interrupt packet, and determines an interrupt request signal matched with the interrupt type supported by the interrupt controller according to the analysis result; and sending the interrupt request signal to an interrupt controller through a PCIE transmission bus. The PCIE transmission buses comprise a Legacy type transmission bus, an MSI type transmission bus and an MSI-X type transmission bus; and the PCIE controller triggers the corresponding type of transmission bus communication according to the type of the interrupt controller, and transmits the interrupt packet to the interrupt controller. For example, if the interrupt controller supports the Legacy type interrupt packet, the PCIE controller triggers the Legacy type transport bus to communicate, and sends the interrupt packet to the interrupt controller through the Legacy type transport bus, where the interrupt controller processes the interrupt packet.
The embodiment of the application also provides a root complex device, which is a schematic diagram of a composition structure of the root complex device, as shown in fig. 10, and includes:
the obtaining module 901 is configured to receive, through a PCIE bus, an interrupt packet corresponding to any interrupt type sent by the second chip of the endpoint device;
the parsing module 902 is configured to parse the interrupt packet to obtain a parsing result of the interrupt packet;
a determining module 903, configured to determine an interrupt request signal that matches an interrupt controller in the root complex device based on the parsing result;
a sending module 904, configured to send the interrupt request signal to the interrupt controller by using a peripheral component interconnect PCIE bus.
In some embodiments, the acquisition module 901 may be located within a first chip in the root complex device.
In some embodiments, the determining module 903 is configured to determine an interrupt type supported by the interrupt controller; and generating an interrupt request signal matched with the interrupt type supported by the interrupt controller based on the analysis result.
In some embodiments, the root complex device further comprises: a processing module (not shown in fig. 10) for acquiring interrupt status information corresponding to the interrupt packet; and storing the interrupt state information to the root complex device.
In some embodiments, the processing module is further configured to determine a function of interrupt service to be performed based on an interrupt vector in the interrupt status information; and calling an interrupt processing program corresponding to the function to execute interrupt service on the function.
In some embodiments, the processing module is further configured to read the saved interrupt status information;
based on the interrupt status information, an interrupt receipt status register in the endpoint device is cleared.
In some embodiments, the processing module is further configured to read the saved interrupt status information; based on the interrupt status information, PCIE interrupts of the endpoint device are enabled again.
It should be noted that the functions of the acquiring module 901, the parsing module 902, the determining module 903, and the processing module may be implemented by a processor. The functions of the transmitting module 904 may be implemented by a signal transmitter or a signal transceiver.
The embodiment of the application also provides electronic equipment, which comprises: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the interrupt handling method described above.
Fig. 11 illustrates a schematic block diagram of an example electronic device 800 that can be used to implement embodiments of the present disclosure. In some alternative embodiments, electronic device 800 may be a terminal device or a server. In some alternative embodiments, the electronic device 800 may implement the interrupt processing method provided in the embodiments of the present application by running a computer program, for example, the computer program may be a native program or a software module in an operating system; a Native (APP) Application, i.e. a program that needs to be installed in an operating system to run; the method can also be an applet, namely a program which can be run only by being downloaded into a browser environment; but also an applet that can be embedded in any APP. In general, the computer programs described above may be any form of application, module or plug-in.
In practical applications, the electronic device 800 may be an independent physical server, a server cluster or a distributed system formed by a plurality of physical servers, or a Cloud server that provides Cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, CDNs, and basic Cloud computing services such as big data and artificial intelligence platforms, where Cloud Technology (Cloud Technology) refers to a hosting Technology that unifies serial resources such as hardware, software, and networks in a wide area network or a local area network to implement computing, storing, processing and sharing of data. The electronic device 800 may be, but is not limited to, a smart phone, tablet, notebook, desktop, smart box, smart television, smart watch, etc.
Electronic devices are intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The electronic device may also represent various forms of mobile devices, such as personal digital assistants, cellular telephones, smartphones, wearable devices, vehicle terminals, and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the disclosure described and/or claimed herein.
As shown in fig. 11, the electronic device 800 includes a computing unit 801 that can perform various appropriate actions and processes according to a computer program stored in a Read Only Memory (ROM) 802 or a computer program loaded from a storage unit 808 into a Random Access Memory (RAM) 803. In the RAM 803, various programs and data required for the operation of the electronic device 800 can also be stored. The computing unit 801, the ROM 802, and the RAM 803 are connected to each other by a bus 804. An input/output (I/O) interface 805 is also connected to the bus 804.
Various components in electronic device 800 are connected to I/O interface 805, including: an input unit 806 such as a keyboard, mouse, etc.; an output unit 807 such as various types of displays, speakers, and the like; a storage unit 808, such as a magnetic disk, optical disk, etc.; and a communication unit 809, such as a network card, modem, wireless communication transceiver, or the like. The communication unit 809 allows the electronic device 800 to exchange information/data with other devices through a computer network such as the internet and/or various telecommunication networks.
The computing unit 801 may be a variety of general and/or special purpose processing components having processing and computing capabilities. Some examples of computing unit 801 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various specialized Artificial Intelligence (AI) computing chips, various computing units running machine learning model algorithms, a Digital Signal Processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 801 performs the respective methods and processes described above, such as an interrupt processing method. For example, in some alternative embodiments, the interrupt handling method may be implemented as a computer software program tangibly embodied on a machine-readable medium, such as the storage unit 808. In some alternative embodiments, part or all of the computer program may be loaded and/or installed onto the electronic device 800 via the ROM 802 and/or the communication unit 809. When a computer program is loaded into RAM 803 and executed by computing unit 801, one or more steps of the interrupt processing method described above may be performed. Alternatively, in other embodiments, the computing unit 801 may be configured as an interrupt handling method by any other suitable means (e.g., by means of firmware).
Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuit systems, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), systems On Chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs, the one or more computer programs may be executed and/or interpreted on a programmable system including at least one programmable processor, which may be a special purpose or general-purpose programmable processor, that may receive data and instructions from, and transmit data and instructions to, a storage system, at least one input device, and at least one output device.
Program code for carrying out the interrupt processing methods of the present disclosure can be written in any combination of one or more programming languages. These program code may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus such that the program code, when executed by the processor or controller, causes the functions/operations specified in the flowchart and/or block diagram to be implemented. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.
In the context of this disclosure, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. The machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and pointing device (e.g., a mouse or trackball) by which a user can provide input to the computer. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic input, speech input, or tactile input.
The systems and techniques described here can be implemented in a computing system that includes a background component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such background, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), and the internet.
The computer system may include a client and a server. The client and server are typically remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server may be a cloud server, a server of a distributed system, or a server incorporating a blockchain.
It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps recited in the present disclosure may be performed in parallel or sequentially or in a different order, provided that the desired results of the technical solutions of the present disclosure are achieved, and are not limited herein.
The embodiment of the application also provides a computer readable storage medium, which stores executable instructions for implementing the interrupt processing method when being executed by a processor.
In some embodiments, the executable instructions may be in the form of programs, software modules, scripts, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and they may be deployed in any form, including as stand-alone programs or as modules, components, subroutines, or other units suitable for use in a computing environment.
As an example, executable instructions may be deployed to be executed on one computing device or on multiple computing devices located at one site or, alternatively, distributed across multiple sites and interconnected by a communication network.
Embodiments of the present application provide a computer program product comprising computer programs/instructions which, when executed by a processor, implement the interrupt handling methods described herein.
The foregoing is merely exemplary embodiments of the present application and is not intended to limit the scope of the present application. Any modifications, equivalent substitutions, improvements, etc. that are within the spirit and scope of the present application are intended to be included within the scope of the present application.

Claims (11)

1. An interrupt handling method, the method being applied to a root complex device, the method comprising:
the first chip of the root complex device is connected with the PCIE bus through the peripheral component, and receives an interrupt packet corresponding to any interrupt type sent by the second chip of the endpoint device;
analyzing the interrupt packet to obtain an analysis result of the interrupt packet;
determining an interrupt request signal matching an interrupt controller in the root complex device based on the parsing result;
triggering a first transmission bus in the PCIE bus to communicate with the interrupt controller, and sending the interrupt request signal to the interrupt controller based on the first transmission bus; the first transmission bus is a transmission bus matched with the type of the interrupt controller.
2. The method of claim 1, wherein the determining an interrupt request signal that matches an interrupt controller in the root complex device based on the parsing result comprises:
determining interrupt types supported by the interrupt controller;
and generating an interrupt request signal matched with the interrupt type supported by the interrupt controller based on the analysis result.
3. The method of claim 1, wherein after the first chip of the root complex device receives an interrupt packet corresponding to any interrupt type sent by the second chip of the endpoint device through the PCIE bus interconnected by the peripheral component, the method further comprises:
obtaining interrupt state information corresponding to the interrupt packet;
and storing the interrupt state information to the root complex device.
4. The method of claim 3, wherein the obtaining the interrupt status information corresponding to the interrupt packet comprises:
and actively reading interrupt state information corresponding to the interrupt packet from the endpoint device by utilizing a read-write remote access engine in the root complex device.
5. The method according to claim 3, wherein after the obtaining the interrupt status information corresponding to the interrupt packet, the method further comprises:
Determining a function of interrupt service to be executed based on the interrupt vector in the interrupt state information;
and calling an interrupt processing program corresponding to the function to execute interrupt service on the function.
6. A method according to claim 3, wherein after said saving said interrupt status information to said root complex device, said method further comprises:
reading the stored interrupt state information;
based on the interrupt status information, an interrupt receipt status register in the endpoint device is cleared.
7. A method according to claim 3, wherein after said saving said interrupt status information to said root complex device, said method further comprises:
reading the stored interrupt state information;
based on the interrupt status information, enabling the PCIE interrupt of the endpoint device again.
8. A root complex device, the root complex device comprising:
the acquisition module is used for receiving an interrupt packet corresponding to any interrupt type sent by the second chip of the endpoint device through the peripheral component interconnect PCIE bus;
the analysis module is used for analyzing the interrupt packet to obtain an analysis result of the interrupt packet;
A determining module, configured to determine an interrupt request signal that matches an interrupt controller in the root complex device based on the parsing result;
and the sending module is used for sending the interrupt request signal to the interrupt controller by utilizing a Peripheral Component Interconnect (PCIE) bus.
9. An electronic device, the electronic device comprising:
at least one processor; and a memory communicatively coupled to the at least one processor; wherein, the liquid crystal display device comprises a liquid crystal display device,
the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the interrupt processing method of any one of claims 1 to 7.
10. A computer readable storage medium storing executable instructions for implementing the method of any one of claims 1 to 7 when executed by a processor.
11. A computer program product, characterized in that it comprises a computer program/instruction which, when executed by a processor, implements the method of any of claims 1 to 7.
CN202310420992.2A 2023-04-12 2023-04-12 Interrupt processing method, root complex device and electronic device Pending CN116450554A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117331720A (en) * 2023-11-08 2024-01-02 瀚博半导体(上海)有限公司 Method, register set, chip and computer device for communication between multiple cores

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117331720A (en) * 2023-11-08 2024-01-02 瀚博半导体(上海)有限公司 Method, register set, chip and computer device for communication between multiple cores
CN117331720B (en) * 2023-11-08 2024-02-23 瀚博半导体(上海)有限公司 Method, register set, chip and computer device for communication between multiple cores

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