CN115098165B - Data processing method, device, chip, equipment and medium - Google Patents
Data processing method, device, chip, equipment and medium Download PDFInfo
- Publication number
- CN115098165B CN115098165B CN202210665616.5A CN202210665616A CN115098165B CN 115098165 B CN115098165 B CN 115098165B CN 202210665616 A CN202210665616 A CN 202210665616A CN 115098165 B CN115098165 B CN 115098165B
- Authority
- CN
- China
- Prior art keywords
- storage space
- write
- instruction
- update vector
- storage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000003672 processing method Methods 0.000 title claims abstract description 20
- 239000013598 vector Substances 0.000 claims abstract description 84
- 230000000903 blocking effect Effects 0.000 claims abstract description 34
- 238000012545 processing Methods 0.000 claims abstract description 28
- 230000004044 response Effects 0.000 claims abstract description 14
- 238000000034 method Methods 0.000 claims description 34
- 238000004590 computer program Methods 0.000 description 15
- 238000004891 communication Methods 0.000 description 13
- 238000010586 diagram Methods 0.000 description 11
- 230000006870 function Effects 0.000 description 6
- 230000008569 process Effects 0.000 description 4
- 238000013459 approach Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 238000013473 artificial intelligence Methods 0.000 description 2
- 230000001413 cellular effect Effects 0.000 description 2
- 230000003993 interaction Effects 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 230000010267 cellular communication Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000010801 machine learning Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052754 neon Inorganic materials 0.000 description 1
- GKAOGPIIYCISHV-UHFFFAOYSA-N neon atom Chemical compound [Ne] GKAOGPIIYCISHV-UHFFFAOYSA-N 0.000 description 1
- 239000013307 optical fiber Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000001953 sensory effect Effects 0.000 description 1
- 239000004984 smart glass Substances 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F16/00—Information retrieval; Database structures therefor; File system structures therefor
- G06F16/20—Information retrieval; Database structures therefor; File system structures therefor of structured data, e.g. relational data
- G06F16/23—Updating
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
- G06F17/16—Matrix or vector computation, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30018—Bit or string instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30094—Condition code generation, e.g. Carry, Zero flag
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The disclosure provides a data processing method, a data processing device, a chip, a device and a medium, relates to the technical field of computers, and particularly relates to the field of chips. The implementation scheme is as follows: determining an update vector for updating the storage space, wherein each element in the update vector has corresponding validity information; and performing a write control operation for any one element in the update vector, wherein the write control operation comprises: generating a blocking instruction for the element in response to the validity information of the element indicating that the element is invalid; and blocking the updating of the stored data in the storage space by the element using the blocking instruction.
Description
Technical Field
The present disclosure relates to the field of computer technology, and in particular, to the field of chips, and more particularly, to a method, apparatus, chip, electronic device, computer readable storage medium, and computer program product for data processing.
Background
A vector processor, also referred to as an array processor, is a hardware processing device, such as a Central Processing Unit (CPU) or Graphics Processing Unit (GPU), implementing an Instruction Set Architecture (ISA) that contains vector instructions that operate on vectors, such as vector architecture, etc. A vector is a unidirectional array containing ordered scalar data elements. By operating on vectors containing multiple data elements, a vector processor may achieve significant performance improvements over a scalar processor that supports scalar instructions operating on a single data element.
The approaches described in this section are not necessarily approaches that have been previously conceived or pursued. Unless otherwise indicated, it should not be assumed that any of the approaches described in this section qualify as prior art merely by virtue of their inclusion in this section. Similarly, the problems mentioned in this section should not be considered as having been recognized in any prior art unless otherwise indicated.
Disclosure of Invention
The present disclosure provides a method, apparatus, electronic device, chip, computer readable storage medium and computer program product for data processing.
According to an aspect of the present disclosure, there is provided a data processing method including: determining an update vector for updating the storage space, wherein each element in the update vector has corresponding validity information; and performing a write control operation for any one element in the update vector, wherein the write control operation comprises: generating a blocking instruction for the element in response to the validity information of the element indicating that the element is invalid; and blocking the updating of the stored data in the storage space by the element using the blocking instruction.
According to another aspect of the present disclosure, there is provided a data processing apparatus including: a determining unit configured to determine an update vector for updating the storage space, wherein each element in the update vector has corresponding validity information; and a control unit configured to perform a write control operation for any one element in the update vector, wherein the control unit includes: a first generation subunit configured to generate a blocking instruction for the element in response to the validity information of the element indicating that the element is invalid; and a blocking subunit configured to block, with a blocking instruction, an update of the stored data within the storage space by the element.
According to another aspect of the present disclosure, there is provided a chip capable of performing the above-described data processing method.
According to another aspect of the present disclosure, there is provided an electronic device including: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method described above.
According to another aspect of the present disclosure, there is provided a non-transitory computer-readable storage medium storing computer instructions for causing a computer to perform the above-described method.
According to another aspect of the present disclosure, there is provided a computer program product comprising a computer program, wherein the computer program, when executed by a processor, implements the method described above.
According to one or more embodiments of the present disclosure, a read port pressure caused by reading stored data from a storage space can be avoided, and the execution efficiency of data processing can be ensured while saving a circuit area.
It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the disclosure, nor is it intended to be used to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the following specification.
Drawings
The accompanying drawings illustrate exemplary embodiments and, together with the description, serve to explain exemplary implementations of the embodiments. The illustrated embodiments are for exemplary purposes only and do not limit the scope of the claims. Throughout the drawings, identical reference numerals designate similar, but not necessarily identical, elements.
FIG. 1 illustrates an exemplary schematic diagram of a data process;
FIG. 2 illustrates a schematic diagram of an exemplary system in which various methods described herein may be implemented, in accordance with an embodiment of the present disclosure;
FIGS. 3A and 3B illustrate a flow chart of a data method according to an embodiment of the present disclosure;
FIG. 4 shows a schematic diagram of a data processing method according to an embodiment of the present disclosure;
FIG. 5 shows a block diagram of a data processing apparatus according to an embodiment of the present disclosure; and
fig. 6 illustrates a block diagram of an exemplary electronic device that can be used to implement embodiments of the present disclosure.
Detailed Description
Exemplary embodiments of the present disclosure are described below in conjunction with the accompanying drawings, which include various details of the embodiments of the present disclosure to facilitate understanding, and should be considered as merely exemplary. Accordingly, one of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope of the present disclosure. Also, descriptions of well-known functions and constructions are omitted in the following description for clarity and conciseness.
In the present disclosure, the use of the terms "first," "second," and the like to describe various elements is not intended to limit the positional relationship, timing relationship, or importance relationship of the elements, unless otherwise indicated, and such terms are merely used to distinguish one element from another element. In some examples, a first element and a second element may refer to the same instance of the element, and in some cases, they may also refer to different instances based on the description of the context.
The terminology used in the description of the various examples in this disclosure is for the purpose of describing particular examples only and is not intended to be limiting. Unless the context clearly indicates otherwise, the elements may be one or more if the number of the elements is not specifically limited. Furthermore, the term "and/or" as used in this disclosure encompasses any and all possible combinations of the listed items.
The main vector instruction sets support the functions of conditional execution of operation instructions, conditional read-write of access instructions and the like, and representative vector instruction sets include X86 AVX512, ARM NEON, RISC-VRV and the like.
FIG. 1 shows a schematic diagram of an exemplary data processing. As shown in fig. 1, the original storage data in the storage space is shown as 111, and the source vector 121 and the source vector 122 perform vector addition operation, and the operation results of both are used as update vectors for updating the original storage data 111 in the storage space. Validity information 130 shows the validity of each element in the update vector, and for each original in the update vector, if the validity information corresponding to the element is 1 (i.e., indicates that the element is valid), the element, for example, b2+c2, is written into the storage space; in the case where the validity information corresponding to the element is 0 (i.e., indicates that the element is invalid), the storage data of the corresponding storage bit in the storage space is unchanged, and thus updated storage data 112 of the storage space can be obtained.
In the related art, in order to implement the conditional execution logic as exemplarily shown in fig. 1, it is necessary to read original storage data in advance from a storage space, and thereafter, perform an operation between the original storage data and an update vector. In the operation, based on the validity information, only a part of elements in the update vector are used to update the original storage data, and thus, the obtained operation result is used as the update storage data and written into the storage space.
However, the above-described processing method requires adding a read port for reading the original stored data to the storage space, resulting in an increase in the area of the storage space, which is undoubtedly contrary to the current demand for miniaturized design of electronic devices. If a new read port is not set for reading the original storage data, other read ports existing in the storage space are needed to read the original storage data, which may cause resource conflict of the read ports, cause data blocking, increase the reading time of data required by operation, cause the processing pipeline to be lengthened, and cause the overall performance of the vector processor to be reduced.
Based on this, the present disclosure proposes a data processing method, performing, for any element in an update vector, a write control operation including at least generating a blocking instruction for the element in response to validity information of the element indicating that the element is invalid, and preventing, with the blocking instruction, an update of storage data in a storage space by the element.
Therefore, the method and the device can prevent the invalid element from updating the stored data through the generated blocking instruction, further realize the conditional execution logic under the condition of avoiding the stored data from being read from the storage space, avoid the processing pressure caused to the read port of the storage space, save the circuit area and ensure the execution efficiency of data processing.
Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.
Fig. 2 illustrates a schematic diagram of an exemplary system 200 in which the various methods and apparatus described herein may be implemented, in accordance with an embodiment of the present disclosure. Referring to fig. 2, the system 200 includes one or more client devices 201, 202, 203, 204, 205, and 206, a server 220, and one or more communication networks 210 coupling the one or more client devices to the server 220. Client devices 201, 202, 203, 204, 205, and 206 may be configured to execute one or more applications.
In embodiments of the present disclosure, server 220 may run one or more services or software applications that enable execution of data processing methods.
In some embodiments, server 220 may also provide other services or software applications that may include non-virtual environments and virtual environments. In some embodiments, these services may be provided as web-based services or cloud services, for example, provided to users of client devices 201, 202, 203, 204, 205, and/or 206 under a software as a service (SaaS) model.
In the configuration shown in fig. 2, server 220 may include one or more components that implement the functions performed by server 220. These components may include software components, hardware components, or a combination thereof that are executable by one or more processors. A user operating client devices 201, 202, 203, 204, 205, and/or 206 may in turn utilize one or more client applications to interact with server 220 to utilize the services provided by these components. It should be appreciated that a variety of different system configurations are possible, which may differ from system 200. Accordingly, FIG. 2 is one example of a system for implementing the various methods described herein and is not intended to be limiting.
The user may use the client devices 201, 202, 203, 204, 205, and/or 206 to perform the data processing methods of the present disclosure or to provide relevant data to a server for performing the data processing methods of the present disclosure. The client device may provide an interface that enables a user of the client device to interact with the client device. The client device may also output information to the user via the interface. Although fig. 2 depicts only six client devices, those skilled in the art will appreciate that the present disclosure may support any number of client devices.
Client devices 201, 202, 203, 204, 205, and/or 206 may include various types of computer devices, such as portable handheld devices, general purpose computers (such as personal computers and laptop computers), workstation computers, wearable devices, smart screen devices, self-service terminal devices, service robots, gaming systems, thin clients, various messaging devices, sensors or other sensing devices, and the like. These computer devices may run various types and versions of software applications and operating systems, such as MICROSOFT Windows, appli os, UNIX-like operating systems, linux, or Linux-like operating systems; or include various mobile operating systems such as MICROSOFT Windows Mobile OS, iOS, windows Phone, android. Portable handheld devices may include cellular telephones, smart phones, tablet computers, personal Digital Assistants (PDAs), and the like. Wearable devices may include head mounted displays (such as smart glasses) and other devices. The gaming system may include various handheld gaming devices, internet-enabled gaming devices, and the like. The client device is capable of executing a variety of different applications, such as various Internet-related applications, communication applications (e.g., email applications), short Message Service (SMS) applications, and may use a variety of communication protocols.
Network 220 may be any type of network known to those skilled in the art that may support data communications using any of a number of available protocols, including but not limited to TCP/IP, SNA, IPX, etc. For example only, the one or more networks 220 may be a Local Area Network (LAN), an ethernet-based network, a token ring, a Wide Area Network (WAN), the internet, a virtual network, a Virtual Private Network (VPN), an intranet, an extranet, a Public Switched Telephone Network (PSTN), an infrared network, a wireless network (e.g., bluetooth, WIFI), and/or any combination of these and/or other networks.
Server 220 may include one or more general-purpose computers, special-purpose server computers (e.g., a PC (personal computer) server, UNIX server, mid-end server), blade servers, mainframe computers, server clusters, or any other suitable arrangement and/or combination. Server 220 may include one or more virtual machines running a virtual operating system, or other computing architecture that involves virtualization (e.g., one or more flexible pools of logical storage devices that may be virtualized to maintain virtual storage devices of the server). In various embodiments, server 220 may run one or more services or software applications that provide the functionality described below.
The computing units in server 220 may run one or more operating systems including any of the operating systems described above as well as any commercially available server operating systems. Server 220 may also run any of a variety of additional server applications and/or middle tier applications, including HTTP servers, FTP servers, CGI servers, JAVA servers, database servers, etc.
In some implementations, server 220 may include one or more applications to analyze and consolidate data feeds and/or event updates received from users of client devices 201, 202, 203, 204, 205, and/or 206. Server 220 may also include one or more applications to display data feeds and/or real-time events via one or more display devices of client devices 201, 202, 203, 204, 205, and/or 206.
In some implementations, the server 220 may be a server of a distributed system or a server that incorporates a blockchain. Server 220 may also be a cloud server, or an intelligent cloud computing server or intelligent cloud host with artificial intelligence technology. The cloud server is a host product in a cloud computing service system, so as to solve the defects of large management difficulty and weak service expansibility in the traditional physical host and virtual private server (VPS, virtual Private Server) service.
The system 200 may also include one or more databases 230. In some embodiments, these databases may be used to store data and other information. For example, one or more of databases 230 may be used to store information such as audio files and video files. Database 230 may reside in a variety of locations. For example, the database used by server 220 may be local to server 220, or may be remote from server 220 and may communicate with server 220 via a network-based or dedicated connection. Database 230 may be of different types. In some embodiments, the database used by server 220 may be, for example, a relational database. One or more of these databases may store, update, and retrieve the databases and data from the databases in response to the commands.
In some embodiments, one or more of databases 230 may also be used by applications to store application data. The databases used by the application may be different types of databases, such as key value stores, object stores, or conventional stores supported by the file system.
The system 200 of fig. 2 may be configured and operated in various ways to enable application of the various methods and apparatus described in accordance with the present disclosure.
Fig. 3A and 3B illustrate a flow chart of a data processing method according to an exemplary embodiment of the present disclosure, including: step S301, determining an update vector for updating the storage space, wherein each element in the update vector has corresponding validity information; and step S302, performing a write control operation for any element in the update vector, where the write control operation may include: step S302-1, generating a blocking instruction for the element in response to the validity information of the element indicating that the element is invalid; and step S302-2, using the blocking instruction, preventing the element from updating the storage data in the storage space.
Therefore, the method and the device can prevent the invalid element from updating the stored data through the generated blocking instruction, further realize the conditional execution logic under the condition of avoiding the stored data from being read from the storage space, avoid the processing pressure caused to the read port of the storage space, save the circuit area and ensure the execution efficiency of data processing.
In step S301, the storage space may be a register file (register file).
According to some embodiments, the update vector may be the result of an operation on one or more source vectors from memory space.
Wherein one or more source vectors need to be read out of the memory space to perform the vector operation. In this scenario, the reading of one or more source vectors requires a read port that occupies memory space.
In the process of realizing the conditional execution logic, the method and the device do not need to read the storage data from the storage space, namely, the read port of the storage space is not occupied by the storage data, so that the reading efficiency of one or more source vectors can be ensured, and the execution efficiency of the whole vector processor is further improved.
According to some embodiments, the validity information may be determined based on a mask (mask) for the update vector.
In some application fields, such as graphics shaders, it may be desirable to implement a mechanism to suppress the effects of certain elements within a vector, which may be implemented through mask control. The mask control may occur based on the results of certain conditional statements (e.g., "IF", "ELSE" and "END-IF").
The mask for the update vector includes a plurality of mask bits, wherein the number of mask bits is equal to the number of elements in the update vector, each mask bit corresponding to an element in the update vector. For example, when the mask bit is 0, then the element in its corresponding update vector is invalid; when the mask bit is 1, then the element in its corresponding update vector is valid.
Based on this, the validity information of each element extracted from the mask (mask) of the update vector can be used as a basis for generating a control instruction (i.e., a blocking instruction or a writing instruction) of the element.
The write control operation for step S302 may further include step S302-1 of generating a blocking instruction for the element in response to the validity information of the element indicating that the element is invalid; and step S302-2, using the blocking instruction, preventing the element from updating the storage data in the storage space.
According to some embodiments, the write control operation may further include: generating a write instruction for the element in response to the validity information of the element indicating that the element is valid; and using the element for updating the stored data in the storage space using the write instruction.
In one embodiment, both the block instruction and the write instruction may be strobe (Strob) signals. For example, if the strobe signal = 0, the strobe signal may act as a blocking instruction, blocking the element from updating the stored data within the storage space; if the strobe signal = 1, then the strobe signal may be used as a write instruction to use the element for updating the stored data within the memory space.
According to some embodiments, using the element for updating the stored data within the storage space may include: determining a storage bit corresponding to the element in the storage space; and updating the stored data in the stored bits with the element.
Thus, the stored data in a specific storage bit in the storage space can be updated with the valid element in the update vector in a targeted manner.
The specific manner of updating the storage data in the storage bit with the element may be, for example, replacing the storage data in the storage bit with the element, accumulating the element on the storage data in the storage bit, and the like, which is not limited herein.
According to some embodiments, the memory space may be built up by a plurality of registers, and wherein the write control operation may be implemented based on a control module located outside the memory space.
Because the control module only needs to execute simple judgment logic before the elements are written into the register, the control module has low resource consumption for the whole processor and cannot influence the processing performance of the processor.
For example, an element and its corresponding strobe (Strob) signal may be input to the control module, which determines whether to update the stored data in the memory space with the element based on the Strob signal.
According to some embodiments, the storage space may be built by a memory (memory), and wherein the write control operation may be implemented based on a strobe (Strob) port located in the memory.
Since there is already a strobe (Strob) port in the memory (memory), the strobe port of the memory can be directly borrowed to realize write control of each element in the update vector without adding an additional processing module.
Fig. 4 shows a schematic diagram of a data processing method according to an exemplary embodiment of the present disclosure. In fig. 4, 410 is a register file (register file) constructed of a plurality of registers, 420 is a vector operation module, 430 is a strobe (strobe) signal generator, and the register file 410, the vector operation module 420, and the strobe (strobe) signal generator 430 may be provided on a chip.
As shown in fig. 4, the source vector S1 and the source vector S2 are read from the register file, and the vector operation module 420 performs vector operation on the source vector S1 and the source vector S2 to obtain an update vector for updating the register file 410, and transmits the update vector to the write port of the register file 410.
According to the mask 401 corresponding to the update vector, a strobe (Strob) signal for each element in the update vector is generated by a strobe (Strob) signal generator 430, respectively, and transmitted to the write port of the register file 410.
At the write port of register file 410, for each element in the update vector, a determination is made as to whether to update the stored data within the memory space with the element based on the strobe (strobe) signal corresponding to the element.
It follows that by setting the strobe (Strob) signal generator 430, a control instruction for each element in the update vector can be generated, which can be set as a blocking instruction or a writing instruction based on the validity information provided by the mask 401, thereby achieving conditional writing to the element in the update vector. The processing efficiency of the vector processor can be improved under the condition of not amplifying the chip area.
Fig. 5 shows a block diagram of a data processing apparatus according to an exemplary embodiment of the present disclosure, as shown in fig. 5, a data processing apparatus 500 includes: a determining unit 510 configured to determine an update vector for updating the storage space, wherein each element in the update vector has corresponding validity information; and a control unit 520 configured to perform a write control operation for any one element in the update vector, wherein the control unit includes: a first generation subunit 521 configured to generate a blocking instruction for the element in response to the validity information of the element indicating that the element is invalid; and a blocking subunit 522 configured to block, with a blocking instruction, an update of the stored data within the storage space by the element.
According to some embodiments, the control unit further comprises: a second generation subunit configured to generate a write instruction for the element in response to the validity information of the element indicating that the element is valid; and a write subunit configured to use the element for updating the stored data within the storage space with a write instruction.
According to some embodiments, the write subunit comprises: a subunit for determining a corresponding storage bit of the element in the storage space; and a subunit for updating the stored data in the stored bits with the element.
According to some embodiments, the memory space is built up by a plurality of registers, and wherein the control unit is arranged outside the memory space.
According to some embodiments, the storage space is built by a memory, and wherein the control unit is built based on a strobe port of the memory.
According to some embodiments, the validity information is determined based on a mask for the update vector.
According to some embodiments, the update vector is the result of an operation from one or more source vectors of memory space.
According to an embodiment of the present disclosure, there is also provided a chip capable of executing any one of the above-described data processing methods.
There is also provided, in accordance with an embodiment of the present disclosure, an electronic device including: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform any one of the methods described above.
There is also provided, in accordance with an embodiment of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions for causing a computer to perform any one of the methods described above.
There is also provided, in accordance with an embodiment of the present disclosure, a computer program product comprising a computer program, wherein the computer program, when executed by a processor, implements any of the methods described above.
Referring to fig. 6, a block diagram of an electronic device 600 that may be a server or a client of the present disclosure, which is an example of a hardware device that may be applied to aspects of the present disclosure, will now be described. Electronic devices are intended to represent various forms of digital electronic computer devices, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processing, cellular telephones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the disclosure described and/or claimed herein.
As shown in fig. 6, the electronic device 600 includes a computing unit 601 that can perform various appropriate actions and processes according to a computer program stored in a Read Only Memory (ROM) 602 or a computer program loaded from a storage unit 608 into a Random Access Memory (RAM) 603. In the RAM603, various programs and data required for the operation of the electronic device 600 can also be stored. The computing unit 601, ROM 602, and RAM603 are connected to each other by a bus 604. An input/output (I/O) interface 605 is also connected to bus 604.
A number of components in the electronic device 600 are connected to the I/O interface 605, including: an input unit 606, an output unit 607, a storage unit 608, and a communication unit 609. The input unit 606 may be any type of device capable of inputting information to the electronic device 600, the input unit 606 may receive input numeric or character information and generate key signal inputs related to user settings and/or function control of the electronic device, and may include, but is not limited to, a mouse, a keyboard, a touch screen, a trackpad, a trackball, a joystick, a microphone, and/or a remote control. The output unit 607 may be any type of device capable of presenting information and may include, but is not limited to, a display, speakers, video/audio output terminals, vibrators, and/or printers. Storage unit 608 may include, but is not limited to, magnetic disks, optical disks. The communication unit 609 allows the electronic device 600 to exchange information/data with other devices through a computer network, such as the internet, and/or various telecommunications networks, and may include, but is not limited to, modems, network cards, infrared communication devices, wireless communication transceivers and/or chipsets, such as bluetooth (TM) devices, 802.11 devices, wiFi devices, wiMax devices, cellular communication devices, and/or the like.
The computing unit 601 may be a variety of general and/or special purpose processing components having processing and computing capabilities. Some examples of computing unit 601 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various specialized Artificial Intelligence (AI) computing chips, various computing units running machine learning model algorithms, a Digital Signal Processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 601 performs the respective methods and processes described above, such as a data processing method. For example, in some embodiments, the data processing method may be implemented as a computer software program tangibly embodied on a machine-readable medium, such as storage unit 608. In some embodiments, part or all of the computer program may be loaded and/or installed onto the electronic device 600 via the ROM 602 and/or the communication unit 609. When a computer program is loaded into RAM603 and executed by computing unit 601, one or more steps of the data processing method described above may be performed. Alternatively, in other embodiments, the computing unit 601 may be configured to perform the data processing method by any other suitable means (e.g. by means of firmware).
Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuit systems, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), systems On Chip (SOCs), complex Programmable Logic Devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs, the one or more computer programs may be executed and/or interpreted on a programmable system including at least one programmable processor, which may be a special purpose or general-purpose programmable processor, that may receive data and instructions from, and transmit data and instructions to, a storage system, at least one input device, and at least one output device.
Program code for carrying out methods of the present disclosure may be written in any combination of one or more programming languages. These program code may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus such that the program code, when executed by the processor or controller, causes the functions/operations specified in the flowchart and/or block diagram to be implemented. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.
In the context of this disclosure, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. The machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and pointing device (e.g., a mouse or trackball) by which a user can provide input to the computer. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic input, speech input, or tactile input.
The systems and techniques described here can be implemented in a computing system that includes a background component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such background, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), and the internet.
The computer system may include a client and a server. The client and server are typically remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server may be a cloud server, a server of a distributed system, or a server incorporating a blockchain.
It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps recited in the present disclosure may be performed in parallel, sequentially or in a different order, provided that the desired results of the disclosed aspects are achieved, and are not limited herein.
In the technical scheme of the disclosure, the related processes of collecting, storing, using, processing, transmitting, providing, disclosing and the like of the personal information of the user accord with the regulations of related laws and regulations, and the public order colloquial is not violated.
Although embodiments or examples of the present disclosure have been described with reference to the accompanying drawings, it is to be understood that the foregoing methods, systems, and apparatus are merely exemplary embodiments or examples, and that the scope of the present invention is not limited by these embodiments or examples but only by the claims following the grant and their equivalents. Various elements of the embodiments or examples may be omitted or replaced with equivalent elements thereof. Furthermore, the steps may be performed in a different order than described in the present disclosure. Further, various elements of the embodiments or examples may be combined in various ways. It is important that as technology evolves, many of the elements described herein may be replaced by equivalent elements that appear after the disclosure.
Claims (13)
1. A data processing method, comprising:
determining an update vector for updating a storage space and transmitting the update vector to a write port of the storage space, wherein each element in the update vector has corresponding validity information; and
performing a write control operation for any one element in the update vector, wherein the write control operation includes:
generating a blocking instruction for the element in response to the validity information of the element indicating that the element is invalid, the blocking instruction not containing stored data in the storage space;
the blocking instruction is utilized at a write port of the storage space to prevent the element from updating the storage data in the storage space;
generating a write instruction for the element in response to the validity information of the element indicating that the element is valid; and
using the write instruction at a write port of the memory space, using the element for updating the stored data in the memory space,
the storage space is constructed through a memory, the write-in control operation is realized based on a gating port positioned in the memory, and the blocking instruction and the write-in instruction are both based on gating signals corresponding to the gating port.
2. The method of claim 1, wherein the using the element for updating the stored data within the storage space comprises:
determining a storage bit corresponding to the element in the storage space; and
the element is used to update the stored data in the stored bits.
3. The method of claim 1 or 2, wherein the storage space is built up by a plurality of registers, and wherein the write control operation is implemented based on a control module located outside the storage space.
4. A method according to any one of claims 1 to 3, wherein the validity information is determined based on a mask for the update vector.
5. The method of any of claims 1-4, wherein the update vector is a result of an operation from one or more source vectors of the storage space.
6. A data processing apparatus comprising:
a determining unit configured to determine an update vector for updating a storage space and to transmit the update vector to a write port of the storage space, wherein each element in the update vector has corresponding validity information; and
a control unit configured to perform a write control operation for any one element in the update vector, wherein the control unit includes:
a first generation subunit configured to generate a blocking instruction for the element in response to the validity information of the element indicating that the element is invalid, the blocking instruction not containing the stored data within the storage space;
a blocking subunit configured to block, at a write port of the storage space, updating of storage data in the storage space by the element using the blocking instruction;
a second generation subunit configured to generate a write instruction for the element in response to the validity information of the element indicating that the element is valid; and
a write subunit configured to use the element for updating the stored data in the storage space with the write instruction at a write port of the storage space,
the storage space is constructed through a memory, the write-in control operation is realized based on a gating port positioned in the memory, and the blocking instruction and the write-in instruction are both based on gating signals corresponding to the gating port.
7. The apparatus of claim 6, wherein the write subunit comprises:
a subunit for determining a corresponding storage bit of the element in the storage space; and
a subunit for updating the stored data in the storage bits with the element.
8. The apparatus of claim 6 or 7, wherein the storage space is constructed by a plurality of registers, and wherein the control unit is disposed outside the storage space.
9. The apparatus of any of claims 6 to 8, wherein the validity information is determined based on a mask for the update vector.
10. The apparatus of any of claims 6 to 9, wherein the update vector is a result of an operation of one or more source vectors from the storage space.
11. A chip capable of performing the data processing method of any one of claims 1-5.
12. An electronic device, comprising:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein the method comprises the steps of
The memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-5.
13. A non-transitory computer readable storage medium storing computer instructions for causing a computer to perform the method of any one of claims 1-5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210665616.5A CN115098165B (en) | 2022-06-13 | 2022-06-13 | Data processing method, device, chip, equipment and medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210665616.5A CN115098165B (en) | 2022-06-13 | 2022-06-13 | Data processing method, device, chip, equipment and medium |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN115098165A CN115098165A (en) | 2022-09-23 |
| CN115098165B true CN115098165B (en) | 2023-09-08 |
Family
ID=83291872
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210665616.5A Active CN115098165B (en) | 2022-06-13 | 2022-06-13 | Data processing method, device, chip, equipment and medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115098165B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102103570A (en) * | 2009-12-22 | 2011-06-22 | 英特尔公司 | Synchronizing SIMD vectors |
| CN106030510A (en) * | 2014-03-26 | 2016-10-12 | 英特尔公司 | Three source operand floating point addition processors, methods, systems, and instructions |
| CN106575216A (en) * | 2014-09-19 | 2017-04-19 | 英特尔公司 | Data element selection and consolidation processors, methods, systems, and instructions |
| CN113407351A (en) * | 2021-07-20 | 2021-09-17 | 北京百度网讯科技有限公司 | Method, apparatus, chip, device, medium and program product for performing operations |
| CN113986788A (en) * | 2021-10-28 | 2022-01-28 | 昆仑芯(北京)科技有限公司 | Data processing method and device, chip, electronic device and medium |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10157061B2 (en) * | 2011-12-22 | 2018-12-18 | Intel Corporation | Instructions for storing in general purpose registers one of two scalar constants based on the contents of vector write masks |
| US9489196B2 (en) * | 2011-12-23 | 2016-11-08 | Intel Corporation | Multi-element instruction with different read and write masks |
| US20160179530A1 (en) * | 2014-12-23 | 2016-06-23 | Elmoustapha Ould-Ahmed-Vall | Instruction and logic to perform a vector saturated doubleword/quadword add |
-
2022
- 2022-06-13 CN CN202210665616.5A patent/CN115098165B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102103570A (en) * | 2009-12-22 | 2011-06-22 | 英特尔公司 | Synchronizing SIMD vectors |
| CN106030510A (en) * | 2014-03-26 | 2016-10-12 | 英特尔公司 | Three source operand floating point addition processors, methods, systems, and instructions |
| CN106575216A (en) * | 2014-09-19 | 2017-04-19 | 英特尔公司 | Data element selection and consolidation processors, methods, systems, and instructions |
| CN113407351A (en) * | 2021-07-20 | 2021-09-17 | 北京百度网讯科技有限公司 | Method, apparatus, chip, device, medium and program product for performing operations |
| CN113986788A (en) * | 2021-10-28 | 2022-01-28 | 昆仑芯(北京)科技有限公司 | Data processing method and device, chip, electronic device and medium |
Also Published As
| Publication number | Publication date |
|---|---|
| CN115098165A (en) | 2022-09-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN113986788A (en) | Data processing method and device, chip, electronic device and medium | |
| CN115098165B (en) | Data processing method, device, chip, equipment and medium | |
| CN116306396A (en) | Chip verification method and device, equipment and medium | |
| CN114510308B (en) | Method, device, equipment and medium for storing application page by mobile terminal | |
| CN113641929B (en) | Page rendering method, device, electronic equipment and computer readable storage medium | |
| CN114359017B (en) | Multimedia resource processing method and device and electronic equipment | |
| CN114040381A (en) | Encryption method, decryption method, device and electronic equipment | |
| CN114095564A (en) | Data processing method and device, equipment and medium | |
| CN117194126A (en) | Storage system testing method and device, electronic equipment and storage medium | |
| CN114398653B (en) | Data processing method, device, electronic equipment and medium | |
| CN115334159B (en) | Method, apparatus, device and medium for processing stream data | |
| CN116700791A (en) | Method, apparatus, device and medium for caching instructions | |
| CN113312050B (en) | Content display method, device, equipment and medium | |
| CN115033286A (en) | Data processing method, device, chip, equipment and medium | |
| CN116841773B (en) | Data interaction method and device, electronic equipment and storage medium | |
| US11870668B1 (en) | System and method for managing data processing systems and hosted devices | |
| CN112764828B (en) | Business logic management method and device, computer equipment and medium | |
| CN117196932A (en) | Image processing method, device, equipment and medium | |
| CN113010383B (en) | Error log filtering method, device, electronic equipment and readable medium | |
| CN117193647A (en) | Data processing task sending method, data processing device and equipment | |
| CN115951894A (en) | Data processing method, device, electronic equipment and medium | |
| CN115934034A (en) | Data processing method and device, equipment and medium | |
| CN116599895A (en) | Data transmission method, device, equipment and medium | |
| CN115373853A (en) | Shared memory cleaning method and device, electronic equipment and medium | |
| CN117834911A (en) | Buffering method, buffering device, electronic equipment and medium for video coding |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP02 | Change in the address of a patent holder |
Address after: CW District, 4th floor, building 1, No. 10, Shangdi 10th Street, Haidian District, Beijing 100101 Patentee after: Kunlun core (Beijing) Technology Co.,Ltd. Address before: Baidu building, No. 10, Shangdi 10th Street, Haidian District, Beijing 100086 Patentee before: Kunlun core (Beijing) Technology Co.,Ltd. |
|
| CP02 | Change in the address of a patent holder |