CN116306396A - Chip verification method and device, equipment and medium - Google Patents
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Abstract
The disclosure provides a chip verification method, a device, equipment and a medium, relates to the technical field of computers, and particularly relates to the technical field of chips. The implementation scheme is as follows: acquiring an instruction set and a target verification option; acquiring target constraint information based on the target verification option, wherein the target constraint information comprises target constraint conditions and types of the target constraint conditions; based on the type of the target constraint condition, a template of a random configuration instruction corresponding to the target constraint information is obtained; generating an executable random configuration instruction based on the template of the random configuration instruction and the target constraint condition; executing the random configuration instruction to randomly determine at least one target instruction from the instruction set, wherein the at least one target instruction meets the target constraint; executing the at least one target instruction by using the chip to be verified; and determining a verification result for the chip to be verified based on the execution result of the at least one target instruction.
Description
Technical Field
The present disclosure relates to the field of computer technology, and in particular, to the field of chip technology, and more particularly, to a chip verification method, apparatus, electronic device, computer readable storage medium, and computer program product.
Background
Artificial intelligence is the discipline of studying the process of making a computer mimic certain mental processes and intelligent behaviors (e.g., learning, reasoning, thinking, planning, etc.) of a person, both hardware-level and software-level techniques. Artificial intelligence hardware technologies generally include technologies such as sensors, dedicated artificial intelligence chips, cloud computing, distributed storage, big data processing, and the like; the artificial intelligence software technology mainly comprises a computer vision technology, a voice recognition technology, a natural language processing technology, a machine learning/deep learning technology, a big data processing technology, a knowledge graph technology and the like.
In order to accommodate the development of artificial intelligence technology, the chip scale and process for executing algorithms based on artificial intelligence are further improved, and more accurate and efficient chip verification technology needs to be applied.
The approaches described in this section are not necessarily approaches that have been previously conceived or pursued. Unless otherwise indicated, it should not be assumed that any of the approaches described in this section qualify as prior art merely by virtue of their inclusion in this section. Similarly, the problems mentioned in this section should not be considered as having been recognized in any prior art unless otherwise indicated.
Disclosure of Invention
The present disclosure provides a chip verification method, apparatus, electronic device, computer readable storage medium and computer program product.
According to an aspect of the present disclosure, there is provided a chip verification method including: acquiring an instruction set and a target verification option; acquiring target constraint information based on the target verification option, wherein the target constraint information comprises target constraint conditions and types of the target constraint conditions; based on the type of the target constraint condition, a template of a random configuration instruction corresponding to the target constraint information is obtained; generating an executable random configuration instruction based on the template of the random configuration instruction and the target constraint condition; executing the random configuration instruction to randomly determine at least one target instruction from the instruction set, wherein the at least one target instruction meets the target constraint; executing the at least one target instruction by using the chip to be verified; and determining a verification result for the chip to be verified based on the execution result of the at least one target instruction.
According to another aspect of the present disclosure, there is provided a chip authentication apparatus including: a first acquisition unit configured to acquire an instruction set and a target authentication option; a second acquisition unit configured to acquire target constraint information including a target constraint condition and a type of the target constraint condition based on the target verification option; a third obtaining unit configured to obtain a template of a random configuration instruction corresponding to the target constraint information based on a type of the target constraint condition; a generation unit configured to generate an executable random configuration instruction based on a template of the random configuration instruction and the target constraint condition; a first determining unit configured to execute the random configuration instruction to randomly determine at least one target instruction from the instruction set, wherein the at least one target instruction meets the target constraint; an execution unit configured to execute the at least one target instruction using the chip to be verified; and a second determining unit configured to determine a verification result for the chip to be verified based on an execution result of the at least one target instruction.
According to another aspect of the present disclosure, there is provided a chip including the chip authentication apparatus as described above.
According to another aspect of the present disclosure, there is provided an electronic device including: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the chip authentication method described above.
According to another aspect of the present disclosure, there is provided a non-transitory computer-readable storage medium storing computer instructions for causing the computer to perform the above-described chip authentication method.
According to another aspect of the present disclosure, there is provided a computer program product comprising a computer program, wherein the computer program is capable of implementing the above-described chip authentication method when being executed by a processor.
According to one or more embodiments of the present disclosure, efficiency and convenience of chip verification may be improved.
It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the disclosure, nor is it intended to be used to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the following specification.
Drawings
The accompanying drawings illustrate exemplary embodiments and, together with the description, serve to explain exemplary implementations of the embodiments. The illustrated embodiments are for exemplary purposes only and do not limit the scope of the claims. Throughout the drawings, identical reference numerals designate similar, but not necessarily identical, elements.
FIG. 1 illustrates a schematic diagram of an exemplary system in which various methods described herein may be implemented, according to an exemplary embodiment of the present disclosure;
FIG. 2 illustrates a flow chart of a chip verification method according to an exemplary embodiment of the present disclosure;
FIG. 3 shows a schematic diagram of a chip verification process according to an exemplary embodiment of the present disclosure;
FIG. 4 shows a schematic diagram of a constraint information base according to an exemplary embodiment of the present disclosure;
fig. 5 shows a block diagram of a chip authentication apparatus according to an exemplary embodiment of the present disclosure;
fig. 6 illustrates a block diagram of an exemplary electronic device that can be used to implement embodiments of the present disclosure.
Detailed Description
Exemplary embodiments of the present disclosure are described below in conjunction with the accompanying drawings, which include various details of the embodiments of the present disclosure to facilitate understanding, and should be considered as merely exemplary. Accordingly, one of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope of the present disclosure. Also, descriptions of well-known functions and constructions are omitted in the following description for clarity and conciseness.
In the present disclosure, the use of the terms "first," "second," and the like to describe various elements is not intended to limit the positional relationship, timing relationship, or importance relationship of the elements, unless otherwise indicated, and such terms are merely used to distinguish one element from another. In some examples, a first element and a second element may refer to the same instance of the element, and in some cases, they may also refer to different instances based on the description of the context.
The terminology used in the description of the various illustrated examples in this disclosure is for the purpose of describing particular examples only and is not intended to be limiting. Unless the context clearly indicates otherwise, the elements may be one or more if the number of the elements is not specifically limited. Furthermore, the term "and/or" as used in this disclosure encompasses any and all possible combinations of the listed items.
In the related art, the code of the random configuration instruction is usually manually copied and modified to adjust the constraint content in the code, so as to influence the execution result of the random configuration instruction. And obtaining at least one random target instruction by executing the random configuration instruction, further enabling the chip to be verified to execute the target instruction, and indicating whether the corresponding function of the chip to be verified is normal or not by utilizing the execution result of the target instruction, thereby realizing the verification of the chip to be verified. However, the manual configuration of the code is inefficient and costly, thereby affecting the efficiency of chip verification.
Based on the above, the disclosure provides a chip verification method, which obtains corresponding target constraint information by obtaining a target verification option set by a user, efficiently generates an executable random configuration instruction by using the target constraint information and a template of the corresponding random configuration instruction, and obtains at least one target instruction for chip verification by executing the random configuration instruction, so that the efficiency and convenience of configuring the random target instruction can be improved, and further, the chip verification can be executed by using the target instruction, and the efficiency and convenience of chip verification are improved.
Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.
Fig. 1 illustrates a schematic diagram of an exemplary system 100 in which various methods and apparatus described herein may be implemented, in accordance with an embodiment of the present disclosure. Referring to fig. 1, the system 100 includes one or more client devices 101, 102, 103, 104, 105, and 106, a server 120, and one or more communication networks 110 coupling the one or more client devices to the server 120. Client devices 101, 102, 103, 104, 105, and 106 may be configured to execute one or more applications.
In embodiments of the present disclosure, the server 120 may run one or more services or software applications that enable execution of the chip authentication method.
In some embodiments, server 120 may also provide other services or software applications, which may include non-virtual environments and virtual environments. In some embodiments, these services may be provided as web-based services or cloud services, for example, provided to users of client devices 101, 102, 103, 104, 105, and/or 106 under a software as a service (SaaS) model.
In the configuration shown in fig. 1, server 120 may include one or more components that implement the functions performed by server 120. These components may include software components, hardware components, or a combination thereof that are executable by one or more processors. A user operating client devices 101, 102, 103, 104, 105, and/or 106 may in turn utilize one or more client applications to interact with server 120 to utilize the services provided by these components. It should be appreciated that a variety of different system configurations are possible, which may differ from system 100. Accordingly, FIG. 1 is one example of a system for implementing the various methods described herein and is not intended to be limiting.
The user may send the target authentication options using client devices 101, 102, 103, 104, 105, and/or 106. The client device may provide an interface that enables a user of the client device to interact with the client device. The client device may also output information to the user via the interface. Although fig. 1 depicts only six client devices, those skilled in the art will appreciate that the present disclosure may support any number of client devices.
The server 120 may include one or more general purpose computers, special purpose server computers (e.g., PC (personal computer) servers, UNIX servers, mid-end servers), blade servers, mainframe computers, server clusters, or any other suitable arrangement and/or combination. The server 120 may include one or more virtual machines running a virtual operating system, or other computing architecture that involves virtualization (e.g., one or more flexible pools of logical storage devices that may be virtualized to maintain virtual storage devices of the server). In various embodiments, server 120 may run one or more services or software applications that provide the functionality described below.
The computing units in server 120 may run one or more operating systems including any of the operating systems described above as well as any commercially available server operating systems. Server 120 may also run any of a variety of additional server applications and/or middle tier applications, including HTTP servers, FTP servers, CGI servers, JAVA servers, database servers, etc.
In some implementations, server 120 may include one or more applications to analyze and consolidate data feeds and/or event updates received from users of client devices 101, 102, 103, 104, 105, and 106. Server 120 may also include one or more applications to display data feeds and/or real-time events via one or more display devices of client devices 101, 102, 103, 104, 105, and 106.
In some implementations, the server 120 may be a server of a distributed system or a server that incorporates a blockchain. The server 120 may also be a cloud server, or an intelligent cloud computing server or intelligent cloud host with artificial intelligence technology. The cloud server is a host product in a cloud computing service system, so as to solve the defects of large management difficulty and weak service expansibility in the traditional physical host and virtual private server (VPS, virtual Private Server) service.
The system 100 may also include one or more databases 130. In some embodiments, these databases may be used to store data and other information. For example, one or more of databases 130 may be used to store information such as audio files and video files. Database 130 may reside in various locations. For example, the database used by the server 120 may be local to the server 120, or may be remote from the server 120 and may communicate with the server 120 via a network-based or dedicated connection. Database 130 may be of different categories. In some embodiments, the database used by server 120 may be, for example, a relational database. One or more of these databases may store, update, and retrieve the databases and data from the databases in response to the commands.
In some embodiments, one or more of databases 130 may also be used by applications to store application data. The databases used by the application may be different types of databases, such as key value stores, object stores, or conventional stores supported by the file system.
The system 100 of fig. 1 may be configured and operated in various ways to enable application of the various methods and apparatus described in accordance with the present disclosure.
Fig. 2 shows a flowchart of a chip authentication method 200 according to an exemplary embodiment of the present disclosure. As shown in fig. 2, the method 200 includes:
step S201, acquiring an instruction set and target verification options;
step S202, acquiring target constraint information based on the target verification option, wherein the target constraint information comprises target constraint conditions and types of the target constraint conditions;
step S203, based on the type of the target constraint condition, a template of a random configuration instruction corresponding to the target constraint information is obtained;
step S204, based on the template of the random configuration instruction and the target constraint condition, generating an executable random configuration instruction;
step S205, executing the random configuration instruction to randomly determine at least one target instruction from the instruction set, wherein the at least one target instruction meets the target constraint condition;
step S206, executing the at least one target instruction by using the chip to be verified; and
step S207, determining a verification result for the chip to be verified based on the execution result of the at least one target instruction.
Therefore, the target constraint information corresponding to the target constraint information can be acquired based on the target verification option set by the user, the executable random configuration instruction is efficiently generated by utilizing the target constraint information and the template of the corresponding random configuration instruction, at least one target instruction for chip verification is obtained by executing the random configuration instruction, the efficiency and convenience of random target instruction configuration can be improved, chip verification can be further executed by utilizing the target instruction, and the efficiency and convenience of chip verification are improved.
In some examples, the chip to be verified may be various types of chips, particularly data processing chips, such as chips for performing deep learning algorithms, voice processing chips, image processing chips, and the like.
By using the steps S201-S204 to generate the random configuration instruction, the configuration result of the target instruction can be controlled by using the target verification option, the code of the random configuration instruction is not required to be repeatedly modified, compiling is only required to be executed once in the code running process, and different target constraint information is required to be configured according to different target verification options, so that the configuration efficiency of the target instruction is improved, and the efficiency of chip verification is improved.
In some examples, the instruction set may be configured in advance by an associated person according to the verification requirement, and by executing a specific random configuration instruction, at least one target instruction may be randomly selected from the instruction set to form a random instruction stream, so that the random instruction stream may be executed by the chip to be verified, so as to implement verification of the specific function of the chip.
In some examples, the contents of the operands, parameters, etc. of the target instruction may be further configured after randomly picking at least one target instruction from the instruction set by executing a random configuration instruction. In one example, when the chip to be authenticated is a data processing chip, by executing the random configuration instruction, it is possible to determine at least one target instruction from a pre-configured set of data processing instructions, and further configure data processing parameters associated with the target instruction according to the requirements. For example, the convolution instruction for performing convolution calculation based on the input feature map may be determined from the instruction set by configuring the random configuration instruction, and the data processing parameter associated therewith may include the size of the input feature map, the number of convolution channels, the size of the convolution kernel, the convolution step size, and the like, based on which the convolution calculation function of the chip to be verified is verified.
According to some embodiments, the type of target constraint includes at least one of: a condition for constraining a type of the at least one target instruction, a condition for constraining a type of an operand of the at least one target instruction, and a condition for constraining a size of an operand of the at least one target instruction. Therefore, the execution result of the random configuration instruction can be restrained by utilizing various different types of target constraint conditions, namely, the range of the instruction randomization is limited according to the requirement, so that at least one required target instruction can be obtained conveniently and efficiently, and verification of a specific chip function can be realized.
In some examples, the target constraint may also include more types, such as a condition for constraining a sequential relationship of a plurality of target instructions, a condition for constraining a read address of a target instruction, a condition for constraining a read address of an operand of a target instruction, as long as a limitation on contents of the target instruction can be achieved, which is not limited by the present disclosure.
According to some embodiments, obtaining target constraint information based on the target verification option in step S202 includes: and obtaining target constraint information corresponding to the target verification options from a constraint information base, wherein at least one verification option and constraint information corresponding to each verification option in the at least one verification option are stored in the constraint information base. Therefore, constraint information can be stored by utilizing the constraint information base, and target constraint information can be acquired more conveniently and rapidly by inquiring the mapping relation between verification options and constraint information in the constraint information base, so that the efficiency and convenience of chip verification are improved.
In some examples, the constraint information base may be configured in advance by the relevant personnel according to commonly used verification requirements.
In some examples, the target verification option may be a combination of a plurality of sub-target verification options, and further, a plurality of sub-constraint information corresponding to the plurality of sub-target verification options respectively may be obtained from the constraint information base based on the target verification option, so as to obtain target constraint information including the plurality of sub-constraint information.
According to some embodiments, the constraint information base includes a plurality of sub constraint information bases, and each of the plurality of sub constraint information bases stores constraint information having a corresponding constraint condition of a same type, and the method 200 further includes: acquiring types of constraint conditions corresponding to the multiple sub constraint information bases respectively; the type of the target constraint is determined based on the type of the constraint corresponding to a target sub-constraint library storing the target constraint. Therefore, the types of the target constraint conditions can be more conveniently determined by storing constraint information of different types into different sub constraint information bases, templates of corresponding random configuration instructions are rapidly matched, the generation efficiency of the random configuration instructions is improved, and the chip verification efficiency is further improved.
According to some embodiments, at least one of the plurality of sub-constraint information bases is a template class. By defining constraint information bases of different types as template classes, the contents and formats of constraint conditions in sub constraint information bases can be efficiently and conveniently managed. In some examples, constraint conditions in the sub constraint information base defined as template classes have the same format, so that target constraint conditions can be simply obtained in the form of object recall, a complex compiling process of random configuration instruction codes is not required to be executed, and the configuration efficiency of target instructions is improved.
According to some embodiments, the template of the random configuration instruction includes an empty queue, and generating the executable random configuration instruction in step S206 based on the template of the random configuration instruction and the target constraint includes: and storing the target constraint condition into the empty queue to obtain an executable random configuration instruction. Therefore, an empty queue is reserved in the template of the random configuration instruction, and the executable random configuration instruction can be obtained efficiently in a mode of filling target constraint conditions, so that the efficiency of chip verification is improved.
In some examples, a queue corresponding to the types of the random configuration instruction and the target constraint condition may be configured and defined as a rand type, and after the target constraint condition is stored in the queue, the corresponding relationship between the target constraint condition and the handle of the random configuration instruction may be configured, so as to simply and efficiently generate the executable random configuration instruction.
In some examples, the execution of the at least one target instruction with the chip to be verified in step S206 may be implemented in a software or hardware-based manner. For example, chip circuits may be designed and configured in a software environment using hardware description languages such as Verilog and VHDL (Veri-High-Speed Integrate Circuit Hardware Description Language, ultra-High-speed integrated circuit hardware description language), and after compiling to generate chip circuit netlist information that can be used for simulation, simulation verification of the chip circuits is performed based on the chip circuit netlist information. In some examples, RTL (Register Transfer Level ) code of the chip circuit to be verified may be obtained in a software environment to describe the data flow of the chip circuit, thereby enabling RTL emulation for the chip. In some examples, the corresponding code that generates the hardware description language may also be written in other languages (e.g., the C language), resulting in chip circuit netlist information that may be used for simulation. For another example, the corresponding hardware circuit may be implemented according to the hardware description language or the circuit netlist information, and verification may be performed on the hardware circuit.
In some examples, when the chip to be verified is a data processing chip, the determining, in step S207, the verification result for the chip to be verified based on the execution result of the at least one target instruction may be implemented by using the following steps: after at least one target instruction is obtained by executing step S201 to step S205, input data and target output data corresponding to the input data are determined based on the target instruction; executing at least one target instruction by using the chip to be verified so as to realize data processing based on input data and obtain output data to be verified, which is output by the chip to be verified; and determining a verification result for the chip to be verified based on the target output data and the output data to be verified. In some examples, a model capable of implementing the respective data processing functions may be written using a computer program, with the model being used to derive the target output data. Therefore, whether the output data to be verified is accurate or not can be indicated by utilizing the target output data, and therefore a verification result aiming at the chip to be verified is obtained.
Fig. 3 shows a schematic diagram of a chip verification process according to an exemplary embodiment of the present disclosure. As shown in fig. 3, the user can control the chip authentication process identified by Test1 by configuring the target authentication option 1, and control the chip authentication process identified by Test2 by configuring the target authentication option 2. By utilizing the method 200 as described above, the target constraint information 1 and the target constraint information 2 can be respectively acquired based on the target verification option 1 and the target verification option 2, and then executable random instructions are generated based on the target constraint information 1 and the target constraint information 2, so as to respectively realize control over random processes contained in the chip verification processes identified by the Test1 and the Test2, and generate target instruction streams meeting the requirements of users, so as to verify the corresponding functions of the chip more accurately and efficiently.
Fig. 4 shows a schematic diagram of a constraint information base 400 according to an exemplary embodiment of the present disclosure. As shown in fig. 4, constraint information base 400 may include an address sub-constraint information base 401, a data sub-constraint information base 402, and a parameter sub-constraint information base 403. The user may configure different types of constraints according to the requirements and store them in the corresponding sub-constraint information base, and may include, for example, address constraints for constraining the target instruction and/or the read address of the operand of the target instruction, data constraints for constraining the operand of the target instruction, parameter constraints for constraining the parameter of the target instruction, and so on.
According to another aspect of the present disclosure, there is also provided a chip verification apparatus. Fig. 5 shows a block diagram of a chip authentication apparatus 500 according to an exemplary embodiment of the present disclosure. As shown in fig. 5, the apparatus 500 includes:
a first obtaining unit 501 configured to obtain an instruction set and a target verification option;
a second obtaining unit 502 configured to obtain target constraint information based on the target verification option, the target constraint information including a target constraint condition and a type of the target constraint condition;
a third obtaining unit 503 configured to obtain a template of a random configuration instruction corresponding to the target constraint information based on the type of the target constraint condition;
a generating unit 504 configured to generate an executable random configuration instruction based on the template of the random configuration instruction and the target constraint condition;
a first determining unit 505 configured to execute the random configuration instruction to randomly determine at least one target instruction from the instruction set, wherein the at least one target instruction meets the target constraint;
an execution unit 506 configured to execute the at least one target instruction with the chip to be verified; and
A second determining unit 507 configured to determine a verification result for the chip to be verified based on an execution result of the at least one target instruction.
According to some embodiments, the second acquisition unit 502 is configured to: and obtaining target constraint information corresponding to the target verification options from a constraint information base, wherein at least one verification option and constraint information corresponding to each verification option in the at least one verification option are stored in the constraint information base.
According to some embodiments, the constraint information base includes a plurality of sub constraint information bases, and each of the plurality of sub constraint information bases stores constraint information of a corresponding constraint condition of a same type, and the method further includes: acquiring types of constraint conditions corresponding to the multiple sub constraint information bases respectively; the type of the target constraint is determined based on the type of the constraint corresponding to a target sub-constraint library storing the target constraint.
According to some embodiments, at least one of the plurality of sub-constraint information bases is a template class.
According to some embodiments, the type of target constraint includes at least one of: a condition for constraining a type of the at least one target instruction, a condition for constraining a type of an operand of the at least one target instruction, and a condition for constraining a size of an operand of the at least one target instruction.
According to some embodiments, the template of the random configuration instruction comprises an empty queue, the generating unit 504 being configured to: and storing the target constraint condition into the empty queue to obtain an executable random configuration instruction.
According to another aspect of the present disclosure, there is also provided a chip comprising the apparatus 500 as described above.
According to another aspect of the present disclosure, there is also provided an electronic apparatus including: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the chip authentication method described above.
According to another aspect of the present disclosure, there is also provided a non-transitory computer-readable storage medium storing computer instructions for causing the computer to perform the above-described chip authentication method.
According to another aspect of the present disclosure, there is also provided a computer program product comprising a computer program, wherein the computer program, when executed by a processor, implements the chip authentication method described above.
Referring to fig. 6, a block diagram of an electronic device 600 that may be a server or a client of the present disclosure, which is an example of a hardware device that may be applied to aspects of the present disclosure, will now be described. Electronic devices are intended to represent various forms of digital electronic computer devices, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processing, cellular telephones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the disclosure described and/or claimed herein.
As shown in fig. 6, the apparatus 600 includes a computing unit 601 that can perform various appropriate actions and processes according to a computer program stored in a Read Only Memory (ROM) 602 or a computer program loaded from a storage unit 608 into a Random Access Memory (RAM) 603. In the RAM 603, various programs and data required for the operation of the device 600 may also be stored. The computing unit 601, ROM 602, and RAM 603 are connected to each other by a bus 604. An input/output (I/O) interface 605 is also connected to bus 604.
Various components in the device 600 are connected to the I/O interface 605, including: an input unit 606, an output unit 607, a storage unit 608, and a communication unit 609. The input unit 606 may be any type of device capable of inputting information to the device 600, the input unit 606 may receive input numeric or character information and generate key signal inputs related to user settings and/or function control of the electronic device, and may include, but is not limited to, a mouse, a keyboard, a touch screen, a trackpad, a trackball, a joystick, a microphone, and/or a remote control. The output unit 607 may be any type of device capable of presenting information and may include, but is not limited to, a display, speakers, video/audio output terminals, vibrators, and/or printers. Storage unit 608 may include, but is not limited to, magnetic disks, optical disks. The communication unit 609 allows the device 600 to exchange information/data with other devices via a computer network, such as the internet, and/or various telecommunications networks, and may include, but is not limited to, modems, network cards, infrared communication devices, wireless communication transceivers and/or chipsets, such as bluetooth (TM) devices, 802.11 devices, wiFi devices, wiMax devices, cellular communication devices, and/or the like.
The computing unit 601 may be a variety of general and/or special purpose processing components having processing and computing capabilities. Some examples of computing unit 601 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various specialized Artificial Intelligence (AI) computing chips, various computing units running machine learning model algorithms, a Digital Signal Processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 601 performs the respective methods and processes described above, such as a chip authentication method. For example, in some embodiments, the chip authentication method may be implemented as a computer software program tangibly embodied on a machine-readable medium, such as storage unit 608. In some embodiments, part or all of the computer program may be loaded and/or installed onto the device 600 via the ROM 602 and/or the communication unit 609. When a computer program is loaded into RAM 603 and executed by computing unit 601, one or more steps of the chip authentication method described above may be performed. Alternatively, in other embodiments, the computing unit 601 may be configured to perform the chip authentication method by any other suitable means (e.g., by means of firmware).
Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuit systems, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), systems On Chip (SOCs), complex Programmable Logic Devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs, the one or more computer programs may be executed and/or interpreted on a programmable system including at least one programmable processor, which may be a special purpose or general-purpose programmable processor, that may receive data and instructions from, and transmit data and instructions to, a storage system, at least one input device, and at least one output device.
Program code for carrying out methods of the present disclosure may be written in any combination of one or more programming languages. These program code may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus such that the program code, when executed by the processor or controller, causes the functions/operations specified in the flowchart and/or block diagram to be implemented. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.
In the context of this disclosure, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. The machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and pointing device (e.g., a mouse or trackball) by which a user can provide input to the computer. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic input, speech input, or tactile input.
The systems and techniques described here can be implemented in a computing system that includes a background component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such background, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), the internet, and blockchain networks.
The computer system may include a client and a server. The client and server are typically remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server may be a cloud server, a server of a distributed system, or a server incorporating a blockchain.
It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps recited in the present disclosure may be performed in parallel, sequentially or in a different order, provided that the desired results of the disclosed aspects are achieved, and are not limited herein.
Although embodiments or examples of the present disclosure have been described with reference to the accompanying drawings, it is to be understood that the foregoing methods, systems, and apparatus are merely exemplary embodiments or examples, and that the scope of the present invention is not limited by these embodiments or examples but only by the claims following the grant and their equivalents. Various elements of the embodiments or examples may be omitted or replaced with equivalent elements thereof. Furthermore, the steps may be performed in a different order than described in the present disclosure. Further, various elements of the embodiments or examples may be combined in various ways. It is important that as technology evolves, many of the elements described herein may be replaced by equivalent elements that appear after the disclosure.
Claims (16)
1. A chip authentication method comprising:
acquiring an instruction set and a target verification option;
Acquiring target constraint information based on the target verification option, wherein the target constraint information comprises target constraint conditions and types of the target constraint conditions;
based on the type of the target constraint condition, a template of a random configuration instruction corresponding to the target constraint information is obtained;
generating an executable random configuration instruction based on the template of the random configuration instruction and the target constraint condition;
executing the random configuration instruction to randomly determine at least one target instruction from the instruction set, wherein the at least one target instruction meets the target constraint;
executing the at least one target instruction by using the chip to be verified; and
and determining a verification result aiming at the chip to be verified based on the execution result of the at least one target instruction.
2. The method of claim 1, wherein the obtaining target constraint information based on the target verification option comprises:
and obtaining target constraint information corresponding to the target verification options from a constraint information base, wherein at least one verification option and constraint information corresponding to each verification option in the at least one verification option are stored in the constraint information base.
3. The method of claim 2, wherein the constraint information base includes a plurality of sub-constraint information bases, each of the plurality of sub-constraint information bases storing constraint information of a corresponding constraint condition of a same type, the method further comprising:
acquiring types of constraint conditions corresponding to the multiple sub constraint information bases respectively;
the type of the target constraint is determined based on the type of the constraint corresponding to a target sub-constraint library storing the target constraint.
4. A method as claimed in claim 3, wherein at least one of the plurality of sub-constraint information bases is a template class.
5. The method of any of claims 1-4, wherein the type of target constraint comprises at least one of:
a condition for constraining a type of the at least one target instruction, a condition for constraining a type of an operand of the at least one target instruction, and a condition for constraining a size of an operand of the at least one target instruction.
6. The method of any of claims 1-5, wherein the template of the random configuration instruction comprises an empty queue, the generating executable random configuration instructions based on the template of random configuration instructions and the target constraint comprising:
And storing the target constraint condition into the empty queue to obtain an executable random configuration instruction.
7. A chip authentication apparatus comprising:
a first acquisition unit configured to acquire an instruction set and a target authentication option;
a second acquisition unit configured to acquire target constraint information including a target constraint condition and a type of the target constraint condition based on the target verification option;
a third obtaining unit configured to obtain a template of a random configuration instruction corresponding to the target constraint information based on a type of the target constraint condition;
a generation unit configured to generate an executable random configuration instruction based on a template of the random configuration instruction and the target constraint condition;
a first determining unit configured to execute the random configuration instruction to randomly determine at least one target instruction from the instruction set, wherein the at least one target instruction meets the target constraint;
an execution unit configured to execute the at least one target instruction using the chip to be verified; and
and a second determining unit configured to determine a verification result for the chip to be verified based on an execution result of the at least one target instruction.
8. The apparatus of claim 7, wherein the second acquisition unit is configured to:
and obtaining target constraint information corresponding to the target verification options from a constraint information base, wherein at least one verification option and constraint information corresponding to each verification option in the at least one verification option are stored in the constraint information base.
9. The apparatus of claim 8, wherein the constraint information base comprises a plurality of sub-constraint information bases, each of the plurality of sub-constraint information bases storing constraint information of a corresponding constraint condition of a same type, the method further comprising:
acquiring types of constraint conditions corresponding to the multiple sub constraint information bases respectively;
the type of the target constraint is determined based on the type of the constraint corresponding to a target sub-constraint library storing the target constraint.
10. The apparatus of claim 9, wherein at least one of the plurality of sub-constraint information bases is a template class.
11. The apparatus of any of claims 7-10, wherein the type of target constraint comprises at least one of:
A condition for constraining a type of the at least one target instruction, a condition for constraining a type of an operand of the at least one target instruction, and a condition for constraining a size of an operand of the at least one target instruction.
12. The apparatus of any of claims 7-11, wherein the template of the random configuration instruction comprises an empty queue, the generating unit configured to:
and storing the target constraint condition into the empty queue to obtain an executable random configuration instruction.
13. A chip comprising the apparatus of any one of claims 7-12.
14. An electronic device, comprising:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein the method comprises the steps of
The memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-6.
15. A non-transitory computer readable storage medium storing computer instructions for causing a computer to perform the method of any one of claims 1-6.
16. A computer program product comprising a computer program, wherein the computer program, when executed by a processor, implements the method according to any of claims 1-6.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117034817A (en) * | 2023-10-10 | 2023-11-10 | 沐曦集成电路(上海)有限公司 | Method, electronic device and medium for automatically randomly generating verification data packet |
| CN117709294A (en) * | 2024-02-05 | 2024-03-15 | 英诺达(成都)电子科技有限公司 | Constraint verification method and device for integrated circuit, electronic equipment, medium and product |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117034817A (en) * | 2023-10-10 | 2023-11-10 | 沐曦集成电路(上海)有限公司 | Method, electronic device and medium for automatically randomly generating verification data packet |
| CN117034817B (en) * | 2023-10-10 | 2023-12-22 | 沐曦集成电路(上海)有限公司 | Method, electronic device and medium for automatically randomly generating verification data packet |
| CN117709294A (en) * | 2024-02-05 | 2024-03-15 | 英诺达(成都)电子科技有限公司 | Constraint verification method and device for integrated circuit, electronic equipment, medium and product |
| CN117709294B (en) * | 2024-02-05 | 2024-04-30 | 英诺达(成都)电子科技有限公司 | Constraint verification method and device for integrated circuit, electronic equipment, medium and product |
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