CN203313319U - Display system - Google Patents
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- CN203313319U CN203313319U CN2013203332705U CN201320333270U CN203313319U CN 203313319 U CN203313319 U CN 203313319U CN 2013203332705 U CN2013203332705 U CN 2013203332705U CN 201320333270 U CN201320333270 U CN 201320333270U CN 203313319 U CN203313319 U CN 203313319U
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Abstract
The utility model is applicable to the video field, and especially relates to a display system. A first video signal input module or a second video signal input module obtains video signals that a user wants to play, and a first video signal processing module or a second video signal processing module processes the video signals to enhance image and optimize image quality. A signal synthesizing module sends OSD state video signals to be displayed, generated by frame interpolation multiplier of OSD signal frame interpolation multiplier unit and video signals to be displayed, generated by frame interpolation multiplier of a video signal frame interpolation multiplier unit to a display module. The display module displays video signals that a user wants to play and a stationary OSD interface. In this way, video signals that a user wants to play are played normally while the stationary OSD interface is displayed for the user to use, thereby effectively preventing the OSD caption deformation, blurry screen, image distortion and edge fragmentation.
Description
Technical field
The utility model belongs to video field, relates in particular to a kind of display system.
Background technology
Video pictures mainly is comprised of two parts, and first is exactly the vision signal of itself, and second portion is exactly OSD(On-Screen Display, the screen menu type regulative mode) video clip; Along with the fast development of video playback, the appearance of the ultra high-definition videos such as especially various 3D OSD and 3D4K2K, regulate display screen by the OSD interface and paid attention to reach good display effect.
The user triggers the OSD triggering signal by the OSD trigger module, can show the OSD interface in display module, and the user can adjust by this OSD interface.For example: user's remote controller, to trigger the OSD triggering signal, there will be the OSD interface on television display screen, the user can adjust by this OSD interface.If when needing to play the video that comprises motion component, use the OSD interface, existing video signal processing module can be processed motion video and OSD video signal mixture together, simultaneously motion picture and OSD interface are taked to frame interpolation technology, thereby also can move in the OSD interface after processing.Therefore, if the user is when watching displaying video, the OSD interface there will be the situations such as the distortion of OSD captions, flower screen, imaging distortion, the broken sense in edge, and this situation is especially very obvious on super HD video.
The utility model content
The purpose of this utility model is to provide a kind of display system, aims to provide a kind of vision signal that will comprise play content and the vision signal at OSD interface and separates the display system of processing.
The utility model is achieved in that a kind of display system, and described display system comprises the first processing module, the second processing module, the first video signal input module, the second video signal input module, OSD trigger module and display module, it is characterized in that,
Described the first processing module comprises:
The output of described the first video signal input module of video input termination, the vision signal that full HD vision signal or resolution are less than to full HD vision signal carry out the first video signal processing unit that figure image intensifying and image quality are optimized;
Trigger the output that receives the described OSD trigger module of termination, when the OSD triggering signal that receives the OSD trigger module, obtain the OSD state parameter to generate OSD state vision signal, and described OSD state vision signal is sent to the osd signal processing unit of osd signal interleave frequency multiplication unit;
Described the second processing module comprises:
The output of described the second video signal input module of video input termination, the first difference video end, the second difference video end, the first differential clocks end and the second differential clocks end connect respectively the first difference video end of described the first video signal processing unit, the second difference video end, the first differential clocks end and the second differential clocks end, receive the second vision signal of described the second video signal input module output, and be that full HD vision signal or resolution are forwarded to described the first video signal processing unit by described the second vision signal while being less than the vision signal of full HD vision signal in described the second vision signal, and described the second video signal processing unit that described the second vision signal is carried out figure image intensifying and image quality optimization when described the second vision signal is the ultra high-definition vision signal,
The video output terminals of described the second video signal processing unit of input termination, carry out the interleave frequency multiplication to the vision signal after figure image intensifying and image quality optimization, generates vision signal to be shown to be sent to the vision signal interleave frequency multiplication unit of signal merge cells;
The first difference video end, the second difference video end, the first differential clocks end and the second differential clocks end connect respectively the first difference video end, the second difference video end, the first differential clocks end and the second differential clocks end of described osd signal processing unit, described OSD state vision signal is carried out to the interleave frequency multiplication, generate OSD state vision signal to be shown to be sent to the described osd signal interleave frequency multiplication unit of described signal merge cells;
The output of the described vision signal interleave frequency multiplication of video input termination unit, the output of the OSD input described osd signal interleave frequency multiplication of termination unit, the input of the described display module of output termination, described OSD state vision signal to be shown and described vision signal to be shown are merged, generate the described signal merge cells that display video signal shows to be sent to display module.
Further, described display system also comprises:
The state parameter input of the described osd signal processing unit of I/O termination, the cache module of storage OSD state parameter.
Further, described the first video signal processing unit adopts vision signal process chip U2;
The video input pin of described vision signal process chip U2 is the video inputs of described the first video signal processing unit, and the first difference video pin of described vision signal process chip U2, the second difference video pin, the first differential clocks pin and the second differential clocks pin are respectively the first difference video end, the second difference video end, the first differential clocks end and the second differential clocks end of described the first video signal processing unit.
Further, described the second video signal processing unit adopts vision signal process chip U3;
The first difference video pin of described vision signal process chip U3, the second difference video pin, the first differential clocks pin and the second differential clocks pin are respectively the first difference video end, the second difference video end, the first differential clocks end and the second differential clocks end of described the second video signal processing unit, the video input pin of described vision signal process chip U3 is the video inputs of described the second video signal processing unit, and the video output pin of described vision signal process chip U3 is the video output terminals of described the second video signal processing unit.
Further, described osd signal processing unit adopts osd signal process chip U1;
The triggering of described osd signal process chip U1 receives pin and the state parameter pin is respectively triggering receiving terminal and state parameter input, and the first difference video pin of described osd signal process chip U1, the second difference video pin, the first differential clocks pin and the second differential clocks pin are respectively the first difference video end, the second difference video end, the first differential clocks end and the second differential clocks end.
Further, described osd signal interleave frequency multiplication unit adopts osd signal interleave frequency multiplication chip U4;
The first difference video pin of described osd signal interleave frequency multiplication chip U4, the second difference video pin, the first differential clocks pin and the second differential clocks pin are respectively the first difference video end, the second difference video end, the first differential clocks end and the second differential clocks end of described osd signal interleave frequency multiplication unit, and the output pin of described osd signal interleave frequency multiplication chip U4 is the output of described osd signal interleave frequency multiplication unit.
Further, the first difference video end of described the first video signal processing unit, the second difference video end, the first differential clocks end and the second differential clocks end are connected respectively after a build-out resistor and are connect the first difference video end of described the second video signal processing unit, the second difference video end, the first differential clocks end and the second differential clocks end, the first difference video end of described osd signal processing unit, the second difference video end, the first differential clocks end and the second differential clocks end are connected respectively after a build-out resistor and are connect the first difference video end of described osd signal interleave frequency multiplication unit, the second difference video end, the first differential clocks end and the second differential clocks end.
In the utility model, the first video signal input module or the second video signal input module are obtained the user and are wanted the vision signal of playing, the first video signal processing module is carried out figure image intensifying and image quality optimization to the vision signal of full HD and following resolution, and the second video signal processing module is carried out figure image intensifying and image quality optimization to the ultra high-definition vision signal; Osd signal interleave frequency multiplication unit carries out the interleave frequency multiplication to OSD state vision signal, generates OSD state vision signal to be shown; The vision signal of vision signal interleave frequency multiplication unit after to figure image intensifying and image quality optimization carried out the interleave frequency multiplication, generates vision signal to be shown; Signal synthesizing module merges to generate display video signal by OSD state vision signal to be shown and vision signal to be shown, and to be sent to display module, display module shows that the user wants the vision signal of playing and static OSD interface; Thereby, the utility model embodiment is when the normal play user wants the video of playing, show static OSD interface so that the user uses, effectively avoided the OSD interface generation of the situations such as the distortion of OSD captions, flower screen, imaging distortion, the broken sense in edge to occur.
The accompanying drawing explanation
Fig. 1 is the circuit structure diagram of the display system that provides of the utility model embodiment;
Fig. 2 is the physical circuit figure of the display system that provides of the utility model embodiment;
Fig. 3 is the another kind of physical circuit figure of the display system that provides of the utility model embodiment.
Embodiment
In order to make the purpose of this utility model, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the utility model is further elaborated.Should be appreciated that specific embodiment described herein is only in order to explain the utility model, and be not used in restriction the utility model.
Fig. 1 shows the structure of the display system that the utility model embodiment provides, and for convenience of explanation, only shows the part relevant to the utility model embodiment, and details are as follows.
A kind of display system, described display system comprise the first processing module 1, the second processing module 2, the first video signal input module 3, the second video signal input module 7, OSD trigger module 4 and display module 6,
Described the first processing module 1 comprises:
The output of described the first video signal input module 3 of video input termination, the vision signal that full HD vision signal or resolution are less than to full HD vision signal carry out the first video signal processing unit 11 that figure image intensifying and image quality are optimized;
Trigger the output that receives the described OSD trigger module 4 of termination, when the OSD triggering signal that receives OSD trigger module 4, obtain the OSD state parameter to generate OSD state vision signal, and described OSD state vision signal is sent to the osd signal processing unit 12 of osd signal interleave frequency multiplication unit 22;
Described the second processing module 2 comprises:
The output of described the second video signal input module 7 of video input termination, the first difference video end, the second difference video end, the first differential clocks end and the second differential clocks end connect respectively the first difference video end of described the first video signal processing unit 11, the second difference video end, the first differential clocks end and the second differential clocks end, receive the second vision signal of described the second video signal input module 7 outputs, and be that full HD vision signal or resolution are forwarded to described the first video signal processing unit 11 by described the second vision signal while being less than the vision signal of full HD vision signal in described the second vision signal, and described the second video signal processing unit 21 that described the second vision signal is carried out figure image intensifying and image quality optimization when described the second vision signal is the ultra high-definition vision signal,
The video output terminals of described the second video signal processing unit 21 of input termination, vision signal after figure image intensifying and image quality optimization is carried out to the interleave frequency multiplication, generate vision signal to be shown to be sent to the vision signal interleave frequency multiplication unit 23 of signal merge cells 24;
The first difference video end, the second difference video end, the first differential clocks end and the second differential clocks end connect respectively the first difference video end, the second difference video end, the first differential clocks end and the second differential clocks end of described osd signal processing unit 12, described OSD state vision signal is carried out to the interleave frequency multiplication, generate OSD state vision signal to be shown to be sent to the described osd signal interleave frequency multiplication unit 22 of described signal merge cells 24;
The output of the described vision signal interleave frequency multiplication of video input termination unit 23, the output of the OSD input described osd signal interleave frequency multiplication of termination unit 22, the input of the described display module 6 of output termination, described OSD state vision signal to be shown and described vision signal to be shown are merged, generate the described signal merge cells 24 that display video signal shows to be sent to display module 6.
It should be noted that, described the first video signal processing unit 11 not only receives the first vision signal of the first video signal input module 3 outputs, but also receives the full HD vision signal of the second video signal input module 7 forwardings or the vision signal that resolution is less than full HD vision signal.
It should be noted that, described the first video signal input module 3 and described the second video signal input module 7 all can be USB interface, full HD video interface, HDMI (High Definition Multimedia Interface) (High Definition Multimedia Interface, HDMI) etc. the video interface of receiving video signals, do not do restriction at this.Therefore, described the first vision signal and described the second vision signal include vision signal and the ultra high-definition vision signal of full HD and following resolution, and wherein, described ultra high-definition signal is the vision signal of full HD above resolution.
It should be noted that, the vision signal that described full HD vision signal and resolution are less than full HD vision signal comprises that the resolution such as vision signal of 4K1K 30HZ are equal to or less than full HD vision signal; Described ultra high-definition vision signal comprises that the resolution such as 4K2K 30HZ are higher than full HD vision signal.
It should be noted that, described OSD trigger module 4 can be: the existing OSD triggers such as remote controller, button controller, at this, do not do restriction.
As another embodiment of the utility model, the function comprised of described the first processing module 1 and described the second processing module 2 all adopts a programmable logic device to realize.
As another embodiment of the utility model, between described the first video signal processing unit 11 and the second video signal processing unit 21, adopt the existing video bus such as LVDS bus, HS LVDS bus to connect, at this, do not do restriction.Between described osd signal processing unit 12 and described osd signal interleave frequency multiplication unit 22, adopt the existing video bus such as LVDS bus, HS LVDS bus to connect, do not do restriction at this.
As another embodiment of the utility model, between the input of the output of described signal merge cells 24 and described display module 6, adopt V-BY-ONE bus and corresponding interface to connect.
As the utility model one embodiment, described display system also comprises:
The state parameter input of the described osd signal processing unit 12 of I/O termination, the cache module 5 of storage OSD state parameter.
It should be noted that, after when osd signal processing unit 12, receiving the OSD triggering signal of OSD trigger module 4, to described cache module 5, send the request of obtaining of OSD state parameter; Cache module 5 is received this by the I/O termination and is obtained and ask and respond, and up-to-date OSD state parameter is fed back to osd signal processing unit 12 by the I/O end.
Fig. 2 shows the physical circuit of the display system that the utility model embodiment provides, and for convenience of explanation, only shows the part relevant to the utility model embodiment, and details are as follows.
As the utility model one embodiment, described the first video signal processing unit 11 adopts vision signal process chip U2;
The video input pin D2 of described vision signal process chip U2 is the video inputs of described the first video signal processing unit 11, and the first difference video pin CP2+ of described vision signal process chip U2, the second difference video pin CP2-, the first differential clocks pin KP2+ and the second differential clocks pin KP2-are respectively the first difference video end, the second difference video end, the first differential clocks end and the second differential clocks end of described the first video signal processing unit 11.
More optimizedly, described the second video signal processing unit 21 adopts vision signal process chip U3;
The first difference video pin CP3+ of described vision signal process chip U3, the second difference video pin CP3-, the first differential clocks pin KP3+ and the second differential clocks pin KP3-are respectively the first difference video end of described the second video signal processing unit 21, the second difference video end, the first differential clocks end and the second differential clocks end, the video input pin D3 of described vision signal process chip U3 is the video inputs of described the second video signal processing unit 21, the video output pin VO3 of described vision signal process chip U3 is the video output terminals of described the second video signal processing unit 21.
As the utility model one embodiment, described osd signal processing unit 12 adopts osd signal process chip U1;
The triggering of described osd signal process chip U1 receives pin OS1 and state parameter pin D1 is respectively triggering receiving terminal and state parameter input, and the first difference video pin CP1+ of described osd signal process chip U1, the second difference video pin CP1-, the first differential clocks pin KP1+ and the second differential clocks pin KP1-are respectively the first difference video end, the second difference video end, the first differential clocks end and the second differential clocks end.
More optimizedly, described osd signal interleave frequency multiplication unit 22 adopts osd signal interleave frequency multiplication chip U4;
The first difference video pin CP4+ of described osd signal interleave frequency multiplication chip U4, the second difference video pin CP4-, the first differential clocks pin KP4+ and the second differential clocks pin KP4-are respectively the first difference video end, the second difference video end, the first differential clocks end and the second differential clocks end of described osd signal interleave frequency multiplication unit 22, and the output pin VO4 of described osd signal interleave frequency multiplication chip U4 is the output of described osd signal interleave frequency multiplication unit 22.
Fig. 3 shows a kind of physical circuit of the display system that the utility model embodiment provides, and for convenience of explanation, only shows the part relevant to the utility model embodiment, and details are as follows.
As the utility model one embodiment, the first difference video end of described the first video signal processing unit 11, the second difference video end, the first differential clocks end and the second differential clocks end build-out resistor (the build-out resistor R1 that connects respectively, build-out resistor R2, build-out resistor R3, build-out resistor R4) after, connect the first difference video end of described the second video signal processing unit 21, the second difference video end, the first differential clocks end and the second differential clocks end, the first difference video end of described osd signal processing unit 12, the second difference video end, the first differential clocks end and the second differential clocks end build-out resistor (the build-out resistor R5 that connects respectively, build-out resistor R6, build-out resistor R7, build-out resistor R8) after, connect the first difference video end of described osd signal interleave frequency multiplication unit 22, the second difference video end, the first differential clocks end and the second differential clocks end.
In order to explain better the utility model, first video signal processing unit 11 of take adopts vision signal process chip U2, the second video signal processing unit 21 to adopt vision signal process chip U3, osd signal processing unit 12 to adopt osd signal process chip U1 and osd signal interleave frequency multiplication unit 22 to adopt osd signal interleave frequency multiplication chip U4 to be example, and the operation principle of display system is described in conjunction with Fig. 2:
The first video signal input module 3 receives and comprises the vision signal that the user wants that play, full HD and following resolution by USB interface.After the video input pin D2 of vision signal process chip U2 receives the vision signal of this full HD following resolution, the vision signal of this full HD following resolution is carried out to figure image intensifying and image quality optimization process, and the vision signal after figure image intensifying and image quality optimization process is sent to vision signal process chip U3, at this moment, vision signal process chip U3 directly is sent to vision signal interleave frequency multiplication unit 23 by after figure image intensifying and image quality optimization process, vision signal full HD following resolution by video output pin VO3.
Perhaps, the second video signal input module 7 receives the user and wants the vision signal of playing, and this vision signal comprises vision signal and the ultra high-definition vision signal of full HD and following resolution; If this vision signal is the vision signal of full HD and following resolution, vision signal process chip U2 this is full HD and vision signal following resolution is forwarded to vision signal process chip U2, by vision signal process chip U2, the vision signal of this full HD following resolution is carried out to figure image intensifying and image quality optimization process; If this vision signal is the ultra high-definition vision signal, vision signal process chip U3 carries out figure image intensifying and image quality optimization process to this ultra high-definition vision signal, and the vision signal after figure image intensifying and image quality optimization process is sent to vision signal interleave frequency multiplication unit 23 by video output pin VO3.
Preferably, the first difference video pin CP2+, the second difference video pin CP2-of the first difference video pin CP3+, the second difference video pin CP3-by vision signal process chip U3 and the vision signal process chip U2 of coupling, complete vision signal or the transmission (receive/send) of the vision signal after figure image intensifying and image quality optimization process between vision signal process chip U3 and vision signal process chip U2 of full HD and following resolution; Transmit clock signal between the first differential clocks pin KP2+ of the first differential clocks pin KP3+, the second differential clocks pin KP3-of vision signal process chip U3 and the vision signal process chip U2 of coupling, the second differential clocks pin KP2-, synchronously receive/send the vision signal of vision signal process chip U3 to guarantee vision signal process chip U2.
When needs called the OSD interface, OSD trigger module 4 can receive user's operation, triggered the OSD triggering signal; After the triggering reception pin OS1 of osd signal process chip U1 receives this OSD triggering signal, by state parameter pin D1, send the request of obtaining of OSD state parameters to cache module 5; This obtains request cache module 5 responses, and up-to-date OSD state parameter is fed back to the triggering reception pin D1 of osd signal process chip U1; Osd signal process chip U1, according to this OSD state parameter, generates OSD state vision signal.Osd signal interleave frequency multiplication chip U4 receives the first difference video pin CP1+ of osd signal process chip U1, the OSD state vision signal that the second difference video pin CP1-sends out by the first difference video pin CP4+, the second difference video pin CP4-; Osd signal interleave frequency multiplication chip U4 receives the first differential clocks pin KP1+ of osd signal process chip U1, the OSD state timer signal that the second differential clocks pin KP1-sends out by the first differential clocks pin KP4+, the second differential clocks pin KP4-, synchronously receives to guarantee osd signal interleave frequency multiplication chip U4 the OSD state vision signal that osd signal process chip U1 sends.
Vision signal after the figure image intensifying of 23 pairs of vision signal interleave frequency multiplication unit and image quality optimization is carried out the interleave frequency multiplication, generates vision signal to be shown.The described OSD state vision signal in 22 pairs of osd signal interleave frequency multiplication unit is carried out the interleave frequency multiplication, generates OSD state vision signal to be shown.More optimizedly, vision signal interleave frequency multiplication unit 23 adopts identical interleave frequency multiplication mode to process vision signal with osd signal interleave frequency multiplication unit 22.
Signal merge cells 24 merges vision signal to be shown and OSD state vision signal to be shown, generates display video signal to be sent to display module 6; Display module 6 is play the user according to display video signal and is wanted the video of playing, and shows simultaneously the OSD interface.
In the utility model embodiment, the first video signal input module or the second video signal input module are obtained the user and are wanted the vision signal of playing; If the vision signal that vision signal process chip U3 receives is the vision signal that full HD vision signal and resolution are less than full HD vision signal, this vision signal is forwarded to vision signal process chip U2; Vision signal process chip U2 carries out figure image intensifying and image quality optimization to the vision signal of full HD and following resolution, and vision signal process chip U3 carries out figure image intensifying and image quality optimization to the ultra high-definition vision signal; Vision signal process chip U3 is sent to vision signal interleave frequency multiplication unit by the vision signal by figure image intensifying and image quality optimization process by video output pin VO3; Osd signal interleave frequency multiplication unit is sent to described signal merge cells by the OSD state vision signal to be shown that the interleave frequency multiplication generates; Vision signal interleave frequency multiplication unit is sent to described signal merge cells by the vision signal to be shown that the interleave frequency multiplication generates; Signal synthesizing module merges OSD state vision signal to be shown and vision signal to be shown, is sent to display module after the generation display video signal, and display module shows that the user wants the vision signal of playing and static OSD interface; Thereby, the utility model embodiment is when the normal play user wants the video of playing, show static OSD interface so that the user uses, effectively avoided the OSD interface generation of the situations such as the distortion of OSD captions, flower screen, imaging distortion, the broken sense in edge to occur.
The foregoing is only preferred embodiment of the present utility model; not in order to limit the utility model; all any modifications of doing within spirit of the present utility model and principle, be equal to and replace and improvement etc., within all should being included in protection range of the present utility model.
Claims (7)
1. display system, described display system comprises the first processing module, the second processing module, the first video signal input module, the second video signal input module, OSD trigger module and display module, it is characterized in that,
Described the first processing module comprises:
The output of described the first video signal input module of video input termination, the vision signal that full HD vision signal or resolution are less than to full HD vision signal carry out the first video signal processing unit that figure image intensifying and image quality are optimized;
Trigger the output that receives the described OSD trigger module of termination, when the OSD triggering signal that receives the OSD trigger module, obtain the OSD state parameter to generate OSD state vision signal, and described OSD state vision signal is sent to the osd signal processing unit of osd signal interleave frequency multiplication unit;
Described the second processing module comprises:
The output of described the second video signal input module of video input termination, the first difference video end, the second difference video end, the first differential clocks end and the second differential clocks end connect respectively the first difference video end of described the first video signal processing unit, the second difference video end, the first differential clocks end and the second differential clocks end, receive the second vision signal of described the second video signal input module output, and be that full HD vision signal or resolution are forwarded to described the first video signal processing unit by described the second vision signal while being less than the vision signal of full HD vision signal in described the second vision signal, and described the second video signal processing unit that described the second vision signal is carried out figure image intensifying and image quality optimization when described the second vision signal is the ultra high-definition vision signal,
The video output terminals of described the second video signal processing unit of input termination, carry out the interleave frequency multiplication to the vision signal after figure image intensifying and image quality optimization, generates vision signal to be shown to be sent to the vision signal interleave frequency multiplication unit of signal merge cells;
The first difference video end, the second difference video end, the first differential clocks end and the second differential clocks end connect respectively the first difference video end, the second difference video end, the first differential clocks end and the second differential clocks end of described osd signal processing unit, described OSD state vision signal is carried out to the interleave frequency multiplication, generate OSD state vision signal to be shown to be sent to the described osd signal interleave frequency multiplication unit of described signal merge cells;
The output of the described vision signal interleave frequency multiplication of video input termination unit, the output of the OSD input described osd signal interleave frequency multiplication of termination unit, the input of the described display module of output termination, described OSD state vision signal to be shown and described vision signal to be shown are merged, generate the described signal merge cells that display video signal shows to be sent to display module.
2. display system as claimed in claim 1, is characterized in that, described display system also comprises:
The state parameter input of the described osd signal processing unit of I/O termination, the cache module of storage OSD state parameter.
3. display system as claimed in claim 1, is characterized in that, described the first video signal processing unit adopts vision signal process chip U2;
The video input pin of described vision signal process chip U2 is the video inputs of described the first video signal processing unit, and the first difference video pin of described vision signal process chip U2, the second difference video pin, the first differential clocks pin and the second differential clocks pin are respectively the first difference video end, the second difference video end, the first differential clocks end and the second differential clocks end of described the first video signal processing unit.
4. display system as claimed in claim 3, is characterized in that, described the second video signal processing unit adopts vision signal process chip U3;
The first difference video pin of described vision signal process chip U3, the second difference video pin, the first differential clocks pin and the second differential clocks pin are respectively the first difference video end, the second difference video end, the first differential clocks end and the second differential clocks end of described the second video signal processing unit, the video input pin of described vision signal process chip U3 is the video inputs of described the second video signal processing unit, and the video output pin of described vision signal process chip U3 is the video output terminals of described the second video signal processing unit.
5. display system as claimed in claim 2, is characterized in that, described osd signal processing unit adopts osd signal process chip U1;
The triggering of described osd signal process chip U1 receives pin and the state parameter pin is respectively triggering receiving terminal and state parameter input, and the first difference video pin of described osd signal process chip U1, the second difference video pin, the first differential clocks pin and the second differential clocks pin are respectively the first difference video end, the second difference video end, the first differential clocks end and the second differential clocks end.
6. display system as claimed in claim 5, is characterized in that, described osd signal interleave frequency multiplication unit adopts osd signal interleave frequency multiplication chip U4;
The first difference video pin of described osd signal interleave frequency multiplication chip U4, the second difference video pin, the first differential clocks pin and the second differential clocks pin are respectively the first difference video end, the second difference video end, the first differential clocks end and the second differential clocks end of described osd signal interleave frequency multiplication unit, and the output pin of described osd signal interleave frequency multiplication chip U4 is the output of described osd signal interleave frequency multiplication unit.
7. display system as claimed in claim 1, it is characterized in that, the first difference video end of described the first video signal processing unit, the second difference video end, the first differential clocks end and the second differential clocks end are connected respectively after a build-out resistor and are connect the first difference video end of described the second video signal processing unit, the second difference video end, the first differential clocks end and the second differential clocks end, the first difference video end of described osd signal processing unit, the second difference video end, the first differential clocks end and the second differential clocks end are connected respectively after a build-out resistor and are connect the first difference video end of described osd signal interleave frequency multiplication unit, the second difference video end, the first differential clocks end and the second differential clocks end.
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| CN103702060A (en) * | 2013-12-31 | 2014-04-02 | 京东方科技集团股份有限公司 | Super-high definition display device and video signal conversion method |
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