CN100578242C - Multifunctional electric cable failure detector - Google Patents

Abstract

The present invention discloses a multifunctional cable-fault detector which is characteristic of comprising of field programmable gate-array chip, field programmable gate-array allocated storage chip, serial communication interface circuit, emitting driving circuit, multi-point relay circuit, signal conditioning shaping circuit, high-speed comparator circuit, A/D conversion circuit, numerical control precision potentiometer, LCD display circuit, LED pilot lamp circuit and key-press circuit. The present invention can detect length of twisted-pair, super-long of twisted-pair, connectivity of twisted-pair (including fault such as open circuit, short circuit, inversed joint, error meeting, super-long and so on), fault class (including open circuit and short circuit), fault point location orientation and multiple parameters such as return loss, can obtain technique parameters of twisted-pair and realize detection and orientation of fault point location, has merits of high precision, credible capability and portable capability.

Description

Multifunctional electric cable failure detector

Technical field

The present invention relates to a kind of multifunctional electric cable failure detector, belong to the cable testing equipment technical field.

Background technology

Along with the fast development of information networking, network has entered the every aspect of life, becomes one of indispensable key element of people.China's network development is rapid, and by the end of on Dec 31st, 2007, network user's total number of persons of China reached 2.1 hundred million people, is only second to the U.S. with 5,000,000 people's difference, occupies the second place of the world.But in the time of the network high-speed development, because the network failure that the transmission cable fault causes also frequently takes place, according to statistics, approximately the network failure of 50%-70% is relevant with cable, the economic loss that causes is very huge, the quality of visible cable itself and the normal operation that installation quality all directly influences network.Therefore, the Network Transmission cable in the comprehensive wiring system is tested had important practical significance.

In numerous transmission cables, twisted-pair cable has that price is low, strong interference immunity, can transmit multiple (voice, data, image and CATV (Community Antenna Television simultaneously, CATV (cable television))) advantage such as multiple signals is widely used in LAN (Local Area Network) and the intelligent building.Since most of network cables be arranged in underground or building wall in, caused inconvenience for the maintenance of network cable, traditional networking cable fault detection method (as playback method, leak detection etc.) need all be taken out the cable that breaks down in underground or building wall, this not only expends great amount of manpower and material resources, and safeguards and maintenance all requires a great deal of time and cost.In addition, the traditional detection method mainly relies on engineering technical personnel's experience, and accuracy and precision all are difficult to guarantee.

The method of testing that present most of cable tester adopts is the time domain pulse reflection method, this method is based on the characteristic impedance meeting generation significant change at Method of Cable Trouble Point place, pulse signal reflects at the impedance place of not matching, and the different principle of pulse-echo coefficient of different faults type.Pulse reflection method is compared with conventional test methodologies has applied widely, easy, the precision advantages of higher of test.But pulse reflection method paired pulses frequency and pulsewidth have higher requirements.The transmission speed of pulse electrical signal in cable is very high, is about 200m/ μ s (friction speed according to the cable insulation medium is slightly different), and be therefore very high to the requirement of signal acquisition process speed, needs to adopt special high-speed signal acquisition and disposal route.Exomonental in addition pulsewidth also has considerable influence to measuring accuracy, and pulsewidth is big more when short distance is measured, and is easy to generate the phenomenon of transponder pulse and reflected impulse aliasing, causes the test blind area, and its measuring resolution is also more little.Otherwise the signal pulsewidth is more little, though can effectively improve measuring accuracy, its high fdrequency component is higher, and energy that signal has relatively more little when loss and the decay of signal during in cable transmission is also bigger, causes measuring distance shorter.In the practical application, general processor or digital integrated chip are difficult to produce the high-frequency impulse that satisfies test request, also are difficult to reach so high response speed, consequently cause measuring accuracy not high, the defective that the blind area is bigger.

Network cable tester great majority in the market are that foreign vendor is (as U.S.'s fluke, Agilent; Britain EDG etc.) product, that its product possesses skills is comparatively ripe, multiple functional, dependable performance, measuring accuracy are higher, the less advantage such as be easy to carry of volume, but great majority belong to medium and high-grade products, its price higher (usually between 20,000-200,000 yuan), and the instrument maintenance cost is very high; Though the network tester quantity that domestic manufacturers produce is many, kind is single, and product belongs to low grade products mostly, though it is cheap, but function singleness (being confined to cable connectivity mostly detects), precision is compared relatively poor than external product, and volume is more easy to carry and use.These unfavorable factors have brought inconvenience for China's network comprehensive lining, also are unfavorable for the construction and the maintenance of China sub-district, urban network, therefore are necessary to develop a kind of Multifunction cable tester, to satisfy the needs of practical application.

Summary of the invention

The object of the present invention is to provide a kind of novel multifunctional electric cable failure detector, whether the length, twisted-pair feeder that this tester can be tested twisted-pair feeder multiple parameters such as the connectedness of overlength, twisted-pair feeder (comprising open circuit, short circuit, reversal connection, wrong to faults such as, overlength), fault type (comprising short circuit, open circuit), position of failure point location and return loss, can quick and precisely obtain the technical parameter of twisted-pair feeder and realize that abort situation detects and the location, have measuring accuracy height, dependable performance, portable characteristics.

The present invention adopts following technical scheme:

A kind of multifunctional network electric cable failure detector, it is characterized in that this tester is by field programmable gate array (Field-Programmable GateArray, FPGA) chip, field programmable gate array configuration store chip, serial communication interface (Universal Asynchronous Receiver/Transmitter, UART) circuit, the emission driving circuit, the multicircuit relay circuit, the signal condition shaping circuit, the high-speed comparator circuit, modulus (AD) change-over circuit, the numerically-controlled precise potentiometer, LCD (Liquid Crystal Display, LCD) display circuit, light emitting diode (Light Emitting Diode, LED) indicator light circuit and key circuit are formed, wherein: field programmable gate array chip is the core devices of whole tester, is controlling the work of whole tester and the processing computing of test data; Field programmable gate array configuration store chip is that its boot is downloaded after programmable gate array chip powers at the scene; Serial communication interface circuit be tester with host computer between the interface of communicating by letter, be used to receive the control command of host computer and realize uploading of test data; The pulse signal that the emission driving circuit is used for that field programmable gate array chip is produced amplifies satisfying test request, and this amplified pulse signal is delivered to the multicircuit relay circuit; The multicircuit relay circuit is used to control the switching between multichannel network cable to be measured; The signal condition shaping circuit will amplify shaping and be met the reflected signal that signals collecting requires from the signal of multicircuit relay circuit; The numerically-controlled precise potentiometer is controlled by described field programmable gate array chip, for high-speed comparator provides reference voltage signal; The high-speed comparator circuit is used for catching, gathers described reflected signal and compares with described reference voltage signal, exports a compare result signal and gives described field programmable gate array chip; The reference voltage signal that analog to digital conversion circuit is used to gather the numerically-controlled precise potentiometer and provides is passed to the field programmable gate array chip processing; Liquid crystal display displays circuit, light emitting diode lamp circuit and key circuit are connected with described field programmable gate array chip, the Man Machine Interface of composition system, be used to show test data, realize that selection function and parameter are provided with function, this multifunctional electric cable failure detector is connected with network cable to be measured by the RJ45 interface.

Wherein, the internal circuit of described field programmable gate array chip is by the flush bonding processor kernel, the liquid crystal display displays control circuit, the light emitting diode lamp control circuit, the serial communication controlling circuit, the keyboard decoding circuit, control relay circuit, analog-digital conversion control circuit, inner embedded phase-locked loop circuit (PLL), pulse produces control circuit, d type flip flop, high-speed counter, data latches and digital potentiometer control circuit are formed, wherein: the flush bonding processor kernel is the maincenter of system, all internal circuits are write by the ieee standard hardware description language, the flush bonding processor kernel is the core of field programmable gate array chip, be responsible for the processing computing of inner each several part circuit working of control field programmable gate array chip and test data, and operation result is delivered to the liquid crystal display displays control circuit; The liquid crystal display displays control circuit is responsible for the data that receive are delivered to outside liquid crystal display displays; The light emitting diode lamp control circuit is used to control the flicker of external light-emitting when continuity testing; The serial communication controlling circuit provides control signal and clock signal for field programmable gate array chip with communicating by letter of host computer; The keyboard decoding circuit is responsible for the input information decoding to external keyboard; Control relay circuit is controlled the closure of outside relay; Analog-digital conversion control circuit plays control analog-digital conversion circuit as described work and receives translation data; The digital potentiometer control circuit is controlled the variation of described numerically-controlled precise potentiometer resistance; Inner embedded phase-locked loop circuit produces control circuit with pulse on the one hand and connects to form pulse-generating circuit, and the opposing party's high-speed counter of praising to his face connects, for high-speed counter provides count pulse; Pulse produces single pulse signal and the output that control circuit will be converted to a known pulsewidth from the continuous high frequency clock signal of the embedded phase-locked loop circuit in inside; The input end of clock of d type flip flop is connected with the output terminal of described high-speed comparator circuit, and the output terminal of d type flip flop connects the Enable Pin of high-speed counter, and high-speed counter begins counting during high level, and high-speed counter stops counting during low level; The clock signal of the standard given frequency of the inner embedded phase-locked loop circuit output of the clock termination of high-speed counter; The count value of high-speed counter is sent into the flush bonding processor kernel processes after latching through data latches.

Multifunctional electric cable failure detector of the present invention is in conjunction with specialized integrated circuit technique, the high-speed signal acquisition treatment technology, modern detecting and electronic circuit technology etc., can test the length of twisted-pair feeder, whether twisted-pair feeder overlength, the connectedness of twisted-pair feeder (comprises open circuit, short circuit, reversal connection, wrong right, faults such as overlength), fault type (comprises short circuit, open circuit), multiple parameters such as position of failure point location and return loss, can quick and precisely obtain the technical parameter of twisted-pair feeder and realize that abort situation detects and the location, has the measuring accuracy height, dependable performance, portable characteristics are a kind of novel, multi-functional, incorporate testing apparatus.This tester can be used for civilian, industrial network comprehensive wiring scene, detect the characteristic and the fault of Network Transmission cable/concentric cable/cables such as common cable easily, and then in time eliminate network failure, and guarantee civilian and unimpeded and operate as normal industrial network, guarantee the unimpeded of information transmission.

During work, at first select test function, test parameter is set.When beginning to test, fpga chip control multicircuit relay circuit switches to test access in a pair of path of network cable to be measured, the single pulse signal that the fpga chip internal pulses produces the circuit generation is urged to network cable to be measured through the emission driving circuit with the transponder pulse amplification, transponder pulse reflects at the place, trouble spot, emission and reflected impulse are delivered to the high-speed comparator circuit through the signal condition shaping circuit, the high-speed comparator circuit with the signal that collects and reference voltage relatively the back output pulse signal to fpga chip, fpga chip is handled this pulse signal, and test result is presented on the LCD screen.

Test philosophy of the present invention is based on the multiecho detection method.The multiecho detection method is a kind of new test detection method that proposes on the basis of time domain pulse reflection method, core is that transponder pulse can take place repeatedly to reflect at the place, trouble spot, and each its reflection coefficient of reflex time is identical, and just the amplitude owing to its reflected impulse of reason of cable internal driving reduces gradually.Adopt the multiecho reflectometry can improve measuring resolution, reduced the test blind area, thereby improved the precision of test, avoided pulse individual reflection method to rely on and improved the restriction that the transponder pulse frequency improves precision, thereby reduced excessive demand the chip processing speed.

The position of failure point computing formula:

$S=V\&times;\frac{\mathrm{<figure-callout\; id="2"\; label="N"\; filenames="C2008100188130010H1.png,C2008100188130011H2.png"\; state="\{\{state\}\}">N</figure-callout>}}{2\mathrm{Mf}}$

Wherein: the S-trouble spot is apart from the distance of test point;

The transmission speed (be about 200m/ μ s) of V-pulse in network cable can be demarcated acquisition by experiment;

The count value of N-FPGA chip internal high-speed counter, i.e. the counting number of full sized pules;

The echo times of gathering in the M-multiecho detection method;

The inner embedded phase-locked loop circuit of f-FPGA (PLL) offers the standard clock signal of high-speed counter, and frequency is known.

Compared with prior art, beneficial effect of the present invention is:

1, the present invention is integrated in multinomial function (fault detect, localization of fault, return loss) in the system, really realizes a tractor serves several purposes, is a kind of novel, multi-functional, incorporate testing apparatus.Advanced person, dependable performance, economical and practical, the test result of possessing skills accurately and reliably, easy to operate and lightweight and portable in volume, portable advantage.

2, adopt time domain test and signal acquisition treatment method that pulse reflection method+the multiecho detection method combines, compare with simple employing pulse time domain reflectometry, reduced the requirement of system, reduced the test blind area, improved system testing precision and sensitivity signal frequency.

3, system is a core with the FPGA technology of maturation, employing is based on the SOPC (System-on-a-Programmable-Chip of FPGA, programmable system on chip) technology makes full use of the advantage of FPGA in high-speed signal acquisition and parallel signal processing, has improved system performance and corresponding speed.The embedded a plurality of high-performance embedded analog phase-locked looks of FPGA (PLL), produce the high-frequency signal that a plurality of frequencies are determined after the clock signal frequency multiplication that external crystal-controlled oscillation can be produced, and any phase shift can be provided and adjust the output signal dutycycle, thereby improved exomonental frequency and improved measuring accuracy.

4, the FPGA chip integration has become RISC flush bonding processor, peripheral hardware, storer, IO interface and test function circuit, all functions are integrated in a slice fpga chip, effectively reduce system cost, complicacy, power consumption, volume and anti-electromagnetic interference (EMI), improved the reliability and stability of system.

5, testing tool can automatically switch between the multi-channel network cable, once finish the test assignment of all paths of network cable, and can be according to the difference of test specification, automatic or manual is regulated exomonental amplitude (3.3V, 5V) and pulsewidth (5ns, 10ns, 20ns), to satisfy the requirement of different test conditions.Closely adopt the transponder pulse of 3.3V, 5ns, adopt the transponder pulse of 5V, 10ns/20ns at a distance.

6, tester promptly can use separately also can be connected with computing machine and realize network on-line test and online programming, can realize the Long-distance Control with tester uploaded of test data easily, is a kind of robotization, networking, intelligentized testing apparatus.

7, tester has all adopted modular design method from software to hardware, has reserved the interface that adds new functional module, has good upgrading space with portable, for laying a good foundation towards the secondary development of different user demands later.

8, the difference that this tester can be according to actual needs, revise the dependence test parameter to realize the various of application scenario, the fault that not only can be used for the test network cable, but also be applicable to the fault detect and the localization of fault of concentric cable, common cable multiple transmission cables such as (electric wires), have advantage applied widely.

Description of drawings

The invention will be further elaborated below in conjunction with the drawings and specific embodiments.

Fig. 1: the structured flowchart of multifunctional electric cable failure detector;

Fig. 2: the internal circuit configuration block diagram of fpga chip;

Fig. 3: the pin synoptic diagram of fpga chip;

Fig. 4: high-speed comparator connecting circuit figure;

Fig. 5: emission driving circuit figure;

Fig. 5 A:3.3V amplification driving circuit figure;

Fig. 5 B:5V amplification driving circuit figure;

Fig. 6: trip point localization of fault principle schematic;

Fig. 7: short dot localization of fault principle schematic.

Embodiment

As shown in Figure 1, a kind of multifunctional electric cable failure detector, form by fpga chip, FPGA configuration store chip, UART circuit, emission driving circuit, multicircuit relay circuit, signal condition shaping circuit, high-speed comparator circuit, A/D convertor circuit, numerically-controlled precise potentiometer, LCD display circuit, LED light circuit and key circuit, wherein: fpga chip is the core devices of whole tester, is controlling the work of whole tester and the processing computing of test data; FPGA configuration store chip is that its boot is downloaded after programmable gate array chip powers at the scene; The UART circuit be tester with host computer between the interface of communicating by letter, be used to receive the control command of host computer and realize uploading of test data; The pulse signal that the emission driving circuit is used for that field programmable gate array chip is produced amplifies satisfying test request, and this amplified pulse signal is delivered to the multicircuit relay circuit; The multicircuit relay circuit is used to control the switching between multichannel network cable to be measured; The signal condition shaping circuit will amplify shaping and be met the reflected signal that signals collecting requires from the signal of multicircuit relay circuit; Digital potentiometer is controlled by described fpga chip, for high-speed comparator provides reference voltage signal; The high-speed comparator circuit is used for catching, gathers described reflected signal and compares with described reference voltage signal, exports a compare result signal and gives described fpga chip; The reference voltage signal that A/D convertor circuit is used to gather the numerically-controlled precise potentiometer and provides is passed to the fpga chip processing; Liquid crystal display displays circuit, light emitting diode lamp circuit and key circuit are connected with described fpga chip, form the Man Machine Interface of system, are used to show test data, realize that selection function and parameter are provided with function.This multifunctional electric cable failure detector is connected with network cable to be measured by the RJ45 interface.

The internal circuit configuration block diagram of fpga chip as shown in Figure 2, by the soft nuclear of flush bonding processor kernel NIOS II flush bonding processor, the LCD display control circuit, the LED light control circuit, the serial communication controlling circuit, the keyboard decoding circuit, control relay circuit, analog to digital conversion (ADC) control circuit, inner embedded phase-locked loop circuit (PLL), pulse produces control circuit, d type flip flop, high-speed counter, data latches and digital potentiometer control circuit are formed, wherein: the flush bonding processor kernel is the maincenter of system, adopt the soft nuclear of NIOS II flush bonding processor, all internal circuits are write by the ieee standard hardware description language, the flush bonding processor kernel is the core of fpga chip, be responsible for the processing computing of inner each several part circuit working of control fpga chip and test data, and operation result is delivered to the LCD display control circuit; The LCD display control circuit is responsible for that the data that receive are delivered to external LCD and is shown; The LED light control circuit is used to control the flicker of external LED when continuity testing; The serial communication controlling circuit provides control signal and clock signal for fpga chip with communicating by letter of host computer; The keyboard decoding circuit is responsible for the input information decoding to external keyboard; Control relay circuit is controlled the closure of outside relay; The ADC control circuit plays control A/D convertor circuit work and receives translation data; The digital potentiometer control circuit is used to control the variation of numerically-controlled precise potentiometer resistance; The PLL circuit produces control circuit with pulse on the one hand and connects to form pulse-generating circuit, is connected with high-speed counter on the other hand, for high-speed counter provides count pulse; Pulse produces single pulse signal and the output that control circuit will be converted to a known pulsewidth from the continuous high frequency clock signal of PLL circuit; The input end of clock of d type flip flop is connected with the output terminal of described high-speed comparator circuit, and the output terminal of d type flip flop connects the Enable Pin of high-speed counter, and high-speed counter begins counting during high level, and high-speed counter stops counting during low level; The clock signal of the standard given frequency of the clock termination PLL circuit output of high-speed counter; The count value of high-speed counter is sent into the flush bonding processor kernel processes after latching through data latches.

Fig. 3 is the pin synoptic diagram of fpga chip, fpga chip is selected the EP1C6Q240C8N chip of the Cyclone of altera corp series for use, this chip has 240 pins, and wherein input and output pin (IO) has 185, can be according to the needs arrangement fpga chip of reality use and being connected of external circuit.Example: the 179th (transponder pulse output S2) of fpga chip and 180 pin (transponder pulse output S1) sending and receiving are respectively penetrated two input ends (launching driving circuit figure referring to Fig. 5) of driving circuit, can export the transponder pulse of 3.3V or 5V as required; The 177th (input I2) and 178 pin (input I1) can be used for connecing two outputs of high-speed comparator; 158-162 pin (relay control output J1-J5) connects the control end of five relays respectively; 138-141 (serial communication U1-U4) is as serial communication; 121-128 pin (meeting ADC output D0-D7) can be used for connecting the data terminal (6-13 of ADC chip) of ADC output; 131-133 pin (control end C1-C3) can be used as the control end of FPGA control ADC work; 134-136 pin (control end C4-C6) connects the control pin (the 1st, 2,7 pin of digital potentiometer) of digital potentiometer; 163-170 pin (LCD exports E0-E7) connects 8 bit data output terminals of LCD display, and 181-183 (LCD control output LC1-LC3) can be used as the control output end of LCD screen; 193-200 pin (LED exports E1-E8) is as the control end of 8 paths of LEDs lamps, and 203-205 pin (Keyboard Control P1-P3) is as the input end of keyboard circuit.High-speed comparator can be selected the LT1394 chip of LINEAR company for use, and A/D convertor circuit can be selected eight bipolarity ADC chip MAX161 of MAXIM company for use, and the numerically-controlled precise potentiometer is selected X9313 for use.

Fig. 4 illustrates high-speed comparator connecting circuit figure, and the in-phase input end of high-speed comparator LT1394 (chip 2 pin) links to each other with network cable to be measured by the RJ-45 interface, is used for the received pulse signal; The inverting input of high-speed comparator LT1394 connects the output terminal (the 5th pin) of numerically-controlled precise potentiometer X9313, for high-speed comparator provides reference voltage; The output of high-speed comparator (the 7th, 8 pin) connects the input end (the 177th, 178 pin) of fpga chip, and the signal that collects is input to the fpga chip internal circuit.The input end of ADC chip MAX161 (4 pin) connects the output terminal of numerically-controlled precise potentiometer X9313, and the reference voltage of high-speed comparator LT1394 is sampled; The output terminal DB1-DB0 of ADC chip MAX161 (13 pin-6 pin) connects the input end (121-128 pin) of fpga chip, and the data after the ADC conversion are inputed to fpga chip; The control end of ADC chip MAX161 (the 14th, 15,16 pin) connects the output terminal (133-131 pin) of fpga chip, the operate as normal of control ADC chip; The CLK end (the 17th pin) of ADC chip connects the external passive crystal oscillator, for the ADC chip provides sampling clock.The control end of numerically-controlled precise potentiometer (the 1st, 2,7 pin) connects the control output end (134-136 pin) of fpga chip, provides different reference voltages for high-speed comparator under the control of fpga chip.

Fig. 5 is divided into two kinds of amplification driving circuits of 3.3V and 5V for the schematic diagram of emission driving circuit.Fig. 5 A is the 3.3V amplification driving circuit, and the base stage of Technitron connects the output terminal of fpga chip (the 180th pin), and the pulse signal of fpga chip output is through the driving of triode, and the emitter by triode exports network cable to be measured to.Fig. 5 B is the 5V amplification driving circuit, and 21 pin of voltage amplification chip 74LVC4245 connect the output terminal of fpga chip (the 179th pin), receives the 3.3V pulse that fpga chip produces; 74LVC4245 is amplified to 5V with pulse, delivers to the base stage of high speed triode by 3 human hair combing wastes, and triode is urged to network cable to be measured by its emitter with signal.

The function of multifunctional electric cable failure detector comprises the following aspects:

1, fault type detects: continuity testing (comprising open circuit, short circuit, reversal connection, wrong to faults such as, overlength), fault type are judged (comprising short circuit, open circuit).

2, abort situation location: the accurate location of short circuit trouble point position, open circuit fault point position.

3, return loss detects: the size of detection of reflected echo.

Functional parameter is as follows:

1, the scope of application: network cable, concentric cable, common cable etc.;

2, function comprises: connective, trouble spot (short circuit, open circuit) location and return loss (Return Loss);

3, pulse height is divided into: two grades of 3.3V, 5V;

4, pulse width is divided into: 5ns, 10ns, 20ns third gear;

5, according to the difference of measuring distance, the pulse height that can automatically switch and pulsewidth;

6, the function that has automatic store test data and automatic/hand switch test path;

7, measuring distance: 0-500 rice;

8, measuring accuracy: 0.1 meter.

Test philosophy of the present invention is based on the multiecho detection method.Fig. 6, Fig. 7 illustrate open circuit fault point location, short circuit trouble point positioning principle synoptic diagram respectively.

Open circuit fault point location principle is as follows:

The high-speed comparator reference voltage is adjusted to suitable positive voltage, selects the out of circuit test function, set test parameter (pulsewidth, frequency), by beginning to test button.The inner PLL circuit of fpga chip with the external crystal-controlled oscillation frequency multiplication after, produce the known single pulse signal of emission one pulsewidth under the control of control circuit in pulse, after the emission driving circuit amplifies, deliver to twisted-pair feeder to be measured; When transponder pulse and reflected signal are higher than the reference voltage of high-speed comparator (reference voltage is a positive voltage), high-speed comparator output high level, when being lower than the reference voltage of high-speed comparator, output low level then; The rising edge that high-speed comparator is exported first pulse triggers the d type flip flop level and puts height, rises and delays output and put low when d type flip flop collects 4 pulses.The Enable Pin of 16 high-speed counters of output termination of d type flip flop, high level begin counting, and the clock signal of high-speed counter is provided after embedded phase-locked loop circuit (PLL) frequency multiplication of fpga chip inside by external crystal-controlled oscillation, and frequency is known.The count value of high-speed counter output is sent into the flush bonding processor kernel after latching through data latches, and processor carries out after the calculation process test result being shown on the LCD display to count value.

The short circuit trouble point positioning principle is as follows:

Select short dot fault test button, the reference voltage of high-speed comparator is transferred to suitable negative level, by the beginning testing button, pulse-generating circuit produces transponder pulse, simultaneously height is put in d type flip flop output, after high-speed comparator output low level when reflected signal is lower than datum, d type flip flop captured the negative edge of two comparer output pulses, output was put low; The high level control high-speed counter of d type flip flop output begins counting, and the clock signal of high-speed counter is the standard clock signal that PLL provides.The count value of high-speed counter output is sent into the flush bonding processor kernel through after the latches, and processor carries out after the calculation process test data being shown on the LCD display to count value.

Claims (1)

1. multifunctional electric cable failure detector, this tester is by field programmable gate array chip, field programmable gate array configuration store chip, serial communication interface circuit, the emission driving circuit, the multicircuit relay circuit, the signal condition shaping circuit, the high-speed comparator circuit, analog to digital conversion circuit, the numerically-controlled precise potentiometer, the liquid crystal display displays circuit, light emitting diode lamp circuit and key circuit are formed, wherein: field programmable gate array chip is the core devices of whole tester, is controlling the work of whole tester and the processing computing of test data; Field programmable gate array configuration store chip is that its boot is downloaded after programmable gate array chip powers at the scene; Serial communication interface circuit be tester with host computer between the interface of communicating by letter, be used to receive the control command of host computer and realize uploading of test data; The pulse signal that the emission driving circuit is used for that field programmable gate array chip is produced amplifies satisfying test request, and this amplified pulse signal is delivered to the multicircuit relay circuit; The multicircuit relay circuit is used to control the switching between multichannel network cable to be measured; The signal condition shaping circuit will amplify shaping and be met the reflected signal that signals collecting requires from the signal of multicircuit relay circuit; The numerically-controlled precise potentiometer is controlled by described field programmable gate array chip, for high-speed comparator provides reference voltage signal; The high-speed comparator circuit is used for catching, gathers described reflected signal and compares with described reference voltage signal, exports a compare result signal and gives described field programmable gate array chip; Analog to digital conversion circuit is used to gather the reference voltage signal that the numerically-controlled precise potentiometer provides and transformation result is passed to field programmable gate array chip handle; The liquid crystal display displays circuit, the light emitting diode lamp circuit is connected with described field programmable gate array chip with key circuit, the Man Machine Interface of composition system, be used to show test data, realize that selection function and parameter are provided with function, this multifunctional network electric cable failure detector is connected with network cable to be measured by the RJ45 interface, the internal circuit that it is characterized in that described field programmable gate array chip is by the flush bonding processor kernel, the liquid crystal display displays control circuit, the light emitting diode lamp control circuit, the serial communication controlling circuit, the keyboard decoding circuit, control relay circuit, analog-digital conversion control circuit, inner embedded phase-locked loop circuit, pulse produces control circuit, d type flip flop, high-speed counter, data latches and digital potentiometer control circuit are formed, wherein: the flush bonding processor kernel is the maincenter of system, all internal circuits are write by the ieee standard hardware description language, the flush bonding processor kernel is the core of field programmable gate array chip, be responsible for the processing computing of inner each several part circuit working of control field programmable gate array chip and test data, and operation result is delivered to the liquid crystal display displays control circuit; The liquid crystal display displays control circuit is responsible for the data that receive are delivered to outside liquid crystal display displays; The light emitting diode lamp control circuit is used to control the flicker of external light-emitting when continuity testing; The serial communication controlling circuit provides control signal and clock signal for field programmable gate array chip with communicating by letter of host computer; The keyboard decoding circuit is responsible for the input information decoding to external keyboard; Control relay circuit is controlled the closure of outside relay; Analog-digital conversion control circuit plays control analog-digital conversion circuit as described work and receives translation data; The digital potentiometer control circuit is controlled the variation of described numerically-controlled precise potentiometer resistance; Inner embedded phase-locked loop circuit produces control circuit with pulse on the one hand and connects to form pulse-generating circuit, is connected with high-speed counter on the other hand, for high-speed counter provides count pulse; Pulse produces single pulse signal and the output that control circuit will be converted to a known pulsewidth from the continuous high frequency clock signal of the embedded phase-locked loop circuit in inside; The input end of clock of d type flip flop is connected with the output terminal of described high-speed comparator circuit, and the output terminal of d type flip flop connects the Enable Pin of high-speed counter, and high-speed counter begins counting during high level, and high-speed counter stops counting during low level; The clock signal of the standard given frequency of the inner embedded phase-locked loop circuit output of the clock termination of high-speed counter; The count value of high-speed counter is sent into the flush bonding processor kernel processes after latching through data latches.

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