CN110175095A - A kind of multi-functional FPGA coincidence measurement system of man-machine interactive and its measurement method - Google Patents
A kind of multi-functional FPGA coincidence measurement system of man-machine interactive and its measurement method Download PDFInfo
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Abstract
The invention discloses a kind of multi-functional FPGA coincidence measurement system of man-machine interactive and its measurement methods, belong to application of electronic technology field, channel selecting can be realized directly in host computer application program, meets window setting, data delay setting, acquisition time, the acquisition of single data or continuous data acquisition, data delayed sweep and the functions such as calibration, data are shown, data save and interface parameter saves；It is proposed meets window adjusting method and mixing latency measurement method, realizes delay automatic measurement and calibration, avoids jitter caused by manually adding and subtracting delay line and regulation clock repeatedly；Integrated channel selects system and meets data processing system, realizes the selection on software to channel, and be capable of real-time acquisition and save data, next, which meets, designs parallel processing algorithm in operation, improves arithmetic speed；Interior design dozens of coincidence measurement module can carry out simultaneously multiple types and meet operation.Favorable expandability of the present invention, coincidence counting is high-efficient, transplantability and strong robustness.
Description
Technical field
The invention belongs to application of electronic technology field more particularly to a kind of man-machine interactive multi-functional FPGA coincidence measurement systems
System and its measurement method.
Background technique
Coincidence measurement is to record the technology that distribution is associated between the response of two or more detectors, be widely used in scientific research and
Signal detection and analysis in engineering, the multi-photon especially in quantum optices detect the specific important application of aspect simultaneously.Light
Son coincidence measurement can be further utilized to explore association light source Nonclassical Properties, and the time delay of signal processing system, visit
Survey device dark counting etc. influence direct interference the accuracy of coincidence counting.
For the relative delay between accurate measuring signal, the art is frequently with time-to-digit converter (Time-to-
Digital converter, TDC), the methods of time-to-amplitude converter (Time-to-amplitude converter, TAC),
These technologies are firstly the need of detection Start and Stop signal, when being spaced between two signals is not to measure the integral multiple of clock, just
It will lead to time measurement inaccuracy, and the module is mainly field programmable gate array
(Field.Programmable.Gate.Array FPGA peripheral equipment is unfavorable for highly integrated due to distribution parameter effect
Change, higher cost.To improve clock resolution, the clock of upper frequency can be used, usually to reach GHz, in circuit common
It is not easy to realize.
In addition, the coincidence measurement system developed both at home and abroad, it is most of can only one-side data acquisition, gate time, symbol
Close the parameters such as window it is cured within hardware, the modification of special parameter cannot be realized using host computer in particular circumstances, be
System does not have open and flexibility.The type of logical operation is carried out with input channel number and in diversification to input signal, is just compeled
Be essential to design it is a kind of can real-time perfoming Different Logic operation, the prolongable coincidence measurement system of logical operation type.
Summary of the invention
In order to solve the above technical problems, the invention adopts the following technical scheme:
A kind of multi-functional FPGA coincidence measurement system of man-machine interactive includes hardware components and corresponding matched software portion
Point；
Wherein, hardware components include clock modulation system, data collection system, data delay adjustment system, meet window
Setting system, channel selecting system, meet data processing system, acquisition time and mode setting system, complex control system and
Serial communication system；
The clock modulation system, output end and data collection system input terminal, data delay adjustment system input, symbol
It closes window setting system input, channel selecting system input terminal, meet data processing system input terminal, acquisition time and mode
Setting system input, complex control system input terminal are connected with serial communication system input terminal；
The data collection system, input terminal is connect with photodetector output end and clock modulation system output, defeated
Outlet postpones adjustment system input with data and connect；
The data postpone adjustment system, input terminal and clock modulation system output, data collection system output end and
The connection of complex control system output end, output end are connect with window setting system input is met；
It is described to meet window setting system, input terminal and clock modulation system output, data delay adjustment system output
End is connected with complex control system output end, output end and channel selecting system input terminal and meets data processing system input terminal
Connection；
The channel selecting system and the data processing system that meets are integrated, and input terminal and clock modulation system export
End, acquisition time and mode setting system output meet window setting system output and complex control system output end company
It connects, output end is connect with serial communication system input terminal；
The acquisition time and mode setting system, input terminal and clock modulation system output and complex control system are defeated
Outlet connection, output end and channel selecting system input terminal and meets data processing system input terminal and connect；
The complex control system, input terminal are connect with clock modulation system output and serial communication system output end,
Output end and data postpone adjustment system input, meet window setting system input, channel selecting system input terminal, meet
Data processing system input terminal, acquisition time are connected with mode setting system input；
The serial communication system, input terminal and clock modulation system output, meet number at channel selecting system output end
It is connected according to processing system output end, complex control system output end with host computer output end, output end is defeated with complex control system
Enter end to connect with host computer input terminal；
The clock modulation system is used to modulate data collection system in the hardware components, data postpone adjustment system,
Meet window setting system, channel selecting system, meet data processing system, acquisition time and mode setting system, comprehensive control
The input clock of system processed and serial communication system；
The data collection system is used for real-time collection voltages signal data, and enters data into fpga chip and handle；
The data delay adjustment system is used to carry out delay compensation to signal data；
It is described meet window setting system for adjust meet window size；
For the channel selecting system for gating several destination channels, non-selected channel is defaulted as high-impedance state；
The data for meeting data processing system for the destination channel to input carry out logical operation, include several
Coincidence counting submodule, each submodule is interior to design parallel processing algorithm；
The acquisition time and mode setting system are used to realize required acquisition data time by the counting to clock
Setting, and acquisition time is input to and is met in data processing system；
The complex control system will be solved for receiving the data that serial communication modular is sent, and in a manner of state machine
Data after tune be respectively allocated to data delay adjustment system, meet window setting system, acquisition time and mode setting system,
Channel selecting system and meet data processing system；The data for the serial communication modular for being also used to receive, are back to serial ports
Communication system；
The serial communication system is used to code and decode data, and is in communication with each other with host computer, is divided into receiving process
With the process of transmission；
Software section includes initialization module, channel selecting module, meets window setting module, data delay setting mould
Block, acquisition time setup module, the acquisition of single data or continuous data acquisition module, data delayed sweep and calibration module, number
According to display module, data storage module and interface parameter preserving module；
The initialization module, for configure serial port information, by channel selecting, meet window, data postpone and adopt
Collect temporal information, according to UART communication protocol, under be transmitted to the decoding of FPGA serial communication modular；
The channel selecting module, meet window setting module and data delay setup module, in the application with
Interface form is presented, and user need to only input relevant parameter on interface and reach the hardware components under encoding, so that it may realize
Fpga chip meets the configuration of window setting system and data delay adjustment system accordingly；
The data disaply moudle for receiving the data of FPGA upload, and decodes, by coincidence counting result with figure shape
Formula real-time display；
The data storage module will for receiving the decode the data of FPGA upload, and according to the preservation duration of setting
Timestamp and coincidence counting result are deposited into document；
The interface parameter saves and calling module, the parameter for interface to be arranged are saved into document, opened in next time
When dynamic application program, initial parameter is such as utilized, original document parameter is called.
As a kind of further preferred scheme of the multi-functional FPGA coincidence measurement system of man-machine interactive of the present invention, when described
Clock modulating system is made of phaselocked loop inside 50M clock crystal oscillator and FPGA；
As a kind of further preferred scheme of the multi-functional FPGA coincidence measurement system of man-machine interactive of the present invention, the number
According in the wiring in each channel of acquisition system use snakelike, parallel and isometric cabling mode.
As a kind of further preferred scheme of the multi-functional FPGA coincidence measurement system of man-machine interactive of the present invention, the number
According to delay adjustment system by FPGA internal logic wiring constitute, for signal data carry out delay compensation, be divided into coarse delay and
Thin delay chain, coarse delay use trigger technology, and the single precision that postpones is 2.5ns, and thin delay chain is using inside several FPGA
The cascade of stone delay cell, each stone delay cell have 0-255 tap, and each tapped delay precision is about 30ps, slightly
Thin delay, which combines, can reach a wide range of dynamic retardation compensation, specific algorithm: total delay=coarse delay (c × 2.5ns)+thin delay
(f × n × 30ps), wherein c is coarse delay number, and f is stone delay cell number, and n is tap coefficient.
It is described to adopt as a kind of further preferred scheme of the multi-functional FPGA coincidence measurement system of man-machine interactive of the present invention
Collection time and mode setting system are made of the wiring of FPGA internal logic, using trigger technology, the acquisition time and mode
Setting system is divided into single acquisition mode and continuous acquisition mode, and the presence or absence of single acquisition time determines in single acquisition mode
The beginning and stopping of single coincidence counting meet data processing system sending in continuous acquisition mode after single coincidence counting
One high level enable signal, is input in single acquisition mode, is again started up single acquisition mode, so recycles, and is formed continuous
Acquisition mode.
As a kind of further preferred scheme of the multi-functional FPGA coincidence measurement system of man-machine interactive of the present invention, using logical
With asynchronous receiving-transmitting transport protocol, wherein receiving process is the order data received in upper computer software, and is decoded as FPGA and can know
Other data information；Transmission process is in the host computer for receiving coincidence counting information inside FPGA and complex control system
Order data is sent to host computer by coding.
A kind of measurement method based on the multi-functional FPGA coincidence measurement system of man-machine interactive, specifically includes the following steps:
Step 1, in the software section, user respectively initialization module, channel selecting module, meet window setting
Module, acquisition time setup module input parameter, and reach the hardware components under encoding；
Step 2, in the hardware components, serial communication system is responsible for receiving the decode in the software section set
Initialization module, channel selecting module, meet window setting module, acquisition time setup module signal, and be separately input to
Correspondence system in the hardware components；
Step 3, for any two path signal of unknown delays, the data delayed sweep and calibration module can be used,
Scanning obtains two paths of signals length of delay, to synchronize two paths of signals；It, can be directly in institute for any two path signal of known delay
Data delay setup module incoming delay values are stated, to synchronize two paths of signals；
Step 4, the single data acquisition module or continuous data acquisition module are clicked, is strobed in the hardware components
Channel start the electric signal of pick-up probe, electric signal successively passes through data collection system, data delay adjustment system and symbol
It closes window and system is set, the logical operation of multi-channel electric signal is secondly carried out in meeting data processing system, data are logical in serial ports
It is encoded and is input in host computer application program in letter system, the data disaply moudle described in host computer application program is shown
Coincidence counting value；
Step 5, duration is saved as a result, can be arranged in data storage module to save coincidence counting, clicks operation, is
Coincidence counting result is just deposited into document by system；
Step 6, to save interface parameter, the interface parameter preserving module is clicked, then system can will input on interface
Setting parameter save to document.Start application program in next time, to call original parameter, clicks the interface parameter tune
With module.
As a kind of further preferred scheme of the multi-functional FPGA coincidence measurement method of man-machine interactive of the present invention, the number
According to devising two kinds of delay measurements methods in delayed sweep and synchronous calibration module: thickness latency measurement method and meeting window and adjust
Method returns to the length of delay between two paths of signals and by two paths of signals school by the delay numerical value between automatically scanning two paths of signals
Standard is synchronization signal；Steps are as follows for the thickness latency measurement method:
Step S1 selects fixed channel and need to be adjusted the channel of delay；
Step S2, if selection coarse delay is carefully prolonged if so, entering step S3.1 if it is not, then entering step S4.1 input
Slow adjustable range and step-length；
Step S3.1 inputs coarse delay adjustable range and step-length；
Step S3.2, coincidence counting statistics, and graphing, abscissa are delay adjustable range, and ordinate is to meet meter
Number result；
Step S3.3, whether fitting result meets the requirements, if so, S2.4 is entered step, if it is not, then entering step
S2.1；
Step S3.4 returns to corresponding length of delay under symmetry axis, and the length of delay is input to data delay adjustment system,
To synchronize two paths of signals；
Step S4.5, if the thin delay of selection is adjusted, if so, S4.1 is entered step, if it is not, then terminating process；
Step S4.1 inputs thin delay adjustable range and step-length；
Step S4.2, coincidence counting statistics, and graphing, abscissa are delay adjustable range, and ordinate is to meet meter
Number result；
Step S4.3, whether fitting result meets the requirements, if so, S4.4 is entered step, if it is not, then entering step
S4.1；
Step S4.4 returns to corresponding length of delay under symmetry axis, and the length of delay is input to data delay adjustment system,
To synchronize two paths of signals, finally terminate process；
Meeting window adjusting method, steps are as follows:
Step A1 selects fixed channel and need to be adjusted the channel of pulse length；
Step A2, to the adjustable range and step-length of the channel setting input pulse length that need to be adjusted；
Step A3, coincidence counting statistics, and graphing, abscissa are pulse length adjustable range, and ordinate is to meet
Count results；
Step A4, whether figure meets the requirements, if so, A5 is entered step, if it is not, then entering step A2；
Step A5, computing relay value, and length of delay input data is postponed adjustment system.
It is described soft as a kind of further preferred scheme of the multi-functional FPGA coincidence measurement method of man-machine interactive of the present invention
Part portions per sends command data to FPGA, and FPGA can return to the order data, for whether just to verify host computer order
Really.
It is described hard as a kind of further preferred scheme of the multi-functional FPGA coincidence measurement method of man-machine interactive of the present invention
After the completion of part portions per coincidence counting, coincidence counting can be received every time to all data xor operations, the software section
When, it also can be to all data xor operations, the comparison of two parts xor operation, for whether just to verify the data of FPGA transmission
Really.
The invention adopts the above technical scheme compared with prior art, has following technical effect that
1) present invention can be realized directly in host computer application program channel selecting, meet window setting, data delay set
Set, acquisition time, single data acquisition or continuous data acquisition, data delayed sweep and calibration, data are shown, data save and
The functions such as interface parameter preservation.It is open strong, it is full-featured, substantially meet existing experiment demand；
2) the present invention is based on host computer application program, proposition meets window adjusting method and mixing latency measurement method, can dynamic
Adjustment meets window and data delay, realizes delay automatic measurement and calibration, avoids manually adding and subtracting delay line and regulation repeatedly
Jitter caused by clock, when for measurement single photon signal, coincidence counting is more acurrate；
3) integrated channel of the present invention selection system and meet data processing system, can be directly directly realized by host computer pair
The selection in channel without plugging channel on hardware, and is capable of real-time acquisition and saves data, next meets in operation, devises
Parallel processing algorithm improves arithmetic speed and robustness；
4) FPGA interior design of the present invention dozens of coincidence measurement module, can carry out multiple types simultaneously meet operation,
Favorable expandability, coincidence counting are high-efficient；
5) present invention does not use external memory technology and time interval measurement technology, but directly develops piece respectively in FPGA
Upper storage resource and latency measurement scheme, convenient for being transplanted in other kinds of chip, the scheme that develops skill versatility；
6) present invention is using flip-flop design coarse delay system, and dynamic deferred adjustable extent is big, and strong antijamming capability is kept away
Exempt from jitter error caused by output signal reducing frequency phenomenon and adjustment clock phase etc..
Detailed description of the invention
Fig. 1 is coincidence measurement structural schematic diagram；
Fig. 2 is coarse delay system structure；
Fig. 3 is thickness latency measurement method flow chart；
Fig. 4 is to meet window adjusting method flow chart.
Specific embodiment
Technical solution of the present invention is described in further detail with reference to the accompanying drawing:
If Fig. 1 is coincidence measurement structural schematic diagram, include hardware components and corresponding matched software section；
Wherein, hardware components include clock modulation system, data collection system, data delay adjustment system, meet window
Setting system, channel selecting system, meet data processing system, acquisition time and mode setting system, complex control system and
Serial communication system；
The clock modulation system, output end and data collection system input terminal, data delay adjustment system input, symbol
It closes window setting system input, channel selecting system input terminal, meet data processing system input terminal, acquisition time and mode
Setting system input, complex control system input terminal are connected with serial communication system input terminal；
The data collection system, input terminal is connect with photodetector output end and clock modulation system output, defeated
Outlet postpones adjustment system input with data and connect；
The data postpone adjustment system, input terminal and clock modulation system output, data collection system output end and
The connection of complex control system output end, output end are connect with window setting system input is met；
It is described to meet window setting system, input terminal and clock modulation system output, data delay adjustment system output
End is connected with complex control system output end, output end and channel selecting system input terminal and meets data processing system input terminal
Connection；
The channel selecting system and the data processing system that meets are integrated, and input terminal and clock modulation system export
End, acquisition time and mode setting system output meet window setting system output and complex control system output end company
It connects, output end is connect with serial communication system input terminal；
The acquisition time and mode setting system, input terminal and clock modulation system output and complex control system are defeated
Outlet connection, output end and channel selecting system input terminal and meets data processing system input terminal and connect；
The complex control system, input terminal are connect with clock modulation system output and serial communication system output end,
Output end and data postpone adjustment system input, meet window setting system input, channel selecting system input terminal, meet
Data processing system input terminal, acquisition time are connected with mode setting system input；
The serial communication system, input terminal and clock modulation system output, meet number at channel selecting system output end
It is connected according to processing system output end, complex control system output end with host computer output end, output end is defeated with complex control system
Enter end to connect with host computer input terminal；
The clock modulation system is used to modulate data collection system in the hardware components, data postpone adjustment system,
Meet window setting system, channel selecting system, meet data processing system, acquisition time and mode setting system, comprehensive control
The input clock of system processed and serial communication system；
The data collection system is used for real-time collection voltages signal data, and enters data into fpga chip and handle；
The data delay adjustment system is used to carry out delay compensation to signal data；
It is described meet window setting system for adjust meet window size；
For the channel selecting system for gating several destination channels, non-selected channel is defaulted as high-impedance state；
The data for meeting data processing system for the destination channel to input carry out logical operation, include several
Coincidence counting submodule, each submodule is interior to design parallel processing algorithm.Meet data processing system and receives clock modulation system
The clock signal that transmits, meet that window setting system transmits meet window size data, the target that channel selecting system transmits
The gate time that channel gating signal, acquisition time and mode setting system transmit starts and cut-off enable signal and comprehensively control
The coincidence counting submodule chip selection signal that system transmits.For one of coincidence counting submodule, it is with 8 input channels
Example, is divided into preceding 4 channel and rear 4 channel while carrying out meeting operation, to improve system stability and speed.Specific algorithm is as follows:
Half_signal_and_channel_1≤(signal [3:0] &channel [3:0])；
Half_signal_and_channel_2≤(signal [7:4] &channel [7:4])；
Check_1≤(Half_signal_and_channel_1==channel [3:0])==1'b1；
Check_2≤(Half_signal_and_channel_2==channel [7:4])==1'b1；
Coincidence≤(Check_1&&Check_2).
Wherein, signal is 8 data, each represents data-signal all the way, when numerical value is 1, indicates that the channel has
Data, on the contrary indicate that the channel does not have data；Channel is 8 data, each represents a channel, when numerical value is 1,
It indicates to gate the channel, otherwise indicates to close the channel；Half_signal_and_channel_1 and Half_signal_and_
Channel_2 is that preceding 4 signal and rear 4 channel are carried out and operated respectively, gates the signal data of destination channel；
Check_1 and Check_2 does and operates with the data of rear 4 gatings to first 4 respectively, namely meets operation；Coincidence
It is to merge to first 4 and latter 4 with operation show to have occurred on the channel for gating primary if Coincidence is 1
Meet, otherwise indicates not meet.
The acquisition time and mode setting system are used to realize required acquisition data time by the counting to clock
Setting, and acquisition time is input to and is met in data processing system；
The complex control system will be solved for receiving the data that serial communication modular is sent, and in a manner of state machine
Data after tune be respectively allocated to data delay adjustment system, meet window setting system, acquisition time and mode setting system,
Channel selecting system and meet data processing system；The data for the serial communication modular for being also used to receive, are back to serial ports
Communication system；
The serial communication system is used to code and decode data, and is in communication with each other with host computer, is divided into receiving process
With the process of transmission；
Software section includes initialization module, channel selecting module, meets window setting module, data delay setting mould
Block, acquisition time setup module, the acquisition of single data or continuous data acquisition module, data delayed sweep and calibration module, number
According to display module, data storage module and interface parameter preserving module；
The initialization module, for configure serial port information, by channel selecting, meet window, data postpone and adopt
Collect temporal information, according to UART communication protocol, under be transmitted to the decoding of FPGA serial communication modular；
The channel selecting module, meet window setting module and data delay setup module, in the application with
Interface form is presented, and user need to only input relevant parameter on interface and reach the hardware components under encoding, so that it may realize
Fpga chip meets the configuration of window setting system and data delay adjustment system accordingly；
The data disaply moudle for receiving the data of FPGA upload, and decodes, by coincidence counting result with figure shape
Formula real-time display；
The data storage module will for receiving the decode the data of FPGA upload, and according to the preservation duration of setting
Timestamp and coincidence counting result are deposited into document；
The interface parameter saves and calling module, the parameter for interface to be arranged are saved into document, opened in next time
When dynamic application program, initial parameter is such as utilized, original document parameter is called.
The clock modulation system is made of phaselocked loop inside 50M clock crystal oscillator and FPGA；
Snakelike, parallel and isometric cabling mode is used in the wiring in each channel of data collection system.
The data delay adjustment system is made of the wiring of FPGA internal logic, for carrying out delay benefit to signal data
It repays, is divided into coarse delay and thin delay chain, coarse delay uses trigger technology, and the single precision that postpones is 2.5ns, and thin delay chain uses
Stone delay cell cascade inside several FPGA, each stone delay cell have 0-255 tap, each tapped delay essence
Degree is about 30ps, and thickness delay, which combines, can reach a wide range of dynamic retardation compensation, specific algorithm: total delay=coarse delay (c ×
2.5ns)+carefully delay (f × n × 30ps), wherein c is coarse delay number, and f is stone delay cell number, and n is tap coefficient.
Specifically, general related method thereof, such as Asynchronous FIFO Design method, since the clock at asynchronous FIFO both ends is different
Frequently, a part of pointer is easily missed, and due to the overturning of counter signals, so that being more prone to produce burr in circuit, interference has
Imitate signal；For clock count related method thereof, on the basis of the single clock cycle, postpone several time cycles, realizes data
The delay of signal, but when required retardation is more than the pulse period of input signal, other than first useful signal,
The signal that he is between retardation is easily ignored, and output signal is resulted in reducing frequency phenomenon occur.The present invention is set using trigger
Coarse delay system is counted, dynamic deferred adjustable extent is big, strong antijamming capability, avoids shake caused by adjustment clock phase
Error, secondly the system expandability is strong, if you need to increase retardation, in the case where FPGA internal resource allows, by extending trigger
Sum of series multiple selector series.
If Fig. 2 is coarse delay system structure, specific step is as follows for the design of coarse delay system:
S1: Clock management
The period of clock determines that the resolution ratio of coarse delay, the present invention use 400MHz clock, i.e. period in coarse delay system
For 2.5ns, every level-one trigger can produce 2.5ns delay；
S: the setting of trigger
Trigger uses d type flip flop, and the d type flip flop of every level-one is connected with next stage trigger, while and multi-path choice
Device connection.
S2: the setting of multiple selector
Multiple selector for gating required target level d type flip flop, the digit of multiple selector by d type flip flop series
It determines, the selection state for making can control for controlling target level multiple selector of multiple selector, multiple selector enables
The digit of control is determined by multiple selector series.
S3: the input and output of signal
Input signal successively passes through d type flip flop and multiple selector, final output signal.When host computer setting coarse delay is
15ns, the control signal of complex control system output multi-channel selector gate the 6th grade of D triggering in the 1st grade of multiple selector
Device, signal successively passes through the 16th grade of the 2nd grade, 3rd level multiple selector, final output signal later.
The acquisition time and mode setting system are made of the wiring of FPGA internal logic, described using trigger technology
Acquisition time and mode setting system are divided into single acquisition mode and continuous acquisition mode, in single acquisition mode when single acquisition
Between the presence or absence of determine the beginning and stopping of single coincidence counting, in continuous acquisition mode after single coincidence counting, meet number
A high level enable signal is issued according to processing system, is input in single acquisition mode, is again started up single acquisition mode, so
Circulation forms continuous acquisition mode.
Using universal asynchronous receiving-transmitting transport protocol, wherein receiving process is the order data received in upper computer software, and
It is decoded as the identifiable data information of FPGA；Transmission process is to receive coincidence counting information inside FPGA and complex control system
To host computer in order data be sent to host computer by coding.
A kind of measurement method based on the multi-functional FPGA coincidence measurement system of claim 1-6 man-machine interactive, feature
It is, specifically includes the following steps:
Step 1, in the software section, user respectively initialization module, channel selecting module, meet window setting
Module, acquisition time setup module input parameter, and reach the hardware components under encoding；
Step 2, in the hardware components, serial communication system is responsible for receiving the decode in the software section set
Initialization module, channel selecting module, meet window setting module, acquisition time setup module signal, and be separately input to
Correspondence system in the hardware components；
Step 3, for any two path signal of unknown delays, the data delayed sweep and calibration module can be used,
Scanning obtains two paths of signals length of delay, to synchronize two paths of signals；It, can be directly in institute for any two path signal of known delay
Data delay setup module incoming delay values are stated, to synchronize two paths of signals；
Step 4, the single data acquisition module or continuous data acquisition module are clicked, is strobed in the hardware components
Channel start the electric signal of pick-up probe, electric signal successively passes through data collection system, data delay adjustment system and symbol
It closes window and system is set, the logical operation of multi-channel electric signal is secondly carried out in meeting data processing system, data are logical in serial ports
It is encoded and is input in host computer application program in letter system, the data disaply moudle described in host computer application program is shown
Coincidence counting value；
Step 5, duration is saved as a result, can be arranged in data storage module to save coincidence counting, clicks operation, is
Coincidence counting result is just deposited into document by system；
Step 6, to save interface parameter, the interface parameter preserving module is clicked, then system can will input on interface
Setting parameter save to document.Start application program in next time, to call original parameter, clicks the interface parameter tune
With module.
Devise two kinds of delay measurements methods in the data delayed sweep and synchronous calibration module: thickness latency measurement method and
Meet window adjusting method, by the delay numerical value between automatically scanning two paths of signals, returns to length of delay between two paths of signals simultaneously
Two paths of signals is calibrated to synchronization signal；Steps are as follows for the thickness latency measurement method:
Step S1 selects fixed channel and need to be adjusted the channel of delay；
Step S2, if selection coarse delay is carefully prolonged if so, entering step S3.1 if it is not, then entering step S4.1 input
Slow adjustable range and step-length；
Step S3.1 inputs coarse delay adjustable range and step-length；
Step S3.2, coincidence counting statistics, and graphing, abscissa are delay adjustable range, and ordinate is to meet meter
Number result；
Step S3.3, whether fitting result meets the requirements, if so, S2.4 is entered step, if it is not, then entering step
S2.1；
Step S3.4 returns to corresponding length of delay under symmetry axis, and the length of delay is input to data delay adjustment system,
To synchronize two paths of signals；
Step S4.5, if the thin delay of selection is adjusted, if so, S4.1 is entered step, if it is not, then terminating process；
Step S4.1 inputs thin delay adjustable range and step-length；
Step S4.2, coincidence counting statistics, and graphing, abscissa are delay adjustable range, and ordinate is to meet meter
Number result；
Step S4.3, whether fitting result meets the requirements, if so, S4.4 is entered step, if it is not, then entering step
S4.1；
Step S4.4 returns to corresponding length of delay under symmetry axis, and the length of delay is input to data delay adjustment system,
To synchronize two paths of signals, finally terminate process；
Meeting window adjusting method, steps are as follows:
Step A1 selects fixed channel and need to be adjusted the channel of pulse length；
Step A2, to the adjustable range and step-length of the channel setting input pulse length that need to be adjusted；
Step A3, coincidence counting statistics, and graphing, abscissa are pulse length adjustable range, and ordinate is to meet
Count results；
Step A4, whether figure meets the requirements, if so, A5 is entered step, if it is not, then entering step A2；
Step A5, computing relay value, and length of delay input data is postponed adjustment system.
The software section sends command data to FPGA every time, and FPGA can return to the order data, for verifying
Whether position machine order is correct.
, can be to all data xor operations after the completion of each coincidence counting of hardware components, the software section is each
When receiving coincidence counting, all data xor operations, the comparison of two parts xor operation can also be sent for verifying FPGA
Data it is whether correct.
General technical staff of the technical field of the invention also will readily appreciate that in addition to the foregoing, illustrates herein and schemes
The specific embodiment shown can further change combination.Although the present invention is to give what diagram illustrated with regard to its preferred embodiment,
But person skilled in the art is, it is recognized that in the spirit and scope of the present invention defined by the attached claims,
A variety of changes and variation can be also made to the present invention.
Claims (10)
1. a kind of multi-functional FPGA coincidence measurement system of man-machine interactive, it is characterised in that: comprising hardware components and corresponding mating
Software section；
Wherein, hardware components include clock modulation system, data collection system, data delay adjustment system, meet window setting
System, channel selecting system meet data processing system, acquisition time and mode setting system, complex control system and serial ports
Communication system；
The clock modulation system, output end and data collection system input terminal, meet window at data delay adjustment system input
Mouth setting system input, meets data processing system input terminal, acquisition time and mode setting at channel selecting system input terminal
System input, complex control system input terminal are connected with serial communication system input terminal；
The data collection system, input terminal are connect with photodetector output end and clock modulation system output, output end
Postpone adjustment system input with data to connect；
The data postpone adjustment system, input terminal and clock modulation system output, data collection system output end and synthesis
The connection of control system output end, output end are connect with window setting system input is met；
It is described to meet window setting system, input terminal and clock modulation system output, data delay adjustment system output and
The connection of complex control system output end, output end and channel selecting system input terminal and meets data processing system input terminal and connects
It connects；
The channel selecting system and the data processing system that meets are integrated, input terminal and clock modulation system output,
Acquisition time and mode setting system output meet window setting system output and connect with complex control system output end,
Output end is connect with serial communication system input terminal；
The acquisition time and mode setting system, input terminal and clock modulation system output and complex control system output end
Connection, output end and channel selecting system input terminal and meets data processing system input terminal and connect；
The complex control system, input terminal are connect with clock modulation system output and serial communication system output end, output
End and data delay adjustment system input meet window setting system input, channel selecting system input terminal, meet data
Processing system input terminal, acquisition time are connected with mode setting system input；
The serial communication system, input terminal and clock modulation system output, meet at data channel selecting system output end
Reason system output, complex control system output end are connected with host computer output end, output end and complex control system input terminal
It is connected with host computer input terminal；
The clock modulation system is for modulating data collection system in the hardware components, data delay adjustment system, meeting
Window setting system, channel selecting system meet data processing system, acquisition time and mode setting system, comprehensively control system
The input clock of system and serial communication system；
The data collection system is used for real-time collection voltages signal data, and enters data into fpga chip and handle；
The data delay adjustment system is used to carry out delay compensation to signal data；
It is described meet window setting system for adjust meet window size；
For the channel selecting system for gating several destination channels, non-selected channel is defaulted as high-impedance state；
The data for meeting data processing system for the destination channel to input carry out logical operation, meet comprising several
Counting submodule, each submodule is interior to design parallel processing algorithm；
Acquisition data time needed for the acquisition time and mode setting system are used to realize by the counting to clock is arranged,
And acquisition time is input to and is met in data processing system；
The complex control system is used to receive the data that serial communication modular is sent, and will be after demodulation in a manner of state machine
Data be respectively allocated to data delay adjustment system, meet window setting system, acquisition time and mode setting system, channel
Selection system and meet data processing system；The data for the serial communication modular for being also used to receive, are back to serial communication
System；
The serial communication system is used to code and decode data, and is in communication with each other with host computer, is divided into receiving process and hair
It is sent into journey；
Software section includes initialization module, channel selecting module, meets window setting module, data delay setup module, adopts
Collection time setup module, the acquisition of single data or continuous data acquisition module, data delayed sweep and calibration module, data are shown
Module, data storage module and interface parameter preserving module；
The initialization module, for configure serial port information, by channel selecting, meet window, data postpone and acquisition when
Between information, according to UART communication protocol, under be transmitted to the decoding of FPGA serial communication modular；
The channel selecting module meets window setting module and data delay setup module, in the application with interface
Change form is presented, and user need to only input relevant parameter on interface and reach the hardware components under encoding, so that it may realize FPGA
Chip meets the configuration of window setting system and data delay adjustment system accordingly；
The data disaply moudle for receiving the data of FPGA upload, and decodes, and coincidence counting result is graphically real
When show；
The data storage module, for receiving the decode the data of FPGA upload, and according to the preservation duration of setting, by the time
Stamp and coincidence counting result are deposited into document；
The interface parameter saves and calling module, the parameter for interface to be arranged are saved into document, and in next time, starting is answered
When with program, initial parameter is such as utilized, original document parameter is called.
2. the multi-functional FPGA coincidence measurement system of a kind of man-machine interactive according to claim 1, it is characterised in that: described
Clock modulation system is made of phaselocked loop inside 50M clock crystal oscillator and FPGA.
3. the multi-functional FPGA coincidence measurement system of a kind of man-machine interactive according to claim 1, it is characterised in that: described
Snakelike, parallel and isometric cabling mode is used in the wiring in each channel of data collection system.
4. the multi-functional FPGA coincidence measurement system of a kind of man-machine interactive according to claim 1, it is characterised in that: described
Data postpone adjustment system and are made of the wiring of FPGA internal logic, for carrying out delay compensation to signal data, are divided into coarse delay
With thin delay chain, coarse delay uses trigger technology, and the single precision that postpones is 2.5ns, and thin delay chain is using in several FPGA
The cascade of portion's stone delay cell, each stone delay cell have 0-255 tap, and each tapped delay precision is about 30ps,
Thickness delay, which combines, can reach a wide range of dynamic retardation compensation, specific algorithm: total delay=coarse delay (c × 2.5ns)+carefully prolong
(f × n × 30ps) late, wherein c is coarse delay number, and f is stone delay cell number, and n is tap coefficient.
5. the multi-functional FPGA coincidence measurement system of a kind of man-machine interactive according to claim 1, it is characterised in that: described
Acquisition time and mode setting system are made of the wiring of FPGA internal logic, using trigger technology, the acquisition time and mould
Formula setting system is divided into single acquisition mode and continuous acquisition mode, and the presence or absence of single acquisition time determines in single acquisition mode
The beginning and stopping of single coincidence counting meets data processing system hair in continuous acquisition mode after single coincidence counting
A high level enable signal out is input in single acquisition mode, is again started up single acquisition mode, is so recycled, the company of being formed
Continuous acquisition mode.
6. the multi-functional FPGA coincidence measurement system of a kind of man-machine interactive according to claim 1, it is characterised in that: use
Universal asynchronous receiving-transmitting transport protocol, wherein receiving process is the order data received in upper computer software, and being decoded as FPGA can
The data information of identification；Transmission process is in the host computer for receiving coincidence counting information inside FPGA and complex control system
Order data be sent to host computer by coding.
7. a kind of measurement method based on the multi-functional FPGA coincidence measurement system of claim 1-6 man-machine interactive, feature exist
In, specifically includes the following steps:
Step 1, in the software section, user respectively initialization module, channel selecting module, meet window setting mould
Block, acquisition time setup module input parameter, and reach the hardware components under encoding；
Step 2, in the hardware components, serial communication system be responsible for receiving the decode in the software section it is set just
Beginningization module, channel selecting module meet window setting module, acquisition time setup module signal, and are separately input to described
Correspondence system in hardware components；
Step 3, for any two path signal of unknown delays, the data delayed sweep and calibration module can be used, scan
Two paths of signals length of delay is obtained, to synchronize two paths of signals；It, can be directly in the number for any two path signal of known delay
According to delay setup module incoming delay values, to synchronize two paths of signals；
Step 4, the single data acquisition module or continuous data acquisition module are clicked, what is be strobed in the hardware components is logical
Road starts the electric signal of pick-up probe, and electric signal successively passes through data collection system, data delay adjustment system and meets window
Mouth setting system, secondly carries out the logical operation of multi-channel electric signal, data are in serial communication system in meeting data processing system
It is encoded and is input in host computer application program in system, the data disaply moudle described in host computer application program, which is shown, to be met
Count value；
Step 5, duration is saved as a result, can be arranged in data storage module to save coincidence counting, clicks operation, system is just
Coincidence counting result is deposited into document；
Step 6, to save interface parameter, the interface parameter preserving module is clicked, then system can be set what is inputted on interface
Parameter is set to save to document.Start application program in next time, to call original parameter, clicks the interface parameter and call mould
Block.
8. a kind of multi-functional FPGA coincidence measurement method of man-machine interactive according to claim 7, it is characterised in that: described
It devises two kinds of delay measurements methods in data delayed sweep and synchronous calibration module: thickness latency measurement method and meeting window and adjust
Method returns to the length of delay between two paths of signals and by two paths of signals school by the delay numerical value between automatically scanning two paths of signals
Standard is synchronization signal；Steps are as follows for the thickness latency measurement method:
Step S1 selects fixed channel and need to be adjusted the channel of delay；
Step S2, if selection coarse delay is adjusted if so, entering step S3.1 if it is not, then entering step the thin delay of S4.1 input
Adjusting range and step-length；
Step S3.1 inputs coarse delay adjustable range and step-length；
Step S3.2, coincidence counting statistics, and graphing, abscissa are delay adjustable range, and ordinate is coincidence counting knot
Fruit；
Step S3.3, whether fitting result meets the requirements, if so, S2.4 is entered step, if it is not, then entering step S2.1；
Step S3.4 returns to corresponding length of delay under symmetry axis, and the length of delay is input to data delay adjustment system, with same
Walk two paths of signals；
Step S4.5, if the thin delay of selection is adjusted, if so, S4.1 is entered step, if it is not, then terminating process；
Step S4.1 inputs thin delay adjustable range and step-length；
Step S4.2, coincidence counting statistics, and graphing, abscissa are delay adjustable range, and ordinate is coincidence counting knot
Fruit；
Step S4.3, whether fitting result meets the requirements, if so, S4.4 is entered step, if it is not, then entering step S4.1；
Step S4.4 returns to corresponding length of delay under symmetry axis, and the length of delay is input to data delay adjustment system, with same
Two paths of signals is walked, process is finally terminated；
Meeting window adjusting method, steps are as follows:
Step A1 selects fixed channel and need to be adjusted the channel of pulse length；
Step A2, to the adjustable range and step-length of the channel setting input pulse length that need to be adjusted；
Step A3, coincidence counting statistics, and graphing, abscissa are pulse length adjustable range, ordinate is coincidence counting
As a result；
Step A4, whether figure meets the requirements, if so, A5 is entered step, if it is not, then entering step A2；
Step A5, computing relay value, and length of delay input data is postponed adjustment system.
9. a kind of multi-functional FPGA coincidence measurement method of man-machine interactive according to claim 8, it is characterised in that: described
Software section sends command data to FPGA every time, and FPGA can return to the order data, for whether verifying host computer order
Correctly.
10. a kind of multi-functional FPGA coincidence measurement method of man-machine interactive according to claim 8, it is characterised in that: institute
, can be to all data xor operations after the completion of stating each coincidence counting of hardware components, the software section receives every time to be met
When counting, also can to all data xor operations, the comparison of two parts xor operation, for verify FPGA transmission data whether
Correctly.
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