CN201392368Y - Characteristic impedance testing device for circuit board - Google Patents

Abstract

The utility model discloses a device capable of fast testing the characteristic impedance of a printed circuit board, which comprises a testing host machine, a probe, a PC, a printer and analysis software, wherein the analysis software operates on the PC, and the testing host machine comprises a pulse generating circuit, a pulse receiving circuit, a coaxial switch, a signal collecting module, a logic control module and a CPU processing module. The device adopts the intelligent and automatic design combining with the testing method, so users can do automatic testing, result display and the like after the simple initialization setting on the PC, the manual operation steps are simplified, and the operation difficulty is lowered. The output end of the device adopts the coaxial switch for switching, so a single step pulse sending circuit and a single receiving passage can be used for realizing the differential resistance testing, the error problem caused by two different step pulse generating circuits or two receiving passages is solved, the testing precision is effectively improved, and simultaneously, the probability of damage on the testing host machine by the external static is lowered.

Description

A kind of wiring board characteristic impedance proving installation

Technical field

The utility model relates to a kind of device of testing PC board characteristic impedance fast.

Background technology

In recent years, develop rapidly along with electronic products such as desktop computer (PC), notebook computer, mobile phone, Digital Television, set-top box, consumer electronics (MP3, MP4, game machine, digital camera etc.), communication facilities and automotive electronics, its signal transmission frequencies and speed are more and more higher, and employed wiring board (PCB) has been proposed strict characteristic impedance test request.

The physical size of circuit, PCB manufactured materials, processing technology etc. are all relevant on the characteristic impedance of pcb board circuit and the plate, and the characteristic impedance of possible each batch wiring board is all different.For the operation circuit impedance, PCB manufacturer need carry out strict characteristic impedance test, the requirement whether check meets design and produce to each the piece PCB that produces; Manufacturer can adjust or compensate the characteristic impedance of different batches PCB by changing methods such as line width, laminated thickness, control etching according to test result, satisfies the requirement of client to pcb board characteristic impedance control accuracy.

The such specialized laboratory's equipment of domain reflectometer (TDR) that traditional proving installation need adopt sampling oscilloscope and step pulse generation/sampler to form comes the characteristic impedance of circuit etching on the measurement circuit plate or test sample plate.There are some shortcomings in this testing apparatus, for example: complicated operation, with high costs, test speed is slow, and instrument is damaged by electrostatic breakdown easily, to test job environmental requirement harshness etc.

The utility model content

The purpose of this utility model is to provide a kind of wiring board characteristic impedance proving installation so that high speed, the characteristic impedance of HF link plate are realized succinctly, test fast and accurately, improves wiring board characteristic impedance detection efficiency.

For achieving the above object, the technical solution adopted in the utility model is:

A kind of wiring board characteristic impedance proving installation is provided, comprises Test Host, probe, PC printer and run on analysis software on the PC.

Described Test Host comprises at least:

One pulse generating circuit is connected with Logic control module, is used for producing excitation step pulse signal;

One pulse receiving circuit is connected between signal acquisition module and the coaxswitch, the pulse signal that the line reflection to be measured that is used to sample is returned;

One coaxial switch is connected in pulse generating circuit, pulse receiving circuit and patches between the output port of probe, is subjected to Logic control module control switch test mode, realizes importing and exporting of signal;

One signal acquisition module is connected between CPU processing module and the pulse receiving circuit, is used for the reflected signal filtering that receives, amplifies and change into digital signal and send into storer and store, and reads for CPU;

One Logic control module is connected with the CPU processing module, and control is coordinated in the work of cpu instruction paired pulses generation module, pulse receiving circuit, signal acquisition module and coaxswitch of accepting;

One CPU processing module is connected communication with PC, accepts test control command and test parameter that PC sends, and the order of translation PC sends to Logic control module.

A kind of concrete scheme is: pin S1, the S5 of described coaxswitch K connect pull-up resistor respectively, and pin S2, S4 connect two output channel CHA, CHB end respectively; Pin S3 connects pulse generating circuit; 3 control pin K1+, K2+, the K-of coaxswitch K all connect logic control circuit; Logic control circuit control coaxswitch switches, and pin S2 and/or S4 can be connected to pin S3, and the driving pulse of the pulse generating circuit output that is connected in the S3 place is loaded on output channel CHA and/or the CHB.

A kind of scheme more specifically is: described CPU processing module comprises DSP digital signal processor and connected ARM microprocessor, described CPU processing module by the ARM microprocessor up with the PC communication, by the DSP digital signal processor descending with Logic control module communication, and data in the acquisition memory.

Advantage of the present utility model is: (1) is with respect to prior art, device described in the utility model adopts intellectuality and The Automation Design, the user only need to PC carry out that simple initialization setting just can be tested rapidly automatically, display result, automatic report generation and printing, simplify manual steps greatly, reduced operation easier; (2) output terminal adopts coaxswitch to switch, use " single step pulse generation circuit and single receiving cable " to realize the test of differential line impedance, when having avoided adopting two step pulse generation circuit or two receiving cable tests, because two pulse generating circuits or two error problems that passage can not in full accordly bring have effectively improved measuring accuracy; (3) when device when not working, utilize coaxswitch to cut off that step pulse takes place and receiving circuit with being connected of output channel, from physically having broken off being connected of the Test Host and the external world, effectively reduce the probability of damage of exterior static to Test Host.

Description of drawings

Fig. 1 is that wiring board characteristic impedance proving installation principle described in the utility model is formed schematic block diagram;

Fig. 2 is described coaxswitch embodiment principle schematic;

Fig. 3 is that coaxswitch described in the utility model works in the CTL1 pattern, and step pulse is loaded into the CHA passage, circuit diagram when CHB is connected to pull-up resistor;

Fig. 4 is that coaxswitch works in the CTL2 pattern, and step pulse is loaded into the CHB passage, circuit diagram when CHA is connected to pull-up resistor;

Fig. 5 is the equivalent circuit diagram of Fig. 3, Fig. 4;

Fig. 6 is that coaxswitch works in the CTL3 pattern, and step pulse is loaded into CHA and CHB channel circuit synoptic diagram simultaneously;

Fig. 7 is the equivalent circuit diagram of Fig. 6;

Fig. 8 is described wiring board characteristic impedance method of testing schematic flow sheet.

Embodiment

For the ease of it will be appreciated by those skilled in the art that the utility model is described in further detail below in conjunction with drawings and Examples:

As Fig. 1, described wiring board characteristic impedance proving installation comprises Test Host 100, is plugged in probe 103, the PC 101 on the Test Host and joins the printer of being located on the PC 102.Described Test Host comprises pulse generating circuit 205, coaxswitch 206, pulse receiving circuit 209, signal acquisition module, Logic control module 202 and CPU processing module 101.

Described pulse generating circuit 205, it is connected with Logic control module 202, is used for producing excitation step pulse signal.When the access test line began to test, high speed step pulse signal was propagated along test line, reflects when running into the impedance point of discontinuity.The step pulse signal rising edge rise time scope that requires its generation in this device is between 120ps～160ps, and the pulse amplitude scope is between 200mV～300mV, and frequency range is between 10kHz～200kHz.The best choosing value of signal is: the rise time is less than 150ps, amplitude 250mV, pulsed frequency 32.768kHz.

Described coaxswitch 206 is connected in pulse generating circuit, pulse receiving circuit and patches between the output port of probe, is subjected to Logic control module control switch test mode, realizes importing and exporting of signal.

Described pulse receiving circuit 209 is connected between signal acquisition module and the coaxswitch, the pulse signal that the line reflection to be measured that is used to sample is returned.

Described signal acquisition module comprises successively the A/D change-over circuit 204 and the FIFO memory circuitry 203 that connect, is used for the reflected signal filtering that receives, stores after amplifying, change into digital signal.

Described Logic control module 202 is connected with CPU processing module 101, accepts cpu instruction paired pulses generation circuit, pulse receiving circuit, signal acquisition module work and coordinates control.The clock 1 of Logic control module 202 received pulse generation circuit is through synchronously and produce the control signal 1 of giving pulse generating circuit, the clock signal 2 of giving the ADC analog to digital conversion circuit after the sequential adjustment and to the clock signal 3 of pulse receiving circuit.Logic control module 202 is by the mode of operation of control signal 3 configuration coaxswitches; Triggering, beginning and power cut-off by control signal 1 control pulse generation circuit; By control

The work schedule of system signal 2 gating pulse receiving circuits and ADC conversion, storage data.

Described CPU processing module is connected communication with PC 101, accepts test control command and test parameter that PC sends, and the order of translation PC sends to Logic control module.PC is connected with printing device 102.

Described CPU processing module can comprise DSP digital signal processor and connected ARM microprocessor.Described CPU processing module by the ARM microprocessor up with the PC communication, by the DSP digital signal processor descending with the Logic control module communication, DSP can be by EMIF and SPI interface and Logic control module communication, and data in the acquisition memory.Here the DSP digital signal processor is now communicated by letter by the HPI cause for gossip with the ARM microprocessor.

Above-mentioned ARM microprocessor can communicate by network service mouth (LAN) and PC, accepts test control command and test parameter that PC sends, and the order of translation PC sends to Logic control module (FPGA).After the test beginning, FPGA launches the step pulse signal according to the test request control pulse generation circuit to the test line plate, and receive the voltage signal reflect, gather, store after converting digital signal to, handle, carry out the impedance conversion computing by the CPU processing module then, be sent to by network interface at last and show in the PC and generate form, printing.

Described PC moves a upper layer software (applications), and upper layer software (applications) mainly comprises network interface circuit monitoring, transceive data, Treatment Analysis data and control characteristic testing impedance host work.After test process finished, PC read data and the result after CPU handles, and showed test waveform and test result at last on screen, and generated report printing.Perhaps PC also can be finished the work such as data processing, impedance conversion computing of CPU, to simplify CPU processing module in the Test Host.

As Fig. 2, be described coaxswitch embodiment principle schematic.

Pin S1, the S5 of described coaxswitch K connect 50 ohmic load resistance respectively, and pin S2, S4 connect CHA, CHB two output channel interface end respectively; Pin S3 connects pulse generating circuit; 3 control pin K1+, K2+, the K-of coaxswitch K all connect logic control circuit; Logic control circuit control coaxswitch switches, and pin S2 and/or S4 can be connected to pin S3, and the driving pulse of the pulse generating circuit output that is connected in the S3 place is loaded on output channel CHA and/or the CHB.

The logical relation such as the following table of the controlled work of described coaxswitch:

The utility model adopts single step pulse generation circuit and single receiving cable to realize the test of differential line impedance by the switching of coaxswitch.When having solved available technology adopting two step pulse generations circuit or two receiving cable tests, because two pulse generating circuits or two error problems that passage can not in full accordly bring have effectively improved measuring accuracy.

Various working methods of coaxswitch and equivalent electrical circuit such as Fig. 3 are to shown in Figure 7.

Based on above-mentioned proving installation, described wiring board characteristic impedance method of testing step is:

(1) user configures test starting point and end point, promptly between the test section by PC;

(2) user's parameter of test file being set according to the characteristic impedance value and the permissible range of wiring board designing requirement on PC, upper layer software (applications) generates the batch testing tabulation automatically;

(3) Test Host in the starting characteristic impedance test device;

(4) PC sends test command and test parameter to logic control circuit by the CPU processing module;

(5) the logic control circuit control pulse generation circuit produces the step pulse signal loading to the test line plate;

(6) pulse receiving circuit, signal acquisition module collaborative work are gathered the sampled point of setting quantity, and are stored in the storer;

(7) (7) CPU processing module reads the data of storer, the splicing sample waveform, and characteristic impedance value and the permissible range of calculating test impedance and setting compare, and obtain " qualified " and " defective " result;

(8) after the single end of test (EOT), PC reads deal with data and the result of CPU, shows test waveform and test result, and generates report printing.

Test Host is once tested each test point successively according to the setup parameter and the order of batch testing tabulation; If what be provided with is the average test mode then repeats repeatedly to test the back and calculate.Can be according to the requirement of setting by PC and the one calculating test impedance at least of CPU processing module, adopt the test of average mode can also calculate mean value, maximal value, minimum value and standard deviation result, the wiring board characteristic impedance value and the permissible range of test result and setting compare, and obtain " qualified " and " defective " result.

Device described in the utility model is universal and extendability is all very strong, at first in step 1,2, for test points different on different pcb boards, the pcb board, different parameters need be set.Each test point all has a test parameter, and after setting, the user needs in time to preserve this parameter; After having set a test point and parameter, the user can continue to add next test point and parameter; Treat that the user has set after all test points, software generates the test tabulation automatically; The user can resequence, revise or add parameter this tabulation, saves as independent test file at last; When needing later on to carry out same test again, can open the preservation test file, proceed test.

The parameter of each test point mainly contains:

Sequence number	Content	Explanation
				1	Title	The test point title is set by the user

2	Lamination	Tested transmission line is in concrete which layer of wiring board
			3	Characteristic impedance value	The typical characteristics resistance value that wiring board design and manufacturing require
4	Allowable tolerance+	Allowable tolerance+scope is represented with ohm or number percent
			5	Allowable tolerance-	Allowable tolerance-scope is represented with ohm or number percent
6	Passage	Specify the passage that uses instrument, CHA or CHB
			7	Method of testing	Single test or average test
8	The test unit of display	Inch/foot/millimeter etc.
			9	The test starting point	The user can set as required
10	The test terminal point	The user can set as required
			11	Cable length	Instrument can dispose the cable of different length, different size
12	Vertical coordinate unit	Unit: ohm/div, the user can oneself set

Step 3, after the tests column table generated, the user just can directly carry out mass and test automatically.Click the initiating key of software, perhaps start the Test Host that is connected with PC by the "enter" key" of lower keyboard, Test Host is inner, and all are soft, hardware module starts simultaneously, enter duty.

Step 4, PC sends test command and test parameter to the CPU processing module according to test file.CPU translates test parameter, and judgement is that test mode is single end testing or difference test, judges test channel, sets the starting point and the end point of sampling instant, sets the number N of sampled data.Send beginning test command, test control command then to the fpga logic control circuit.

Can be divided into several situations after the step 5,6:

(1) if the user selects CHA or CHB passage to carry out the single end testing mode, then carry out according to the following steps:

A, fpga logic control circuit send CTL1 or CTL2 orders to coaxswitch, sends initiation command then to step pulse generation circuit.

The step pulse signal that b, pulse generating circuit produce via CHA or CHB channel transfer to the test line plate, signal runs into the impedance point of discontinuity and reflects, receive this by pulse receiving circuit and transmit, become digital signal, store in the FIFO storer through the signal acquisition module treatment conversion;

C, fpga logic control circuit are controlled each circuit and are repeated a, b operation, reach setting value up to the data number of gathering and store;

D, FPGA circuit send CTL4 and order to coaxswitch, and CHA or CHB passage and test line plate are separated;

E, the test of FPGA circuit transmission are simultaneously finished look-at-me to CPU, notice CPU reading of data.

(2) if the user selects the differential impedance test mode, promptly the differential line impedance on the wiring board is tested, then need successively to use CHA and CHB passage, concrete operations are as follows:

At first use the CHA passage:

A, fpga logic control circuit send CTL1 and order to coaxswitch, send initiation command then to step pulse generation circuit;

The step pulse signal that b, pulse generating circuit produce is delivered on the test line plate via the CHA passage, receives this signal by receiving circuit afterwards through reflection, and converts digital signal to by signal acquisition module, stores in the FIFO storer;

C, fpga logic control circuit repeat a, b repeatedly, up to gathering and store into the data of setting number;

Use the CHB passage then:

D, fpga logic control circuit send CTL2 and order to coaxswitch, send initiation command then to step pulse generation circuit;

The pulse signal that e, step pulse generation circuit produce is delivered on the test line plate via the CHB passage, receives this signal by receiving circuit afterwards through reflection, and converts digital signal to by signal acquisition module, stores in the FIFO storer.

F, logic control circuit repeat d, e repeatedly, up to gathering and store into the data of setting number; Use CHA and CHB passage at last simultaneously:

G, logic control circuit continue to send CTL3 orders to coaxswitch, sends initiation command then to pulse generating circuit;

The pulse signal that h, pulse generating circuit produce is delivered on the test line plate via CHA, receives this signal by receiving circuit afterwards through reflection, and converts digital signal to by signal acquisition module, stores in the FIFO storer;

I, logic control circuit repeat g, h repeatedly, up to the collection of ADC analog to digital conversion circuit and store into and set a logarithmic data, send and interrupt to CPU;

J, FPGA circuit send CTL4 and order to coaxswitch, and CHA or CHB passage and test line plate are separated.

Step 7, CPU receives the data that read after the look-at-me that the final test that sends of FPGA finishes in the FIFO storer, the splicing sample waveform calculates the test impedance, adopts the test of average mode can also obtain mean value, maximal value, minimum value, standard deviation.Adopt the difference test mode can obtain even mould and differential impedance result.Last CPU compares according to the characteristic impedance value and the permissible range of wiring board design, draws " qualified " and " defective " result.

Step 8, after the single test point end of test (EOT), PC reads the data and the result of the processing of CPU, shows to survey this test point waveform and test result, and generates form, prints.After single test point test was finished, the user can select to suspend, stop or continuing test on PC.If select to continue, software calls the test parameter of next test point automatically, prepares test next time, and the user selects beginning, and operating procedure 3～8 is automatically just tested, processing, display result and generation form automatically.

The concrete computation process of CPU is described as follows to Fig. 7 in conjunction with Fig. 3:

The step pulse voltage of known emission is V _p, output impedance is R _S, through the switching of coaxswitch, carrying out three tests, step pulse is loaded into CHA, CHB respectively and is loaded into simultaneously on CHA and the CHB; Pulse receiving circuit receives to be handled and computing through CPU after reflected signal is handled again, can obtain three voltage V successively _RefA, V _RefBAnd V _RefABIf Z _eBe the common code impedance of symmetric difference output line, Z _xBe the mutual impedance between its two independent output line, Z _oDifferential impedance for the symmetric difference transmission line.

When step pulse is loaded into CHA and CHB, can obtain expression formula (1) according to Fig. 7

$\frac{\frac{1}{2}{\mathrm{<figure-callout\; id="1"\; label="Z\; e"\; filenames="Y2008202042590015H1.png,Y2008202042590016H2.png"\; state="\{\{state\}\}">Z</figure-callout>}}_e}{\frac{1}{2}{Z}_e+R_S}=\frac{V_{\mathrm{refAB}}}{V_p}---\left(1\right)$

Calculation expression (1) can obtain Z _eThe result

$Z_e=\frac{V_{\mathrm{refAB}}\&times;R_S\&times;2}{V_p-V_{\mathrm{refAB}}}---\left(2\right)$

When step pulse only is loaded into CHA,, set an intermediate variable Z according to Fig. 5 _T1Be Z among Fig. 5 _e,

Z _xThe equiva lent impedance of three resistor networks, same, when step pulse only is loaded into CHB, set an intermediate variable Z _T2Be Z among Fig. 5 _e,

Z _xThe equiva lent impedance of three resistor networks.

Equivalent electrical circuit according to Fig. 5 can obtain expression formula

So have:

$\frac{Z_{t1}}{{\mathrm{<figure-callout\; id="1"\; label="Z\; t"\; filenames="Y2008202042590015H1.png,Y2008202042590016H2.png"\; state="\{\{state\}\}">Z</figure-callout>}}_t+R_S}=\frac{V_{\mathrm{refA}}}{V_p}---\left(3\right)$

$\frac{Z_{t2}}{{\mathrm{<figure-callout\; id="2"\; label="Z\; t"\; filenames="Y2008202042590015H1.png"\; state="\{\{state\}\}">Z</figure-callout>}}_t+R_S}=\frac{V_{\mathrm{refB}}}{V_p}---\left(4\right)$

Calculating (3), (4) can obtain Z _T1, Z _T2Expression formula

${\mathrm{<figure-callout\; id="1"\; label="Z\; t"\; filenames="Y2008202042590015H1.png,Y2008202042590016H2.png"\; state="\{\{state\}\}">Z</figure-callout>}}_t=\frac{V_{\mathrm{refA}}\&times;R_S}{V_p-V_{\mathrm{refA}}}---\left(5\right)$

${\mathrm{<figure-callout\; id="2"\; label="Z\; t"\; filenames="Y2008202042590015H1.png"\; state="\{\{state\}\}">Z</figure-callout>}}_t=\frac{V_{\mathrm{refB}}\&times;R_S}{V_p-V_{\mathrm{refB}}}---\left(6\right)$

Equivalent electrical circuit according to Fig. 5 can also obtain expression formula (7), (8)

${\mathrm{<figure-callout\; id="1"\; label="Z\; t"\; filenames="Y2008202042590015H1.png,Y2008202042590016H2.png"\; state="\{\{state\}\}">Z</figure-callout>}}_t=\frac{(Z_x+\frac{1}{2}{Z}_e)\&times;Z_e}{Z_x+\frac{1}{2}{Z}_e+Z_e}---\left(7\right)$

${\mathrm{<figure-callout\; id="2"\; label="Z\; t"\; filenames="Y2008202042590015H1.png"\; state="\{\{state\}\}">Z</figure-callout>}}_t=\frac{(Z_x+\frac{1}{2}{Z}_e)\&times;Z_e}{Z_x+\frac{1}{2}{Z}_e+Z_e}---\left(8\right)$

Calculation expression (7), (8) can obtain Z _xExpression formula (9)

$Z_x=\frac{Z_e(3Z_{t1}-2Z_e)}{2(Z_e-Z_{t1})}=\frac{Z_e(3Z_{t2}-2Z_e)}{2(Z_e-Z_{t2})}---\left(9\right)$

(5) or (6) formula is updated to (9) formula just can obtains Z _xNet result.

Z _oBe the differential impedance of symmetric difference transmission line, then can obtain final differential impedance result of calculation.

$Z_o=\frac{2Z_e\&times;Z_x}{2Z_e+Z_x}---\left(10\right)$

When expression formula (5) has drawn step pulse and has only loaded on CHA, the CHA test impedance results that CPU calculates.

When expression formula (6) has drawn step pulse and has only loaded on CHB, the CHB test impedance results that CPU calculates.

Expression formula (10) has drawn the final differential impedance result of calculation of difference characteristic impedance test.

When the symmetry of symmetric difference transmission line was reasonable, the impedance curve of (8), (9) two test result draftings overlapped basically, if symmetry is not good, test result just has than mistake.Also can obtain asymmetry (unbalance) result of symmetric difference transmission line according to expression formula (8), (9), shown in expression formula (11).

$U_b=\frac{Z_{t1}-Z_{t2}}{\frac{{\mathrm{<figure-callout\; id="1"\; label="Z\; t"\; filenames="Y2008202042590015H1.png,Y2008202042590016H2.png"\; state="\{\{state\}\}">Z</figure-callout>}}_t+{\mathrm{<figure-callout\; id="2"\; label="Z\; t"\; filenames="Y2008202042590015H1.png"\; state="\{\{state\}\}">Z</figure-callout>}}_t}{2}}\&times;100\%---\left(11\right)$

The user is according to designing requirement, and the asymmetry scope that can self-defined symmetric difference transmission line allows if surpass this scope, shows that then this symmetric difference transmission line does not meet the setting requirement.

In sum, wiring board characteristic impedance proving installation disclosed in the utility model and method of testing adopt the design of intelligent and robotization, adopt Test Host to finish test process jointly in conjunction with PC, PC adopts common computer to get final product, move particular software application on the PC, it is simple, convenient to utilize the simple friendly man-machine interface of PC to make, and has simplified wiring board characteristic impedance testing procedure, reduce the difficulty of operation, improved work efficiency greatly.Test Host has substituted expensive domain reflectometer simultaneously, effectively reduces testing cost.

Need to prove; embodiment and method in the above device only are preferable embodiment of the utility model and method of work thereof; it can not be interpreted as restriction to the utility model protection domain; do not breaking away under the utility model design prerequisite, any impartial the variation with modification that the utility model is done all belongs to protection domain of the present utility model.

Claims (5)

1, a kind of wiring board characteristic impedance proving installation comprises Test Host, probe, PC, printer and runs on analysis software on the PC, and it is characterized in that: described Test Host comprises at least:

One pulse generating circuit is connected with Logic control module, is used to produce the step pulse signal;

One coaxial switch is connected in pulse generating circuit, pulse receiving circuit and patches between the output port of probe, is subjected to Logic control module control switch test mode, realizes importing and exporting of signal;

One pulse receiving circuit is connected between signal acquisition module and the coaxswitch, the pulse signal that the line reflection to be measured that is used to sample is returned;

One signal acquisition module is connected between CPU processing module and the pulse receiving circuit, is used for the reflected signal filtering that receives, amplifies and change into digital signal and send into storer and store, and reads for CPU;

One Logic control module is connected with the CPU processing module, and control is coordinated in the work of cpu instruction paired pulses generation circuit, pulse receiving circuit, signal acquisition module and coaxswitch of accepting;

The CPU processing module is connected communication with PC, accepts test control command and test parameter that PC sends, and the order of translation PC sends to Logic control module.

2, wiring board characteristic impedance proving installation according to claim 1, it is characterized in that: pin S1, the S5 of described coaxswitch K connect pull-up resistor respectively, and pin S2, S4 connect two output channel CHA, CHB end respectively; Pin S3 connects pulse generating circuit; 3 control pin K1+, K2+, the K-of coaxswitch K all connect logic control circuit; Logic control circuit control coaxswitch switches, and pin S2 and/or S4 can be connected to pin S3, and the driving pulse of the pulse generating circuit output that is connected in the S3 place is loaded on output channel CHA and/or the CHB.

3, wiring board characteristic impedance proving installation according to claim 2, it is characterized in that: described probe comprises single end testing probe and difference test probe.

4, wiring board characteristic impedance proving installation according to claim 3, it is characterized in that: described pulse generating circuit adopts periodically rect.p. generation circuit, the step pulse signal rising edge rise time scope that this circuit produced is 120ps～160ps, the pulse amplitude scope is 200mV～300mV, and frequency range is 10kHz～200kHz.

5, according to claim 1 or 4 described wiring board characteristic impedance proving installations, it is characterized in that: described CPU processing module comprises digital signal processor DSP and connected ARM microprocessor, described CPU processing module by the ARM microprocessor up with the PC communication, by digital signal processor DSP descending with Logic control module communication, and data in the acquisition memory.

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