CN108665922B - Variable bidirectional digital delay method applied to radar simulation - Google Patents
Variable bidirectional digital delay method applied to radar simulation Download PDFInfo
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- CN108665922B CN108665922B CN201810372837.7A CN201810372837A CN108665922B CN 108665922 B CN108665922 B CN 108665922B CN 201810372837 A CN201810372837 A CN 201810372837A CN 108665922 B CN108665922 B CN 108665922B
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Abstract
The invention discloses a variable bidirectional digital delay method applied to radar simulation, belongs to the signal processing technology, and particularly relates to a digital delay method. The variable bidirectional digital delay implementation method based on the single-port DRAM and the single-time clock has a simple design structure, and can implement delay only by setting control words and circularly counting to the control words in engineering application. Because the invention adopts the single-time working clock, the achievable working frequency can reach the highest working frequency of the FPGA. When the delay amount is increased or decreased, only the value of the delay amount after the increase or decrease needs to be set, and the digital delay method is simple and efficient and has higher resolution.
Description
Technical Field
The invention belongs to the signal processing technology, and particularly relates to a digital delay method.
Background
Digital signal delay has a wide application in digital signal processing, and has a wide application in the fields of radar, communication and the like.
The digital signal delay is realized by two methods, namely an analog circuit and a digital circuit, and generally speaking, the method for realizing the digital signal delay by using the traditional analog circuit technology is complex, poor in controllability and low in integration level. Typical methods for digital circuit implementation are those using a single FIFO, double clock based bi-directional digital delay. The method controls the read-write enable signal of the FIFO by using 2 times of clock frequency. In the FPGA technology, due to the limited clock frequency, if the read-write enable signal of the FIFO is controlled by 2 times of the clock, the minimum unit of digital delay is greatly limited. For example, in the implementation of an FPGA platform, the internal clock can reach 500MHz at the most, and then the maximum frequency that can be reached by the signal delay is 250MHz in practice. In addition, the design implementation using a single FIFO double clock results in higher design complexity because of the multiple control lines involved.
In engineering applications, integration is considered for realizing digital signal delay, the minimum delay unit (a main reason of delay precision) is also considered, and the complexity of design is further considered. It is necessary how to implement a variable bi-directional digital delay in a more simple way.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a simple and efficient digital delay method with higher resolution.
The variable bidirectional digital delay implementation method based on the single-port DRAM and the single-time clock has a simple design structure, and can implement delay only by setting control words and circularly counting to the control words in engineering application. Because the invention adopts the single-time working clock, the achievable working frequency can reach the highest working frequency of the FPGA. The technical scheme of the invention is that the variable bidirectional digital delay method applied to radar simulation comprises the following steps:
step 2: determining a delay quantity N of radar simulation;
and step 3: reading and writing the memory of the DRAM according to the delay amount, wherein the mode is reading first and then writing;
(1) when the delay amount is N, the maximum depth of the pointer is N:
first beat: reading out data '0' at the 1 st position in the DRAM, writing the data '0' into the radar simulation 1 st data0, and jumping to the 2 nd position by a pointer;
the second beat: reading out the data '0' at the 2 nd position in the DRAM, writing the data '0' into the radar simulation 2 nd data1, and jumping the pointer to the 3 rd position;
and (3) taking a third beat: reading out data '0' at the 3 rd position in the DRAM, writing the data '0' into radar simulation data2 at the 3 rd position, and jumping to the 4 th position by a pointer;
……
the Nth beat: reading data '0' at the Nth position in the DRAM, writing the data into a radar to simulate data dataN-1 of the Nth position, and jumping to the 1 st position by a pointer;
beat N + 1: reading data 'data 0' at the 1 st position in a DRAM, writing the data into radar simulation data N +1, and jumping to the 2 nd position by a pointer;
beat N + 2: reading data 'data 1' at the 2 nd position in a DRAM, writing the data into radar simulation data N +2, and jumping to the 3 rd position by a pointer;
……
the method is that after the pointer points to the Nth position in the DRAM memory, the next position jumps to the 1 st position in the DRAM memory, and the method is adopted to delay the subsequent radar analog signals in sequence;
(2) when the delay amount is changed from N to N + M, the maximum depth of the pointer is N + M:
firstly, sequentially jumping the pointers from the 1 st position to the Nth position in a DRAM, when the pointers point to the Nth position, jumping to the N +1 th position next time, reading data '0' of the N +1 th position in the DRAM, and writing the data into the current T-th analog data of the radar;
then sequentially jumping the pointer from the N +1 th position to the N + M th position in the DRAM, when the pointer points to the N + M th position, jumping to the 1 st position next time, reading data of the 1 st position in the DRAM, and writing the data into T + M +1 analog data of the current radar; sequentially jumping the pointers from the 1 st position to the N + M th position in the DRAM; when the pointer points to the (N + M) th position, jumping to the 1 st position next time, reading data of the 1 st position in the DRAM memory, and writing the data into the analog data of the current radar;
(3) when the delay amount is changed from N to N-M, the maximum depth of the pointer is N-M:
firstly, sequentially jumping the pointers from the 1 st position to the Nth position in a DRAM, and when the pointers point to the Nth position, jumping to the 1 st position next time;
then sequentially jumping the pointers from the 1 st position to the N-M th position in the DRAM, and jumping to the 1 st position next time when the pointers point to the N-M th position; sequentially jumping the pointers from the 1 st position to the N-M position in the DRAM; when the pointer points to the Nth-M position, jumping to the 1 st position next time; and after each jump, the pointer reads and writes the radar simulation data according to a mode of reading first and then writing.
When the delay amount is increased or decreased, the invention only needs to set the value of the delay amount after the increase or decrease, and is a simple and efficient digital delay method with higher resolution.
Drawings
FIG. 1 is a schematic diagram of an overall implementation architecture of the present invention;
FIG. 2 is a timing diagram of the delay amount from N to (N + M) according to the present invention;
FIG. 3 is a timing diagram of the present invention for a delay amount from N to (N-M);
fig. 4 to 18 are schematic views of specific steps in the embodiment.
Detailed Description
1. A synchronization signal of the signal is set, the synchronization signal being synchronized with the signal.
Setting the read-write mode to read first and then write, as shown in FIG. 4;
3. the loop counts to the size specified by the control word, the pointer points to the 0 position after reaching the size specified by the control word, and data0, data1, … … data (N-1) are data written into DRAM
Outputting data when the delay amount is N:
first beat: the input data is covered by the data of the original address 0, and the DRAM outputs the data0 of the address 0, as shown in FIG. 5;
the second beat: the input data is covered with the data of the original address 1, and the DRAM outputs the data0 of the address 1, as shown in FIG. 6;
the Nth beat: the input data is to cover the data of the original address (N-1), and the DRAM outputs the data0 of the address (N-1), as shown in FIG. 7;
beat (N + 1): the pointer jumps from the position of the address (N-1) to the address 0, the input data overwrites the data of the original address 0, and the DRAM outputs the data0 of the address 0, as shown in FIG. 8;
repeating the above operation, the pointer reaches the address (N-1) position and then jumps to the address 0 position.
Delay amount is (N + M) output data:
how to realize the delay amount (N + M) on the basis of the delay amount N:
when the delay amount is N, the data format inside the DRAM is as shown in fig. 9;
when the control word is (N + M), the maximum depth of the pointer becomes (N + M-1);
on the basis of the delay amount N:
in the first beat, input data dataN covers the data of the original address N, and DRAM outputs data0 of the address N, as shown in FIG. 10;
in the second beat, the input data (N +1) covers the data of the original address (N +1), and the DRAM outputs the data0 of the address (N +1), as shown in FIG. 11;
the Mth beat: the input data (N + M-1) covers the data of the original address (N + M-1), and the DRAM outputs the data0 of the address (N + M-1), as shown in FIG. 12;
beat (M + 1): the input data (N + M) overwrites the data of the original address 0, and the DRAM outputs the data0 of the address (N + M-1), as shown in fig. 13;
repeating the above operations, and jumping to the address 0 position when the pointer reaches the address (N + M-1) position;
note that in the data stream, from the delay amount N to the delay amount (N + M-1), in the signal of the delay amount N, the data stream realizes an increase in the delay amount in such a manner that M0 s are added;
delay amount is (N-M) output data:
(M across data).
How to realize the delay amount (N-M) on the basis of the delay amount N:
when the delay amount is N, the data format inside the DRAM is as shown in fig. 14:
when the control word is (N-M), the maximum depth of the pointer becomes (N-M-1);
on the basis of the delay amount N:
in the first beat, the input data dataN overwrites the data of the original address 0, and the DRAM outputs the data0 of the address 0, as shown in FIG. 15;
in the second beat, the input data (N +1) overwrites the data of the original address 1, and the DRAM outputs the data1 of the address 1, as shown in fig. 16,
in the (N-M) th beat, the input data (2N-M-1) covers the data of the original address (N-M-1), and the DRAM outputs the data (N-M-1) of the address (N-M-1), as shown in FIG. 17;
in the (N-M +1) th beat, the input data (2N-M) covers the data of the original address 0, and the DRAM outputs the data dataN of the address 0, as shown in FIG. 18;
repeating the above operation, the pointer reaches the address (N-M-1) position and then jumps to the address 0 position.
Claims (1)
1. A variable two-way digital delay method for radar simulation, the method comprising:
step 1, initializing all memory data of the DRAM to be 0, and aiming at a1 st position in the DRAM;
step 2: determining a delay quantity N of radar simulation;
and step 3: reading and writing the memory of the DRAM according to the delay amount, wherein the mode is reading first and then writing;
(1) when the delay amount is N, the maximum depth of the pointer is N:
first beat: reading out data '0' at the 1 st position in the DRAM, writing the data '0' into the radar simulation 1 st data0, and jumping to the 2 nd position by a pointer;
the second beat: reading out the data '0' at the 2 nd position in the DRAM, writing the data '0' into the radar simulation 2 nd data1, and jumping the pointer to the 3 rd position;
and (3) taking a third beat: reading out data '0' at the 3 rd position in the DRAM, writing the data '0' into radar simulation data2 at the 3 rd position, and jumping to the 4 th position by a pointer;
……
the Nth beat: reading data '0' at the Nth position in the DRAM, writing the data into a radar to simulate data dataN-1 of the Nth position, and jumping to the 1 st position by a pointer;
beat N + 1: reading data 'data 0' at the 1 st position in a DRAM, writing the data into radar simulation data N, and jumping the pointer to the 2 nd position;
beat N + 2: reading data 'data 1' at the 2 nd position in a DRAM, writing the data into radar simulation data N +1, and jumping to the 3 rd position by a pointer;
……
in the method, after the pointer points to the Nth position in the DRAM, the next position jumps to the 1 st position in the DRAM, and the method is adopted to sequentially delay the subsequent radar analog signals;
(2) when the delay amount is changed from N to N + M, the maximum depth of the pointer is N + M:
firstly, sequentially jumping the pointers from the 1 st position to the Nth position in a DRAM, when the pointers point to the Nth position, jumping to the N +1 th position next time, reading data '0' of the N +1 th position in the DRAM, and writing the data into the Nth analog data of the current radar;
then sequentially jumping the pointer from the N +1 th position to the N + M th position in the DRAM, when the pointer points to the N + M th position, jumping to the 1 st position next time, reading data of the 1 st position in the DRAM, and writing the data into the N + M +1 analog data of the current radar; sequentially jumping the pointers from the 1 st position to the N + M th position in the DRAM; when the pointer points to the (N + M) th position, jumping to the 1 st position next time, reading data of the 1 st position in the DRAM memory, and writing the data into the analog data of the current radar;
(3) when the delay amount is changed from N to N-M, the maximum depth of the pointer is N-M:
firstly, sequentially jumping the pointers from the 1 st position to the Nth position in a DRAM, and when the pointers point to the Nth position, jumping to the 1 st position next time;
then sequentially jumping the pointers from the 1 st position to the N-M th position in the DRAM, and jumping to the 1 st position next time when the pointers point to the N-M th position; sequentially jumping the pointers from the 1 st position to the N-M position in the DRAM; when the pointer points to the Nth-M position, jumping to the 1 st position next time; and after each jump, the pointer reads and writes the radar simulation data according to a mode of reading first and then writing.
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| CN102667731A (en) * | 2009-12-25 | 2012-09-12 | 富士通株式会社 | Signal restoration circuit, latency adjustment circuit, memory controller, processor, computer, signal restoration method, and latency adjustment method |
| CN102778673A (en) * | 2012-07-24 | 2012-11-14 | 清华大学 | Radar return signal high-precision distance simulation method and device as well as target simulator |
| CN104022775A (en) * | 2014-06-02 | 2014-09-03 | 复旦大学 | FIFO protocol based digital interface circuit for SerDes technology |
| CN104216462A (en) * | 2014-08-27 | 2014-12-17 | 电子科技大学 | Large-dynamic and high-precision programmable time delay device based on FPGA (field programmable gate array) |
| CN104731550A (en) * | 2015-03-12 | 2015-06-24 | 电子科技大学 | Double-clock bidirectional digital delay method based on single FIFO |
| CN105676198A (en) * | 2016-03-31 | 2016-06-15 | 电子科技大学 | Echo pulse delay generating device for pulse type radar test |
| CN106680786A (en) * | 2017-03-20 | 2017-05-17 | 湖南鼎方电子科技有限公司 | Real time target information modulation method for radar jammer |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2005076035A1 (en) * | 2004-02-09 | 2005-08-18 | Anritsu Corporation | Radar apparatus |
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- 2018-04-24 CN CN201810372837.7A patent/CN108665922B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4129867A (en) * | 1977-04-28 | 1978-12-12 | Motorola Inc. | Multi-pulse modulator for radar transponder |
| CN102667731A (en) * | 2009-12-25 | 2012-09-12 | 富士通株式会社 | Signal restoration circuit, latency adjustment circuit, memory controller, processor, computer, signal restoration method, and latency adjustment method |
| CN102778673A (en) * | 2012-07-24 | 2012-11-14 | 清华大学 | Radar return signal high-precision distance simulation method and device as well as target simulator |
| CN104022775A (en) * | 2014-06-02 | 2014-09-03 | 复旦大学 | FIFO protocol based digital interface circuit for SerDes technology |
| CN104216462A (en) * | 2014-08-27 | 2014-12-17 | 电子科技大学 | Large-dynamic and high-precision programmable time delay device based on FPGA (field programmable gate array) |
| CN104731550A (en) * | 2015-03-12 | 2015-06-24 | 电子科技大学 | Double-clock bidirectional digital delay method based on single FIFO |
| CN105676198A (en) * | 2016-03-31 | 2016-06-15 | 电子科技大学 | Echo pulse delay generating device for pulse type radar test |
| CN106680786A (en) * | 2017-03-20 | 2017-05-17 | 湖南鼎方电子科技有限公司 | Real time target information modulation method for radar jammer |
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