CN109946666A - MMW RADAR SIGNAL USING processing system based on MPSoC - Google Patents
MMW RADAR SIGNAL USING processing system based on MPSoC Download PDFInfo
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Abstract
The MMW RADAR SIGNAL USING processing system based on MPSoC that the invention discloses a kind of comprising host computer (1) and signal processor (2).Host computer is used for transmission initialization bookbinding parameter, testing result and target information between signal processor；Signal processor includes master controller and functional module, its master controller realizes the function of traditional double-core framework using single-chip, A/D acquisition control module (21) is for the sampling to analogue echo in functional module, the end PL preprocessing module (22) is for carrying out preprocessing tasks, arm processor module (23) is used for system electrification initial configuration and object detection task, communications interface control module (24) is for serial communication and control AXI bus and interruption, the present invention is under the premise of guaranteeing Radar Signal Processing System performance, realize signal processor miniaturization, reduce power consumption, improve integrated level, it can be widely applied to the Detection And Tracking of target.
Description
Technical field
The invention belongs to Radar Signal Processing Technology fields, are related specifically to MMW RADAR SIGNAL USING processor system, can
With the Detection And Tracking for target.
Background technique
Millimetre-wave radar has the characteristics that round-the-clock, round-the-clock, operating distance is remote and microwave imaging, is indispensable system
Lead detecting devices, and key of the signal processor as entire radar seeker, directly determine the performance of guidance detecting devices.
In existing MMW RADAR SIGNAL USING processor technology, the hardware platform of mainstream is mostly using DSP+FPGA
Double-core framework, the Radar Signal Processing platform under this framework have very powerful operational capability and flexibility.But
There are following defects: first is that in terms of size, due to having complicated periphery using the framework and DSP and FPGA of double-core
Circuit, therefore this framework cannot achieve the requirement of miniaturization, collection degree is low, size is big；Second is that in power consumption, it is flat with hardware
The FPGA XC7VX485T of the high-performance multicore Floating-point DSP TMS320C6678 and XILINX company of the common TI company of platform is
Example, dynamic power consumption 15W of a piece of TMS320C6678 or so, and the power consumption of a piece of XC7VX485T is in 20W or so, so can not expire
The requirement of sufficient low-power consumption；Third is that the transmission rate of chip interface suffers from circuit board work in terms of processor communication speed
The influence of the factors such as skill and environment causes the overall performance of processor to decline；Fourth is that in terms of cost, the framework of double-core is inevitable
It will increase component cost, increase the printed circuit board number of plies, be unfavorable for cost control.
Summary of the invention
It is an object of the invention to provide a kind of millimeter wave thunder based on MPSoC for deficiency present in prior art
Up to signal processing system, under the premise of guaranteeing Assessment of Radar Signal Processor Performance, miniaturization, low-power consumption and highly integrated property are realized
Purpose of design, while shortening the development cycle, reducing research and development cost.
To achieve the above object, present system includes: host computer 1 and signal processor 2, and host computer 1 is used for signal
Processor 2 sends initialization bookbinding parameter, and receives the testing result of the return of signal processor 2, realizes the real-time sight to target
It examines, which is characterized in that signal processor 2 includes: master controller and functional module；
The functional module includes:
A/D acquisition control module 21 is sampled for the analog echo signal to radar, converts thereof into digital letter
Number, it is sent to the end PL preprocessing module 22；
The end PL preprocessing module 22, the initialization bookbinding parameter sent for receiving host computer 1, the echo that sampling is obtained
Digital signal successively carries out Digital Down Convert, Fourier transformation, pulse compression, inverse Fourier transform, model selection, phase compensation
With the pretreatment of image mosaic, and by pretreated echo data with direct memory access dma mode pass through AXI bus interface
It is sent to arm processor system module 23；
Arm processor module 23, for carrying out power-up initializing configuration to system, and to the end PL preprocessing module 22
The echo data of transmission carries out target detection, and will test result and pass host computer 1 back by the end PL preprocessing module 22；
Communications interface control module 24, in the serial communication and chip of the end PL preprocessing module 22 and host computer 1
The AXI bus marco and interruption of the portion end PL preprocessing module 22 and arm processor module 23 control, and realize and join to initialization bookbinding
The transmission of number, echo data and testing result；
The master controller, using the ZYNQ Series FPGA chip of new generation of ZU9EG, which handles complete ARM
Device system on chip and 16nm low-power consumption programmable logic are closely integrated together, can realize traditional double-core hardware on a single chip
The function of platform architecture, the end the PL preprocessing module 22 realize that the arm processor module 23 is based on based on programmable logic resource
Arm processor system on chip is realized.
The invention has the following advantages that
First, the present invention uses the ZYNQ Series FPGA chip of new generation of model ZU9EG, will be complete using the chip
Arm processor system on chip and 16nm low-power consumption programmable logic are closely integrated function together as master controller, make letter
Number processor has the characteristics that rich hardware resource, scalability are strong, high-speed interface type is more, while can plug-in a large amount of storage
Device, to meet requirement of the system to processing big data quantity and operation complicated algorithm；
Second, master controller chip used in the present invention embeds multiple arm processor kernels, utilizes with traditional FPGA
Soft core, which carries out SOPC design, very big difference, can greatly promote the overall performance of SOPC, while saving fpga logic resource；
Third, the signal processor in the present invention using single-chip as master controller so that the present invention can be achieved it is small-sized
Change, the requirement of low-power consumption and highly integrated property, overcomes the prior art due to using muti-piece board and cause the anti-external interference of system
The low disadvantage of ability, improves the stability of signal processor system；
4th, the present invention in the end PL preprocessing module 22 and arm processor system module 23 between communication use core
AXI bus protocol inside piece transmits data by direct memory access dma mode, and the processor avoided between multi-chip is logical
Transmission speed is slow caused by believing, Handshake Protocol is complicated and it is easy by external environmental interference the problems such as, the present invention can be effectively improved
Real-time, meet requirement of the radar signal processor system to high real-time and quick response；
5th, the demand for MMW RADAR SIGNAL USING processing system to complex work mode, the present invention in the end PL it is pre-
Processing module 22 and arm processor system module 23 realize the inspection to target using pulse Doppler system and step frequency system
It surveys, overcomes the simple disadvantage of prior art function, improve reliability and flexibility of the invention；
6th, signal processor 2 of the invention and host computer 1 have good human-computer interaction function, the ginseng such as operating mode
Several and real-time processing result dynamically can be adjusted and be shown.
Detailed description of the invention
Fig. 1 is structural block diagram of the invention；
Fig. 2 is the transmission relational graph in the present invention between A/D acquisition control module 21 and the end PL preprocessing module 22；
Fig. 3 is the transmission relational graph in the present invention between arm processor system module 23 and the end PL preprocessing module 22；
Fig. 4 is the connection schematic diagram between host computer 1 and signal processor 2 of the invention.
Specific embodiment:
The present invention is described in further detail with reference to the accompanying drawing.
Referring to Fig.1, present system includes: host computer 1 and signal processor 2, in which:
Host computer 1 for sending initialization bookbinding parameter to signal processor 2, while receiving the detection of signal processor 2
As a result it carries out working state of system with target information, real-time observation of the realization to target and controls and monitors, host computer in this example
1 is the general purpose PC used.
Signal processor 2, including master controller and functional module, in which:
Master controller uses the ZYNQ Series FPGA chip of new generation of model ZU9EG, which will be at complete ARM
Reason device system on chip PS and 16nm low-power consumption programmable logic PL is closely integrated together, is realized by internal AXI bus interface
High-speed data communication, wherein the end PS includes four core ARM Cortex-A53 application processing unit APU, double-core ARM Cortex-R5
Real-time processing unit RPU, ARM Mali-400 graphics processing unit GPU, a large amount of on piece cache and ocm storage resource and
PCIe, USB3.0, SATA, GTR high-speed interface, while there is the Integrated Management Platform PMU of multiple power domains, and plug-in a piece of
For the 8GB EMMC of memory image file, the operation of operating system is realized；The part the PL FPGA resource general with Xilinx is patrolled
It collects identical comprising: 599550 logic units, 548160 triggers, 214604 LUT, 2520 DSP Slices,
The Block RAM of the Distributed RAM and 32.1Mb of 8.8Mb, 4 Clock management module CM T, 24 speed are up to
The high-speed transceiver GTH of 16.3Gb/s shares 1156 I/O pins.
Functional module includes: A/D acquisition control module 21, the end PL preprocessing module 22, arm processor system module 23
With communications interface control module 24, in which:
A/D acquisition control module 21 converts thereof into digital signal, then will for sampling to analog echo signal
Data after sampling are sent to the end PL preprocessing module 22.The module uses the AD9694 chip of ADI company, which is a
Four-way, 14,500MSPS analog-digital converter, built-in piece internal inner ring and sampling hold circuit, specifically for low-power consumption, small
Size and ease for use and design.AD9694 is for wide input bandwidth, high sampling rate, the outstanding linearity and small package low-power consumption
And optimize.This four-way ADC kernel is integrated with output error correction logic using multistage, differential pipeline framework.Each ADC
Wide bandwidth buffering input is all had, supports the optionally various input ranges of user.Integrated reference voltage source can simplify design, simulation
Input and clock signal are differential input signal.AD9694 chip interior has four digital down-converter units, the unit by
NCO, half-band filter and FIR filter, gain control and complex signal conversion real signal module composition, can to the data of sampling into
Row filtering and extraction processing, support the input and output of flexible real signal and complex signal to select, and can greatly simplify PL pretreatment
The data processing algorithm of module 22.
The end PL preprocessing module 22, the initialization bookbinding parameter sent for receiving host computer 1, the echo that sampling is obtained
Digital signal is pre-processed, and pretreated echo data is sent to arm processor system module 23 comprising: number
Word down coversion submodule 221, pulse compression submodule 222, moving-target detection MTD submodule 223 and image mosaic submodule
224.The initialization bookbinding parameter information for waiting host computer 1 to send after signal processor 2 powers on, the end PL preprocessing module 22
According to the operating mode of the initialization information selection signal processor 2 received, its working principle is that: Digital Down Convert submodule
221 A/D acquisition control module 21 is sampled after data be mixed, filtered and extraction operation；The data after extraction are passed again
Be sent to pulse compression submodule 222, according to different mode be sequentially completed data point-variable Fourier transformation FFT operation,
With filtering and inverse Fourier transform IFFT operation；Pulse is compressed into the data transmission after 222 operation of submodule to moving-target again
MTD submodule 223 is detected, which is first stored in controller piece for the data adopted in entire frame synchronizing signal in a manner of rattling
Upper Block RAM, after a frame data have stored, go forward side by side by same distance unit reads data take action target detection MTD or
Inverse Fourier transform IFFT processing, then processing result is rattled and is stored in the end PL preprocessing module (22) plug-in DDR4 memory
It is interior；Then data are read into obtaining in the complete paired data one-dimensional range profile of image mosaic submodule 224 again with same distance unit
It takes, is used for subsequent algorithm of target detection；Finally pretreated echo data is passed through with direct memory access dma mode
AXI bus interface is sent to arm processor system module 23.
Arm processor system module 23, for carrying out power-up initializing configuration to system, and to the end PL preprocessing module
22 echo datas sent carry out target detection, and will test result and pass host computer 1 back by the end PL preprocessing module 22, wrap
It includes: detection sub-module 231 and identification submodule 232.Wherein, power-up initializing configuration includes: to power module electric sequence
Control, the initialization of direct memory access DMA, the initialization of clock chip and A/D chip initialization.Arm processor system
The echo data that module 23 receives is divided into "and" circuit-switched data and " and difference is poor " three data, working principle according to operating mode
Are as follows: under search pattern, detection sub-module 231 handles "and" circuit-switched data, obtains existing in the one-dimensional picture of this section of high-resolution
Then the number of target and corresponding distance unit position take each N number of distance before and after each target respective distances cell position single
The data of member carry out the interception of target phase high-resolution lattice image, and wherein the value of N is by distance resolution and the mesh of being hit
Target length determines, then falls into a trap the signal to noise ratio of evidence of counting in identification submodule 232, and obtain the accurate position of target by gravity model appoach
Confidence breath；Under tracing mode, detection sub-module 231 is to " and difference is poor " three data "and" number in the case where doing same search pattern respectively
According to identical algorithm, and each target phase strong scattering point number is calculated, then to two " poor " numbers in identification submodule 232
According to calculating separately azimuth angle error and pitching angle error, and the speed of target is calculated using alpha-beta filtering and predicts a fortune under target
Dynamic position, finally will test result and passes host computer 1 back.
Communications interface control module 24, for realizing the serial communication of PL preprocessing module 22 and host computer 1, and to master
The control of AXI bus and interruption inside controller chip.Wherein serial communication uses RS422 interface protocol, passes through ADM2587
Chip realizes transmission of the differential signal to single-ended conversion, for parameter, data and detection information；Master controller chip interior
AXI bus and interruption control are for being transferred to arm processor system module 23, and reception for the data of PL preprocessing module 22
The target information that arm processor system module 23 is sent.
With reference to Fig. 2, the connection between A/D acquisition control module 21 and the end PL preprocessing module 22 is further described
Description.
A/D acquisition control module 21 use AD9694 chip be by JESD204B encode serial digital output, then with
The GTH high-speed interface of the end PL preprocessing module 22 is connected, while the SPI configuration pin of AD9694 and the common I/O at the end PL draw
Foot is connected.External reference clock is inputted by SMA interface, is believed using the clock for obtaining three road coherents after clock chip frequency multiplication
Number, sampling clock of the first via as A/D chip, control clock of second tunnel as GTH high-speed interface, third road is as the end PL
The data processing synchronised clock of preprocessing module 22.After system electrification, the end PL preprocessing module 22 is drawn firstly the need of by SPI
Foot carries out initiation parameter configuration, including operating mode, data format and the configuration of JESD204B interface to AD9694.A/D's adopts
Sample frequency is 480MHz, and data rate is 48MHz after the down coversion of chip interior and extraction, and the end PL preprocessing module 22 is logical
Cross the data progress follow-up signal algorithm pretreatment for receiving the input of GTH interface.
Referring to Fig. 3, the connection between arm processor system module 23 and the end PL preprocessing module 22 is made further
Bright description.
The data that the end PL preprocessing module 22 exports are divided into "and" circuit-switched data and " and difference is poor " three number according to operating mode
According to, while initiation parameter is sent to arm processor system module 23, arm processor system by the end PL preprocessing module 22
The target information that module 23 will also will test returns to PL preprocessing module 21, wants to guarantee that message transmission rate meets algorithm
It asks, the end PL preprocessing module 22 is respectively the IP kernel that " and difference is poor " three data respectively adds a direct memory access DMA, point
It is not denoted as DMA0, DMA1 and DMA2, it is logical with ARM processor system module 23 by the way of AXI bus high-speed interface and interruption
Letter.Wherein, AXI bus interface selects control interface agreement of the AXI4-stream as the end PL preprocessing module 22, and the end PL is pre-
Processing module 22 only carries out writing the control of data to two " poor " roads DMA1 and DMA2, and "and" road DMA0 should be sent initially
Change parameter and data, receives the information of detection target again.ARM processor system module 23 needs to deposit three direct memories
It takes the IP kernel of DMA to carry out initial configuration, and distributes enough read/write address spaces in its plug-in DDR4 for three data,
After the read-write interrupted to start direct memory access DMA generated by the end PL preprocessing module 22, each direct memory access
The read-write operation of DMA can also generate corresponding interruption when completing, and each parameter instruction respectively corresponds arm processor system module
An interrupt number in 23 can carry out different processing tasks when corresponding interruption generates.
Referring to Fig. 4, description is further described to the connection between host computer 1 and signal processor 2.
It is communicated between host computer 1 and signal processor 2 using the serial port protocol of RS422 interface, Configuration of baud rate is
115.2KSPS, eight bit data, no parity position, and realize differential signal to single-ended conversion by ADM2587 chip.When
After signal processor 2 powers on, host computer 1 needs to carry out signal processor 1 bookbinding of initiation parameter, including pulse repeats week
The parameters such as phase, pulse width, scheme control code and target range range.The transmission of data is according to certain frame format, every frame number
According to starting packet header be hexadecimal A5A51234A5A51234 fixed value, then send different initiation parameters.Work as signal
After the completion of processor 2 detects, the information of target can be carried out real-time display by host computer 1.The target information specifically transmitted includes: mesh
Mark number, the position of each target, the target phase high-resolution lattice image of interception, the signal to noise ratio of echo, the orientation of each target
The speed and next predicted position of angle error and pitching angle error and each target.
The entire working principle of this example is as follows:
Signal processor 2 in present system acquires and the data and reference clock handled are all by radar return mould
What quasi- device generated, signal processor 2 controls the defeated of the echo data of simulator by sending frame synchronization and pulse synchronous signal
Out.MMW RADAR SIGNAL USING processing system is divided into frequency modulation step mode and step frequency mode according to transmitted waveform, no matter signal
Which kind of operating mode is processing system be under, and MMW Seeker takes two kinds of working systems, i.e. broadband step frequency body
System and narrow-band impulse Doppler system, two kinds of working systems are all to carry out initialization bookbinding by host computer 1.In different Working moulds
Under formula and transmitted waveform parameter, the task and function of signal processing system are different, and even if under same mode, signal
Processing system can also automatically switch to search or tracking two states according to the discovery situation difference to target.
Present system workflow approximately as:
Firstly, powered on by the booting of signal processor 2,2 inside each section of signal processor start to carry out power-up initializing and
Self-test operations, if system boot is in operation irregularity state and can feed back to host computer 1.After the completion of the initialization of signal processor 2
Standby mode can be entered, wait the initialization bookbinding parameter to be received from host computer 1, these parameters include working system, antenna
Transmitted waveform.Signal processor 2, will be according to the working system of radar in parameter after receiving these initiation parameters
It selects to enter corresponding operating mode, the signal processing of each submodule BOB(beginning of block) search phase with transmitted waveform；A/D acquisition control mould
Block 21 can acquire echo data by frame synchronization and impulsive synchronization, then pre-processed, handled in the end PL preprocessing module 22
Result afterwards is then forwarded to arm processor module 23, and arm processor module 23 carries out object detection process to data, works as search
Each submodule of signal initially enters tracing mode after to target.In tracking mode, signal processor 2 is constantly by the angle of target
Control information is sent to host computer 1, while constantly closed loop adjusts range gate, that is, tracking sampling window position, until hitting mesh
Mark completes entire processing task.
Above description is only example of the present invention, does not constitute any limitation of the invention, it is clear that for
It, all may be without departing substantially from the principle of the invention, structure after having understood the content of present invention and principle for one of skill in the art
In the case where, carry out various modifications and change in form and details, but these modifications and variations based on inventive concept
Still within the scope of the claims of the present invention.
Claims (8)
1. a kind of MMW RADAR SIGNAL USING processing system based on MPSoC, including host computer (1) and signal processor (2), upper
Machine (1) is used to send initialization bookbinding parameter to signal processor (2), and receives the testing result of signal processor (2) return,
Realize the real-time observation to target, which is characterized in that signal processor (2) includes: master controller and functional module；
The functional module includes:
A/D acquisition control module (21), samples for the analog echo signal to radar, converts thereof into digital signal,
It is sent to the end PL preprocessing module (22)；
The end PL preprocessing module (22), the initialization bookbinding parameter sent for receiving host computer (1), the echo that sampling is obtained
Digital signal successively carries out Digital Down Convert, Fourier transformation, pulse compression, inverse Fourier transform, model selection, phase compensation
With the pretreatment of image mosaic, and by pretreated echo data with direct memory access dma mode pass through AXI bus interface
It is sent to arm processor system module (23)；
Arm processor module (23) for carrying out power-up initializing configuration to system, and is sent out the end PL preprocessing module (22)
The echo data sent carries out target detection, and will test result and pass host computer (1) back by the end PL preprocessing module (22)；
Communications interface control module (24) is used for the serial communication and chip of the end PL preprocessing module (22) and host computer (1)
The AXI bus marco and interruption of the internal end PL preprocessing module (22) and arm processor module (23) control, and realize to initialization
The transmission of bookbinding parameter, echo data and testing result；
The master controller, using the ZYNQ Series FPGA chip of new generation of ZU9EG, the chip is by complete arm processor piece
Upper system and 16nm low-power consumption programmable logic are closely integrated together, can realize traditional double-core hardware platform on a single chip
The function of framework, the end the PL preprocessing module (22) realize that the arm processor module (23) is based on based on programmable logic resource
Arm processor system on chip is realized.
2. system according to claim 1, which is characterized in that the plug-in a piece of 2GB of the end PL preprocessing module (22) holds
The DDR4 memory chip of amount.
3. system according to claim 1, which is characterized in that the plug-in a piece of 2GB capacity of arm processor module (23)
DDR4 memory chip and a piece of 8GB EMMC for memory image file.
4. system according to claim 1, which is characterized in that the A/D acquisition control module (21) is using ADI company
A low-power consumption, four-way, 14, the AD9694 chip of 500MSPS, sampling clock pass through SMA interface by external reference clock
Input, using being obtained after clock chip frequency multiplication.
5. system according to claim 1, which is characterized in that arm processor module (23) power on to system initial
Change configuration, comprising: to the control of power module electric sequence, the initialization of direct memory access DMA, the initialization of clock chip
With the initialization of A/D chip.
6. system according to claim 1, which is characterized in that the communication interface modules (24) uses RS422 communication protocols
View realizes differential signal to single-ended conversion by ADM2587 chip.
7. system according to claim 1, which is characterized in that the end PL preprocessing module (22) includes:
Digital Down Convert submodule (221), for realizing mixing, filtering and the extraction operation to echo data；
Submodule (222) are compressed in pulse, for completing the number after extracting to Digital Down Convert submodule (221) according to different mode
According to Fourier transformation FFT operation, matched filtering and the inverse Fourier transform IFFT operation for successively carrying out point-variable；
Moving-target detect MTD submodule (223), for pulse compress submodule (222) operation after data carry out it is identical away from
Reading from unit, target detection MTD or inverse Fourier transform IFFT processing of taking action of going forward side by side；
Image mosaic submodule (224), for detecting MTD submodule (223) to moving-target, treated, and data are spliced, and are obtained
Access is according to one-dimensional range profile.
8. system according to claim 1, which is characterized in that arm processor module (23) includes:
Detection sub-module (231), there are the numbers of target and corresponding distance unit position for obtaining, and carry out target phase height
Differentiate the interception of one-dimensional range profile；
It identifies submodule (232), for calculating data according to different mode to the processing data after detection sub-module (231)
Signal to noise ratio simultaneously obtains the precise position information of target or computer azimuth angle error and pitching angle error, calculates the speed of target and pre-
Survey the lower movement position of target.
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