CN110794415B - FMCW echo signal receiving and processing system and laser radar signal processing device - Google Patents

FMCW echo signal receiving and processing system and laser radar signal processing device Download PDF

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CN110794415B
CN110794415B CN201911044547.0A CN201911044547A CN110794415B CN 110794415 B CN110794415 B CN 110794415B CN 201911044547 A CN201911044547 A CN 201911044547A CN 110794415 B CN110794415 B CN 110794415B
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program module
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CN110794415A (en
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张传胜
龚高茂
邓姣
赵海军
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Hunan Maxwell Electronic Technology Co Ltd
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S17/00—Systems using the reflection or reradiation of electromagnetic waves other than radio waves, e.g. lidar systems
    • G01S17/02—Systems using the reflection of electromagnetic waves other than radio waves
    • G01S17/06—Systems determining position data of a target
    • G01S17/08—Systems determining position data of a target for measuring distance only
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/48—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S17/00
    • G01S7/483—Details of pulse systems
    • G01S7/486—Receivers
    • G01S7/487—Extracting wanted echo signals, e.g. pulse detection
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/48—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S17/00
    • G01S7/491—Details of non-pulse systems
    • G01S7/493—Extracting wanted echo signals

Abstract

The invention discloses an FMCW echo signal receiving and processing system and a laser radar signal processing device, wherein the echo signal receiving and processing system comprises a signal acquisition and storage module, a signal capture module, a signal tracking module and a sampling signal real-time output module, wherein the signal acquisition and storage module comprises a plurality of ADC modules, a plurality of input serializer ISERDES modules, a plurality of complex processing program modules, a parallel linear compensation program module, a 0-complementing and parallel/serial conversion module, an FIFO + DMA writing module and the like. The invention realizes the multi-gear adjustable frequency modulation continuous wave signal adjustment, can realize the distance measurement of different distances through parameter adjustment, and meets the requirements of laser radar distance measurement under different conditions.

Description

FMCW echo signal receiving and processing system and laser radar signal processing device
Technical Field
The present invention relates to the field of laser radar, and more particularly, to an FMCW echo signal receiving and processing system and a laser radar signal processing apparatus.
Background
Frequency Modulated Continuous Wave (FMCW) radar is a radar system that obtains range and speed information by frequency modulating a continuous wave, which may be modulated in a variety of ways, such as linear modulation and sinusoidal modulation. The Linear Frequency Modulation Continuous Wave (LFMCW) radar has the advantages of high distance resolution, low transmitting power, high receiving sensitivity, simple structure and the like, does not have a distance blind area, and has the characteristics of better anti-stealth, anti-background clutter and anti-interference capability than a pulse radar. The prior art adopts fixed signal frequency, and does not accord with different distances and high-precision distance measurement requirements.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides an FMCW echo signal receiving and processing system and a laser radar signal processing device, which realize multi-gear adjustable frequency modulation continuous wave signal adjustment, can realize distance measurement at different distances through parameter adjustment and can meet the requirement of laser radar accurate distance measurement under different conditions.
The purpose of the invention is realized by the following technical scheme:
an FMCW echo signal reception processing system comprising:
the device comprises an upper computer, a network port chip, an AXI _ Ethernet (IP) + Ethernet _ pcs _ pma (IP) module, an AXI _ Interconnect module, a DDR module, an MIG IP module, a signal acquisition and storage module, a signal capture module, a signal tracking module and a sampling signal real-time output module; the input and output end of the upper computer is connected with the input and output end of a network port chip, the input and output end of the network port chip is connected with the input and output end of an AXI _ Ethernet (IP) + Ethernet _ pcs _ pma (IP) module, the input and output end of the AXI _ Ethernet (IP) + Ethernet _ pcs _ pma (IP) module is connected with the input and output end of an AXI _ Interconnect module, the first input and output end of the AXI _ Interconnect module is connected with the input and output end of a MIG IP module, and the input and output end of the MIG IP module is connected with the input and output end of a DDR module; and a second input/output end of the AXI _ Interconnect module is connected with an input/output end of the signal acquisition and storage module, and a third input/output end of the AXI _ Interconnect module is connected with an input/output end of the signal capture module.
Furthermore, the signal acquisition and storage module comprises a plurality of ADC modules, a plurality of input serializer ISERDES modules, a plurality of complex processing program modules, a parallel linear compensation program module, a 0-complementing and parallel/serial conversion module and an FIFO + DMA writing module; the output end of the first ADC module is connected with the input end of a first input serializer ISERDES module, the output end of the first input serializer ISERDES module is connected with the input end of a first complex processing program module, the output end of the first complex processing program module is connected with the input end of a first parallel linear compensation program module, the output end of the first parallel linear compensation program module is connected with a first 0-complementing module and the input end of a parallel/serial conversion module, and the output end of the first 0-complementing module and the output end of the parallel/serial conversion module are connected with the input end of a first FIFO + DMA writing module; the output end of the second ADC module is connected with the input end of a second input serializer ISERDES module, the output end of the second input serializer ISERDES module is connected with the input end of a first complex processing program module, the output end of the first complex processing program module is connected with the input end of a first parallel linear compensation program module, the output end of the first parallel linear compensation program module is connected with a first 0-complementing module and the input end of a parallel/serial conversion module, and the output end of the first 0-complementing module and the output end of the parallel/serial conversion module are connected with the input end of a first FIFO + DMA writing module; the output end of the third ADC module is connected with the input end of a third input serializer ISERDES module, the output end of the third input serializer ISERDES module is connected with the input end of a second complex processing program module, the output end of the second complex processing program module is connected with the input end of a second parallel linear compensation program module, the output end of the second parallel linear compensation program module is connected with a second 0-complementing module and the input end of a parallel/serial conversion module, and the output end of the second 0-complementing module and the output end of the parallel/serial conversion module are connected with the input end of a second FIFO + DMA writing module.
Further, the signal capturing module comprises a DMA read + FIFO module, a 0 loss and serial/parallel conversion module, a complex multiplication program module, an extraction program module, an FFT program module, a peak value calculation program module, 8 frequency control word modules and 8 parallel DDS modules; the output end of the first DMA read + FIFO module is connected with the input end of a first lost 0 and serial/parallel conversion module, the output end of the first lost 0 and serial/parallel conversion module is connected with the input end of a first complex multiplication program module, the output end of the first complex multiplication program module is connected with the input end of a first extraction program module, the output end of the first extraction program module is connected with the input end of a first FFT program module, and the output end of the first FFT program module is connected with the input end of a first peak value calculation program module; the output end of the second DMA read + FIFO module is connected with the input end of a second lost 0 and serial/parallel conversion module, the output end of the second lost 0 and serial/parallel conversion module is connected with the input end of a second complex multiplication program module, the output end of the second complex multiplication program module is connected with the input end of a second extraction program module, the output end of the second extraction program module is connected with the input end of a second FFT program module, and the output end of the second FFT program module is connected with the input end of a second peak value calculation program module; the output end of the first 8 frequency control word modules is connected with the input end of the first 8-path parallel DDS module, and the output end of the first 8-path parallel DDS module is connected with the input end of the first complex multiplication program module; the output end of the second 8 frequency control word modules is connected with the input end of the second 8-path parallel DDS module, and the output end of the second 8-path parallel DDS module is connected with the input end of the second complex multiplication program module.
Further, the signal tracking module comprises a complex multiplication program module, an extraction program module, an FFT program module, a peak value calculation program module, three groups of frequency control word switching modules and an 8-channel parallel DDS module; the output end of the first complex multiplication program module is connected with the input end of the first extraction program module, the output end of the first extraction program module is connected with the input end of the first FFT program module, and the output end of the first FFT program module is connected with the input end of the first calculation program module; the output end of the second complex multiplication program module is connected with the input end of the second extraction program module, the output end of the second extraction program module is connected with the input end of the second FFT program module, and the output end of the second FFT program module is connected with the input end of the second calculation program module; the output end of the first three groups of frequency control word switching modules is connected with the input end of a first 8-channel parallel DDS module, and the output end of the first 8-channel parallel DDS module is connected with the input end of a first complex multiplication program module; the output end of the second three groups of frequency control word switching modules is connected with the input end of the second 8-channel parallel DDS module, and the output end of the second 8-channel parallel DDS module is connected with the input end of the second complex multiplication program module.
Furthermore, the sampling signal real-time output module comprises an SPF optical fiber module, a plurality of GTX interface modules, a write controller, a plurality of FIFO modules and a plurality of data processing modules; the input end of the first data processing module is connected with the output end of the first ADC module, the output end of the first data processing module is connected with the input end of the first FIFO module, the output end of the first FIFO module is connected with the first input end of the write controller, the first output end of the write controller is connected with the input end of the first GTX interface module, and the output end of the first GTX interface module is connected with the first input end of the SPF optical fiber module; the input end of the second data processing module is connected with the output end of the second ADC module, the output end of the second data processing module is connected with the input end of the second FIFO module, the output end of the second FIFO module is connected with the second input end of the write controller, the second output end of the write controller is connected with the input end of the second GTX interface module, and the output end of the second GTX interface module is connected with the second input end of the SPF optical fiber module; the input end of the third data processing module is connected with the output end of the third ADC module, the output end of the third data processing module is connected with the input end of the third FIFO module, the output end of the third FIFO module is connected with the third input end of the write controller, the third output end of the write controller is connected with the input end of the third GTX interface module, and the output end of the third GTX interface module is connected with the third input end of the SPF optical fiber module; the input end of the fourth data processing module is connected with the output end of the fourth ADC module, the output end of the fourth data processing module is connected with the input end of the fourth FIFO module, the output end of the fourth FIFO module is connected with the fourth input end of the write controller, the fourth output end of the write controller is connected with the input end of the fourth GTX interface module, and the output end of the fourth GTX interface module is connected with the fourth input end of the SPF optical fiber module.
A lidar signal processing apparatus comprising an FMCW echo signal receiving and processing system as claimed in any one of the preceding claims.
The invention has the beneficial effects that:
(1) the invention realizes the frequency modulation continuous wave signal regulation, can realize the ranging of different distances by parameter regulation, and meets the requirements of the laser radar ranging under different conditions.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a schematic diagram of the FMCW laser detection principle of the present invention.
FIG. 2 is a schematic diagram of the FMCW laser detection signal conversion process of the present invention.
Fig. 3 is a schematic diagram illustrating the principle of the modulation distance measurement and velocity measurement of the present invention.
FIG. 4 is a schematic diagram of the difference frequency without velocity according to the present invention.
Fig. 5 is a block diagram of a signal receiving and processing system according to the present invention.
Fig. 6 is a block diagram of a system for generating a frequency modulated source according to the present invention.
Fig. 7 is a flow chart of the chirp generation process of the present invention.
Detailed Description
The technical solutions of the present invention are further described in detail below with reference to the accompanying drawings, but the scope of the present invention is not limited to the following. All of the features disclosed in this specification, or all of the steps of a method or process so disclosed, may be combined in any combination, except combinations where mutually exclusive features and/or steps are used.
Any feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving equivalent or similar purposes, unless expressly stated otherwise. That is, unless expressly stated otherwise, each feature is only an example of a generic series of equivalent or similar features.
Specific embodiments of the present invention will be described in detail below, and it should be noted that the embodiments described herein are only for illustration and are not intended to limit the present invention. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one of ordinary skill in the art that: it is not necessary to employ these specific details to practice the present invention. In other instances, well-known circuits, software, or methods have not been described in detail so as not to obscure the present invention.
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Before describing the embodiments, some necessary terms need to be explained. For example:
if the terms "first," "second," etc. are used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a "first" element discussed below could also be termed a "second" element without departing from the teachings of the present invention. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.
The various terms appearing in this application are used for the purpose of describing particular embodiments only and are not intended as limitations of the invention, with the singular being intended to include the plural unless the context clearly dictates otherwise.
When the terms "comprises" and/or "comprising" are used in this specification, these terms are intended to specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence and/or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
As shown in fig. 1 to 7, an FMCW echo signal receiving and processing system includes:
the device comprises an upper computer, a network port chip, an AXI _ Ethernet (IP) + Ethernet _ pcs _ pma (IP) module, an AXI _ Interconnect module, a DDR module, an MIG IP module, a signal acquisition and storage module, a signal capture module, a signal tracking module and a sampling signal real-time output module; the input and output end of the upper computer is connected with the input and output end of a network port chip, the input and output end of the network port chip is connected with the input and output end of an AXI _ Ethernet (IP) + Ethernet _ pcs _ pma (IP) module, the input and output end of the AXI _ Ethernet (IP) + Ethernet _ pcs _ pma (IP) module is connected with the input and output end of an AXI _ Interconnect module, the first input and output end of the AXI _ Interconnect module is connected with the input and output end of a MIG IP module, and the input and output end of the MIG IP module is connected with the input and output end of a DDR module; and a second input/output end of the AXI _ Interconnect module is connected with an input/output end of the signal acquisition and storage module, and a third input/output end of the AXI _ Interconnect module is connected with an input/output end of the signal capture module.
Furthermore, the signal acquisition and storage module comprises a plurality of ADC modules, a plurality of input serializer ISERDES modules, a plurality of complex processing program modules, a parallel linear compensation program module, a 0-complementing and parallel/serial conversion module and an FIFO + DMA writing module; the output end of the first ADC module is connected with the input end of a first input serializer ISERDES module, the output end of the first input serializer ISERDES module is connected with the input end of a first complex processing program module, the output end of the first complex processing program module is connected with the input end of a first parallel linear compensation program module, the output end of the first parallel linear compensation program module is connected with a first 0-complementing module and the input end of a parallel/serial conversion module, and the output end of the first 0-complementing module and the output end of the parallel/serial conversion module are connected with the input end of a first FIFO + DMA writing module; the output end of the second ADC module is connected with the input end of a second input serializer ISERDES module, the output end of the second input serializer ISERDES module is connected with the input end of a first complex processing program module, the output end of the first complex processing program module is connected with the input end of a first parallel linear compensation program module, the output end of the first parallel linear compensation program module is connected with a first 0-complementing module and the input end of a parallel/serial conversion module, and the output end of the first 0-complementing module and the output end of the parallel/serial conversion module are connected with the input end of a first FIFO + DMA writing module; the output end of the third ADC module is connected with the input end of a third input serializer ISERDES module, the output end of the third input serializer ISERDES module is connected with the input end of a second complex processing program module, the output end of the second complex processing program module is connected with the input end of a second parallel linear compensation program module, the output end of the second parallel linear compensation program module is connected with a second 0-complementing module and the input end of a parallel/serial conversion module, and the output end of the second 0-complementing module and the output end of the parallel/serial conversion module are connected with the input end of a second FIFO + DMA writing module.
Further, the signal capturing module comprises a DMA read + FIFO module, a 0 loss and serial/parallel conversion module, a complex multiplication program module, an extraction program module, an FFT program module, a peak value calculation program module, 8 frequency control word modules and 8 parallel DDS modules; the output end of the first DMA read + FIFO module is connected with the input end of a first lost 0 and serial/parallel conversion module, the output end of the first lost 0 and serial/parallel conversion module is connected with the input end of a first complex multiplication program module, the output end of the first complex multiplication program module is connected with the input end of a first extraction program module, the output end of the first extraction program module is connected with the input end of a first FFT program module, and the output end of the first FFT program module is connected with the input end of a first peak value calculation program module; the output end of the second DMA read + FIFO module is connected with the input end of a second lost 0 and serial/parallel conversion module, the output end of the second lost 0 and serial/parallel conversion module is connected with the input end of a second complex multiplication program module, the output end of the second complex multiplication program module is connected with the input end of a second extraction program module, the output end of the second extraction program module is connected with the input end of a second FFT program module, and the output end of the second FFT program module is connected with the input end of a second peak value calculation program module; the output end of the first 8 frequency control word modules is connected with the input end of the first 8-path parallel DDS module, and the output end of the first 8-path parallel DDS module is connected with the input end of the first complex multiplication program module; the output end of the second 8 frequency control word modules is connected with the input end of the second 8-path parallel DDS module, and the output end of the second 8-path parallel DDS module is connected with the input end of the second complex multiplication program module.
Further, the signal tracking module comprises a complex multiplication program module, an extraction program module, an FFT program module, a peak value calculation program module, three groups of frequency control word switching modules and an 8-channel parallel DDS module; the output end of the first complex multiplication program module is connected with the input end of the first extraction program module, the output end of the first extraction program module is connected with the input end of the first FFT program module, and the output end of the first FFT program module is connected with the input end of the first calculation program module; the output end of the second complex multiplication program module is connected with the input end of the second extraction program module, the output end of the second extraction program module is connected with the input end of the second FFT program module, and the output end of the second FFT program module is connected with the input end of the second calculation program module; the output end of the first three groups of frequency control word switching modules is connected with the input end of a first 8-channel parallel DDS module, and the output end of the first 8-channel parallel DDS module is connected with the input end of a first complex multiplication program module; the output end of the second three groups of frequency control word switching modules is connected with the input end of the second 8-channel parallel DDS module, and the output end of the second 8-channel parallel DDS module is connected with the input end of the second complex multiplication program module.
Furthermore, the sampling signal real-time output module comprises an SPF optical fiber module, a plurality of GTX interface modules, a write controller, a plurality of FIFO modules and a plurality of data processing modules; the input end of the first data processing module is connected with the output end of the first ADC module, the output end of the first data processing module is connected with the input end of the first FIFO module, the output end of the first FIFO module is connected with the first input end of the write controller, the first output end of the write controller is connected with the input end of the first GTX interface module, and the output end of the first GTX interface module is connected with the first input end of the SPF optical fiber module; the input end of the second data processing module is connected with the output end of the second ADC module, the output end of the second data processing module is connected with the input end of the second FIFO module, the output end of the second FIFO module is connected with the second input end of the write controller, the second output end of the write controller is connected with the input end of the second GTX interface module, and the output end of the second GTX interface module is connected with the second input end of the SPF optical fiber module; the input end of the third data processing module is connected with the output end of the third ADC module, the output end of the third data processing module is connected with the input end of the third FIFO module, the output end of the third FIFO module is connected with the third input end of the write controller, the third output end of the write controller is connected with the input end of the third GTX interface module, and the output end of the third GTX interface module is connected with the third input end of the SPF optical fiber module; the input end of the fourth data processing module is connected with the output end of the fourth ADC module, the output end of the fourth data processing module is connected with the input end of the fourth FIFO module, the output end of the fourth FIFO module is connected with the fourth input end of the write controller, the fourth output end of the write controller is connected with the input end of the fourth GTX interface module, and the output end of the fourth GTX interface module is connected with the fourth input end of the SPF optical fiber module.
A lidar signal processing apparatus comprising an FMCW echo signal receiving and processing system as claimed in any one of the preceding claims.
In an embodiment of the present invention, the system uses a tunable frequency modulated continuous wave, for example, the frequency modulated continuous wave laser detection philosophy is shown in fig. 1. The local emission source DDS1 emits triangular frequency modulation continuous waves, the triangular frequency modulation continuous waves are amplified and frequency-doubled and then emitted by the laser part, the signals are reflected back when meeting obstacles, and are received by the laser receiving part and mixed with the local replica signal DDS2 to generate difference frequency signals, and the difference frequency signals contain the distance and speed information of a target. The difference frequency is amplified, A/D is carried out on the difference frequency, then digital signal processing is carried out, a target is captured and tracked, and the target distance and speed are solved. While the intensity of the echo light also contains relative intensity information about the reflectivity of the target, since intensity data can be acquired.
The FMCW laser detection system determines the distance to the target and the speed information by measuring the frequency of the intermediate frequency signal after mixing the transmitted and received laser frequency modulation signals, so that the FMCW laser detection system goes through four processes from the generation of the modulation signal to the acquisition of the intermediate frequency signal, i.e., laser intensity modulation, laser spatial transmission and target scattering, and receiving and mixing by the photodetector, as shown in fig. 2.
The frequency modulation continuous wave can have various waveforms, and the scheme adopts an improved triangular waveform and is divided into three sections: frequency rise, frequency fall, frequency invariance. The temporal variation of the instantaneous frequencies of the transmitted signal and the target echo signal is shown in fig. 3. In order to prevent the fbd frequency difference from exceeding the processing range too much, a frequency invariant segment is used.
The round trip transit time of the light and the target speed are such that there is a certain frequency difference between the two. And setting the signal scanning bandwidth as B, the repetition period as T, the distance R and the target echo signal delay as tau.
In the case of a stationary target:
Figure BDA0002253772770000074
Figure BDA0002253772770000071
obtaining:
Figure BDA0002253772770000072
c light speed 3X 108m/s
Target present speed case:
fbu＝fb-fv
fbd＝fb+fv
Figure BDA0002253772770000073
Figure BDA0002253772770000081
f0: center frequency point
As a result of the above equation, one can obtain:
Figure BDA0002253772770000082
Figure BDA0002253772770000083
according to the formula, to obtain the speed and distance information, the system digital signal processing is to solve fvHeel fbu。
1. Ranging resolution
Distance calculation formula:
Figure BDA0002253772770000084
derivation of the formula yields:
Figure BDA0002253772770000085
as can be seen, the range resolution is determined by the frequency resolution of the frequency domain processing of the echo signal. When the signal in one period time is subjected to spectrum analysis, the minimum frequency interval capable of being distinguished is minimum 1/T, because fbThe observation period is T/3, i.e. Δ fbMinimum value of Δ fbSubstituting the formula for 3/T to obtain:
Figure BDA0002253772770000086
from the above formula, the detection range resolution is only related to the bandwidth B of the fm signal, and is not related to other factors.
The bandwidth designed by the scheme is 450MHz, namely the distance resolution is
Figure BDA0002253772770000087
(one) System index calculation
The following technical indexes are taken as examples to illustrate the calculation process of system parameters
The system scans the bandwidth: b ═ 2 GHz.
Signal repetition frequency: 1 kHz-500 kHz.
The requirement of the range measurement is as follows: less than or equal to 10 Km.
The requirement of speed measurement range: is less than or equal to 3400 m/s.
Systematic frequency difference calculation
From the distance calculation formula
Figure BDA0002253772770000091
Then, the maximum frequency difference is generated by substituting the 1KHz repetition frequency and the 10Km distance into the formula:
Figure BDA0002253772770000092
frequency difference generated by speed:
Figure BDA0002253772770000093
Figure BDA0002253772770000094
assuming that the laser wavelength is 1500nm, substituting the formula to obtain:
Figure BDA0002253772770000095
the velocity doppler is down-converted to control the range within 200MHz for signal sampling processing.
The software is divided into a transmitting part and a receiving part, the transmitting part and the receiving part are completely separated on the hardware, and the FPGA is used for data processing, so that the software is divided into two parts to be designed respectively.
The FPGA software realizes the block diagram, and the software part mainly comprises two parts of echo signal receiving, processing and frequency modulation source signal transmitting. The receiving part realizes the main functions of signal acquisition and DDR storage, signal capture, signal tracking and real-time output of sampled signals. The transmitting part mainly realizes the generation of two-channel frequency modulation source signals and the time delay control of two channels.
Fig. 5 is a software block diagram of echo signal receiving processing, and fig. 6 is a software block diagram of frequency modulation source signal generation. The FPGA chips all adopt xilinx K7 series chips. Microblaze in the figure is a processor (soft core), and mainly implements parameter configuration, data flow control, data scheduling of each functional module and parsing and encapsulation of an internet protocol (only a receiving part needs to process the internet protocol); MIG (memory Interface Generator) is a DDR controller (soft core); the Ethernet _ pcs _ pma (soft core) and the AXI _ Ethernet (soft core) mainly realize the communication between the upper computer and the FPGA processing board card; GTX (hard core) is a high-speed serial data transceiver, and the single line rate can support 12Gb/s at most.
Generation of (a) chirp signals
The chirp signal is generated using a waveform direct read method. Firstly, storing a waveform file to be generated in the Nor Flash, reading the waveform file from the Nor Flash to the DDR buffer by the FPGA, and then sending the waveform file read from the DDR buffer by the FPGA to the DAC through the JESD204B interface to form a chirp transmitting signal. The data processing flow is as shown in FIG. 7
The frequency modulation signal generation module mainly generates frequency modulation signals with different repetition frequencies (1 kHz-500 kHz), wherein each repetition frequency comprises three waveforms of frequency rise, frequency fall and frequency invariance and is divided equally. The module control interface is a serial interface, and controllable signals are as follows: the size of a repetition period and the delay of two channels (the resolution is 100ns, and the range is 0-1 ms).
The frequency modulation signal adopts an AWG scheme, and the matlab is used for generating a corresponding waveform signal according to different frequency modulation repetition frequencies in the early stage, and the waveform signal is sampled and stored in the Nor flash. When a frequency modulation source starting signal is received, reading the data from the Nor flash to the DDR for buffering, and then sending the data to the DAC.
Regarding the delay control part, a data delay processing block is optionally added at the channel 2. For an equivalent parallel 32 samples, lane 2 is delayed by 1 clock cycle of 125MHz relative to lane 1, which corresponds to a delay of 8ns for the lane 2 waveform relative to lane 1. And before the generation of the frequency modulation signal is started, calculating the number of delayed cycles according to the delay time. For integral multiple N delay, directly delaying N period output; for non-integer multiples of delay, additional data processing is required. For the lowest resolution of delay control, 100ns, that is, 100/8 is 12.5 clock cycles, data processing only needs to stagger a half cycle on the basis of delaying an integer cycle (only one cycle needs to be delayed in FPGA processing, then 16 samples after the previous cycle of the previous cycle are spliced into 32 samples, and 16 sample values in the previous cycle are 0 during initialization). Therefore, in the actual process, when the fm generation signal is received, the two channels respectively read the required waveform signal from the DDR into the FIFO, then the data transmission of the channel 1 is started first, and then the data transmission of the channel 2 is started according to the number of delay cycles, and the data delay process can only be two of N half cycles (non-integer cycle delay) and N cycles (integer cycle delay). The present invention may also employ sinusoidal frequency modulated continuous waves, etc.
In other technical features of the embodiment, those skilled in the art can flexibly select and use the features according to actual situations to meet different specific actual requirements. However, it will be apparent to one of ordinary skill in the art that: it is not necessary to employ these specific details to practice the present invention. In other instances, well-known algorithms, methods or systems have not been described in detail so as not to obscure the present invention, and are within the scope of the present invention as defined by the claims.
For simplicity of explanation, the foregoing method embodiments are described as a series of acts or combinations, but those skilled in the art will appreciate that the present application is not limited by the order of acts, as some steps may occur in other orders or concurrently depending on the application. Further, those skilled in the art should also appreciate that the embodiments described in the specification are preferred embodiments and that the acts and elements referred to are not necessarily required in this application.
Those of skill in the art would appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The disclosed systems, modules, and methods may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units may be only one logical division, and there may be other divisions in actual implementation, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be referred to as an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and the parts displayed as units may or may not be physical units, may be located in one place, or may also be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
It will be understood by those skilled in the art that all or part of the processes in the methods for implementing the embodiments described above can be implemented by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium, and when executed, the program can include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a ROM, a RAM, etc.
The foregoing is illustrative of the preferred embodiments of this invention, and it is to be understood that the invention is not limited to the precise form disclosed herein and that various other combinations, modifications, and environments may be resorted to, falling within the scope of the concept as disclosed herein, either as described above or as apparent to those skilled in the relevant art. And that modifications and variations may be effected by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (5)

1. An FMCW echo signal reception processing system, comprising:
the device comprises an upper computer, a network port chip, an AXI _ Ethernet (IP) + Ethernet _ pcs _ pma (IP) module, an AXI _ Interconnect module, a DDR module, an MIG IP module, a signal acquisition and storage module, a signal capture module, a signal tracking module and a sampling signal real-time output module; the input and output end of the upper computer is connected with the input and output end of a network port chip, the input and output end of the network port chip is connected with the input and output end of an AXI _ Ethernet (IP) + Ethernet _ pcs _ pma (IP) module, the input and output end of the AXI _ Ethernet (IP) + Ethernet _ pcs _ pma (IP) module is connected with the input and output end of an AXI _ Interconnect module, the first input and output end of the AXI _ Interconnect module is connected with the input and output end of a MIG IP module, and the input and output end of the MIG IP module is connected with the input and output end of a DDR module; a second input/output end of the AXI _ Interconnect module is connected with an input/output end of the signal acquisition and storage module, and a third input/output end of the AXI _ Interconnect module is connected with an input/output end of the signal capture module;
the signal acquisition and storage module comprises a plurality of ADC modules, a plurality of input serializer ISERDES modules, a plurality of complex processing program modules, a parallel linear compensation program module, a 0 complementing and parallel/serial conversion module and an FIFO + DMA writing module; the output end of the first ADC module is connected with the input end of a first input serializer ISERDES module, the output end of the first input serializer ISERDES module is connected with the input end of a first complex processing program module, the output end of the first complex processing program module is connected with the input end of a first parallel linear compensation program module, the output end of the first parallel linear compensation program module is connected with a first 0-complementing module and the input end of a parallel/serial conversion module, and the output end of the first 0-complementing module and the output end of the parallel/serial conversion module are connected with the input end of a first FIFO + DMA writing module; the output end of the second ADC module is connected with the input end of a second input serializer ISERDES module, the output end of the second input serializer ISERDES module is connected with the input end of a first complex processing program module, the output end of the first complex processing program module is connected with the input end of a first parallel linear compensation program module, the output end of the first parallel linear compensation program module is connected with a first 0-complementing module and the input end of a parallel/serial conversion module, and the output end of the first 0-complementing module and the output end of the parallel/serial conversion module are connected with the input end of a first FIFO + DMA writing module; the output end of the third ADC module is connected with the input end of a third input serializer ISERDES module, the output end of the third input serializer ISERDES module is connected with the input end of a second complex processing program module, the output end of the second complex processing program module is connected with the input end of a second parallel linear compensation program module, the output end of the second parallel linear compensation program module is connected with a second 0-complementing module and the input end of a parallel/serial conversion module, and the output end of the second 0-complementing module and the output end of the parallel/serial conversion module are connected with the input end of a second FIFO + DMA writing module.
2. The FMCW echo signal receiving and processing system of claim 1, wherein the signal capture module includes a DMA read + FIFO module, a 0 loss and serial/parallel conversion module, a complex multiplication program module, an extraction program module, an FFT program module, a peak computation program module, and 8 frequency control word modules, 8 DDS modules; the output end of the first DMA read + FIFO module is connected with the input end of a first lost 0 and serial/parallel conversion module, the output end of the first lost 0 and serial/parallel conversion module is connected with the input end of a first complex multiplication program module, the output end of the first complex multiplication program module is connected with the input end of a first extraction program module, the output end of the first extraction program module is connected with the input end of a first FFT program module, and the output end of the first FFT program module is connected with the input end of a first peak value calculation program module; the output end of the second DMA read + FIFO module is connected with the input end of a second lost 0 and serial/parallel conversion module, the output end of the second lost 0 and serial/parallel conversion module is connected with the input end of a second complex multiplication program module, the output end of the second complex multiplication program module is connected with the input end of a second extraction program module, the output end of the second extraction program module is connected with the input end of a second FFT program module, and the output end of the second FFT program module is connected with the input end of a second peak value calculation program module; the output end of the first 8 frequency control word modules is connected with the input end of the first 8-path parallel DDS module, and the output end of the first 8-path parallel DDS module is connected with the input end of the first complex multiplication program module; the output end of the second 8 frequency control word modules is connected with the input end of the second 8-path parallel DDS module, and the output end of the second 8-path parallel DDS module is connected with the input end of the second complex multiplication program module.
3. The FMCW echo signal receiving and processing system of claim 1, wherein the signal tracking module includes a complex multiplication program module, an extraction program module, an FFT program module, a peak calculation program module, a three-set frequency control word switching module and an 8-channel parallel DDS module; the output end of the first complex multiplication program module is connected with the input end of the first extraction program module, the output end of the first extraction program module is connected with the input end of the first FFT program module, and the output end of the first FFT program module is connected with the input end of the first peak value calculation program module; the output end of the second complex multiplication program module is connected with the input end of the second extraction program module, the output end of the second extraction program module is connected with the input end of the second FFT program module, and the output end of the second FFT program module is connected with the input end of the second peak value calculation program module; the output end of the first three groups of frequency control word switching modules is connected with the input end of a first 8-channel parallel DDS module, and the output end of the first 8-channel parallel DDS module is connected with the input end of a first complex multiplication program module; the output end of the second three groups of frequency control word switching modules is connected with the input end of the second 8-channel parallel DDS module, and the output end of the second 8-channel parallel DDS module is connected with the input end of the second complex multiplication program module.
4. The FMCW echo signal receiving and processing system of claim 1, wherein the sampled signal real-time output module includes an SPF fiber module, a plurality of GTX interface modules, a write controller, a plurality of FIFO modules and a plurality of data processing modules; the input end of the first data processing module is connected with the output end of the first ADC module, the output end of the first data processing module is connected with the input end of the first FIFO module, the output end of the first FIFO module is connected with the first input end of the write controller, the first output end of the write controller is connected with the input end of the first GTX interface module, and the output end of the first GTX interface module is connected with the first input end of the SPF optical fiber module; the input end of the second data processing module is connected with the output end of the second ADC module, the output end of the second data processing module is connected with the input end of the second FIFO module, the output end of the second FIFO module is connected with the second input end of the write controller, the second output end of the write controller is connected with the input end of the second GTX interface module, and the output end of the second GTX interface module is connected with the second input end of the SPF optical fiber module; the input end of the third data processing module is connected with the output end of the third ADC module, the output end of the third data processing module is connected with the input end of the third FIFO module, the output end of the third FIFO module is connected with the third input end of the write controller, the third output end of the write controller is connected with the input end of the third GTX interface module, and the output end of the third GTX interface module is connected with the third input end of the SPF optical fiber module; the input end of the fourth data processing module is connected with the output end of the fourth ADC module, the output end of the fourth data processing module is connected with the input end of the fourth FIFO module, the output end of the fourth FIFO module is connected with the fourth input end of the write controller, the fourth output end of the write controller is connected with the input end of the fourth GTX interface module, and the output end of the fourth GTX interface module is connected with the fourth input end of the SPF optical fiber module.
5. Lidar signal processing apparatus comprising the FMCW echo signal reception processing system of any one of the preceding claims.
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