CN116886247B - Baud rate self-adaption method and device based on UART communication, UART system and medium - Google Patents
Baud rate self-adaption method and device based on UART communication, UART system and medium Download PDFInfo
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Abstract
The invention provides a baud rate self-adaption method, a device, a UART system and a medium based on UART communication, wherein the method comprises the following steps: the upper computer sends an identification frame and a reference clock, and the high-low level counter counts the level and outputs a level count value to the count value comparator; outputting a target count value to a sampling clock generator after the count value comparator is filled up to determine a sampling clock and a target baud rate; the data control module obtains sampling data according to the sampling clock and sends the sampling data to the upper computer; and when the sampling data and the check data are consistent, the target baud rate and the sampling clock are sent to the slave computer, and the upper computer is in interactive communication with the slave computer through the data control module. According to the technical scheme provided by the embodiment of the invention, the sampling clock can be determined according to the identification frame, so that the target baud rate of the upper computer can be automatically determined, complex command interaction between the upper computer and the slave computer is not needed, the self-adaptation process of the baud rate is simplified, and the identification efficiency of the baud rate is improved.
Description
Technical Field
The present invention relates to the field of UART communication technologies, and in particular, to a UART communication-based baud rate adaptive method, apparatus, UART system, and medium.
Background
Currently, UART communication technology is applied to various fields and devices, and in order to ensure that data transmission is correct, it is necessary to ensure that the baud rates of the two devices are identical. In the traditional baud rate configuration method, a group of interfaces which are independently communicated with an upper computer are required to be provided on a slave computer, so that the upper computer can directly access a configuration register in the slave computer, and then the slave computer is directly configured with the consistent baud rate through the upper computer. Although the baud rate is consistent, the complexity of the interface design and the communication pins of the device are increased, and the development efficiency is affected.
Some related technologies propose a baud rate adaptive method, which automatically identifies the baud rate used by the communication of the upper computer through the slave, and adjusts the baud rate to be consistent. However, before the self-adaption is completed, the baud rates of the upper computer and the slave computer are not consistent, the command interaction or register operation performed at the moment is very complex, the development difficulty is high, and the degree of automation is low.
Disclosure of Invention
The present invention aims to solve at least one of the technical problems existing in the prior art. Therefore, the invention provides a baud rate self-adaption method, a device, a UART system and a medium based on UART communication, which can simplify the baud rate self-adaption process and improve the self-adaption baud rate efficiency.
In a first aspect, an embodiment of the present invention provides a UART communication-based baud rate adaptive method, which is applied to a UART system, where the UART system includes a baud rate adaptive device, an upper computer, and a slave computer, the baud rate adaptive device includes a high-low level counter, a count value comparator, a sampling clock generator, and a data control module, the high-low level counter and the data control module are connected with the upper computer, the sampling clock generator and the data control module are connected with the slave computer, and the UART communication-based baud rate adaptive method includes:
when the UART system is electrified, the upper computer sends an identification frame and a reference clock to the baud rate self-adaptive device, wherein the identification frame comprises identification data and check data, the identification data is positioned before the check data, and the data quantity of the identification data is the same as the storage space of the count value comparator;
the count value comparator enables the high-low level counter in an unfilled state, the high-low level counter performs level counting on the identification data according to the reference clock, and a plurality of level count values are output to the count value comparator, wherein the level count values are used for indicating the duration of high level or low level;
Stopping enabling the high-low level counter when the count value comparator is filled, and sending a target count value to the sampling clock generator, wherein the target count value is used for indicating the maximum number of the level count values with the same value;
the sampling clock generator determines a sampling clock according to the reference clock and the target count value, determines a target baud rate according to the sampling clock, enables the data control module and sends the sampling clock to the data control module;
the data control module performs data sampling on the data sent by the upper computer according to the sampling clock to obtain sampling data, and sends the sampling data to the upper computer;
and when the sampling data are consistent with the verification data, the data control module enables the sampling clock generator to send the target baud rate and the sampling clock to the slave computer, and the upper computer interactively communicates data with the slave computer through the data control module.
According to some embodiments of the invention, the host computer sends an identification frame and a reference clock to the baud rate adaptive device, including:
the upper computer generates the identification frame and splits the identification frame into a plurality of groups of frame data according to the data receiving bit number of the baud rate self-adapting device;
The upper computer generates the identification data and the check data according to the frame data, wherein the identification data and the check data comprise start bits, the frame data and stop bits which are sequentially arranged, and the frame data of the identification data is positioned before the frame data of the check data in the identification frame;
and the upper computer continuously transmits the reference clock to the baud rate self-adaptive device and sequentially transmits the identification data and the verification data.
According to some embodiments of the invention, the high-low level counter level counts the identification data according to the reference clock, outputs a plurality of level count values to the count value comparator, and includes:
the high-low level counter starts level counting after detecting the falling edge of the start bit;
each time the high-low level counter detects a new rising edge, performing high level counting, and outputting a level counting value to the counting value comparator;
each time the high-low level counter detects a new falling edge, performing low level counting, and outputting a level counting value to the counting value comparator;
And stopping level counting when the high-low level counter detects the rising edge of the stop bit.
According to some embodiments of the invention, the count value comparator includes a plurality of registers, and when the count value comparator is filled, the high and low level counter is disabled, and the sending of the target count value to the sampling clock generator includes:
the counter value comparator stores the level counter values into the registers, wherein each register stores one level counter value;
stopping enabling the high-low level counter when all the registers of the count value comparator are filled;
the count value comparator compares the values of the level count values stored in the register, determines the target count value according to the level count value with the largest number of times, and sends the target count value to the sampling clock generator.
According to some embodiments of the invention, the sampling clock generator determines a sampling clock from the reference clock and the target count value, comprising:
the sampling clock generator takes the reference clock as a reference, and turns once according to the duration indicated by half of the target count value to obtain a turning level;
And forming the sampling clock according to all the inversion levels.
According to some embodiments of the present invention, the data control module performs data sampling on data sent by the upper computer according to the sampling clock to obtain sampled data, including:
the data control module performs level sampling on the data sent by the upper computer according to the rising edge of the sampling clock to obtain a sampling level;
and the data control module composes all the sampling levels into the sampling data according to the data length of the check data.
According to some embodiments of the invention, the baud rate adaptive device further comprises a reset system, the method further comprising:
when the reset system acquires an internal reset signal or an external reset signal, the count value comparator is emptied, so that the counter comparator enables the high-low level counter again, wherein the internal reset signal is generated after the data control module determines that the sampling data and the verification data are inconsistent, and the external reset signal is generated by the upper computer;
and the upper computer resends the identification frame and the reference clock to the baud rate self-adaptive device.
In a second aspect, an embodiment of the present invention provides a UART communication-based baud rate adaptive device, including at least one control processor and a memory communicatively coupled to the at least one control processor; the memory stores instructions executable by the at least one control processor to enable the at least one control processor to perform the UART communication based baud rate adaptation method according to the first aspect described above.
In a third aspect, an embodiment of the present invention provides a UART system, including a baud rate adaptive device based on UART communication according to the second aspect.
In a fourth aspect, an embodiment of the present invention provides a computer readable storage medium storing computer executable instructions for performing the UART communication based baud rate adaptation method according to the first aspect.
The baud rate self-adaptive method based on UART communication according to the embodiment of the invention has at least the following beneficial effects: when the UART system is electrified, the upper computer sends an identification frame and a reference clock to the baud rate self-adaptive device, wherein the identification frame comprises identification data and check data, the identification data is positioned before the check data, and the data quantity of the identification data is the same as the storage space of the count value comparator; the count value comparator enables the high-low level counter in an unfilled state, the high-low level counter performs level counting on the identification data according to the reference clock, and a plurality of level count values are output to the count value comparator, wherein the level count values are used for indicating the duration of high level or low level; stopping enabling the high-low level counter when the count value comparator is filled, and sending a target count value to the sampling clock generator, wherein the target count value is used for indicating the maximum number of the level count values with the same value; the sampling clock generator determines a sampling clock according to the reference clock and the target count value, determines a target baud rate according to the sampling clock, enables the data control module and sends the sampling clock to the data control module; the data control module performs data sampling on the data sent by the upper computer according to the sampling clock to obtain sampling data, and sends the sampling data to the upper computer; and when the sampling data are consistent with the verification data, the data control module enables the sampling clock generator to send the target baud rate and the sampling clock to the slave computer, and the upper computer interactively communicates data with the slave computer through the data control module. According to the technical scheme of the embodiment of the invention, the baud rate self-adaptive device can determine and check the sampling clock according to the identification frame, further automatically determine the target baud rate of the upper computer, synchronize communication data between the upper computer and the slave computer according to the target baud rate, do not need complex command interaction between the upper computer and the slave computer, and only need simple frame identification and sampling, thereby simplifying the baud rate self-adaptive process and improving the baud rate identification efficiency.
Drawings
Fig. 1 is a schematic diagram of a baud rate adaptive device according to an embodiment of the present invention;
FIG. 2 is a flow chart of a baud rate adaptation method based on UART communication according to an embodiment of the present invention;
FIG. 3 is a flow chart of generating an identification frame provided by another embodiment of the present invention;
FIG. 4 is a schematic diagram of a data transmission waveform according to another embodiment of the present invention;
FIG. 5 is a flow chart of level counting provided by another embodiment of the present invention;
FIG. 6 is a flow chart of acquiring a level count value provided by another embodiment of the present invention;
FIG. 7 is a flow chart of generating a sampling clock provided by another embodiment of the present invention;
FIG. 8 is a waveform schematic diagram of a sampling clock provided in another embodiment of the present invention;
FIG. 9 is a flow chart of data sampling provided by another embodiment of the present invention;
FIG. 10 is a flow chart of a system reset provided by another embodiment of the present invention;
FIG. 11 is a flow chart of a specific example provided by the present invention;
fig. 12 is a block diagram of a baud rate adaptive device based on UART communication according to another embodiment of the present invention.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the invention.
In the description of the present invention, it should be understood that references to orientation descriptions such as upper, lower, front, rear, left, right, etc. are based on the orientation or positional relationship shown in the drawings, are merely for convenience of description of the present invention and to simplify the description, and do not indicate or imply that the apparatus or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present invention.
In the description of the present invention, a number means one or more, a number means two or more, and greater than, less than, exceeding, etc. are understood to not include the present number, and above, below, within, etc. are understood to include the present number. The description of the first and second is for the purpose of distinguishing between technical features only and should not be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated or implicitly indicating the precedence of the technical features indicated.
In the description of the present invention, unless explicitly defined otherwise, terms such as arrangement, installation, connection, etc. should be construed broadly and the specific meaning of the terms in the present invention can be reasonably determined by a person skilled in the art in combination with the specific contents of the technical scheme.
The embodiment of the invention provides a baud rate self-adaption method, a device, a UART system and a medium based on UART communication, wherein the baud rate self-adaption method based on UART communication comprises the following steps: when the UART system is electrified, the upper computer sends an identification frame and a reference clock to the baud rate self-adaptive device, wherein the identification frame comprises identification data and check data, the identification data is positioned before the check data, and the data quantity of the identification data is the same as the storage space of the count value comparator; the count value comparator enables the high-low level counter in an unfilled state, the high-low level counter performs level counting on the identification data according to the reference clock, and a plurality of level count values are output to the count value comparator, wherein the level count values are used for indicating the duration of high level or low level; stopping enabling the high-low level counter when the count value comparator is filled, and sending a target count value to the sampling clock generator, wherein the target count value is used for indicating the maximum number of the level count values with the same value; the sampling clock generator determines a sampling clock according to the reference clock and the target count value, determines a target baud rate according to the sampling clock, enables the data control module and sends the sampling clock to the data control module; the data control module performs data sampling on the data sent by the upper computer according to the sampling clock to obtain sampling data, and sends the sampling data to the upper computer; and when the sampling data are consistent with the verification data, the data control module enables the sampling clock generator to send the target baud rate and the sampling clock to the slave computer, and the upper computer interactively communicates data with the slave computer through the data control module. According to the technical scheme of the embodiment of the invention, the baud rate self-adaptive device can determine and check the sampling clock according to the identification frame, further automatically determine the target baud rate of the upper computer, synchronize communication data between the upper computer and the slave computer according to the target baud rate, do not need complex command interaction between the upper computer and the slave computer, and only need simple frame identification and sampling, thereby simplifying the baud rate self-adaptive process and improving the baud rate identification efficiency.
First, the structure of the UART system of the present invention is described as an example, but the present example is not limited to the structure of the UART system, and one embodiment of the technical solution of the present invention may be implemented, and referring to fig. 1, fig. 1 is a schematic structural diagram of a baud rate adaptive device provided in the present invention, where the baud rate adaptive device includes a high-low level counter, a count value comparator, a sampling clock generator, a data control module, and a reset system. The baud rate self-adaptive device is respectively connected with the upper computer and the slave computer.
The high-low level counter is connected to the TX (transmit) interface of the upper computer and the count value comparator, and is used for counting the high level or the low level to generate the level count value under the driving of the reference clock.
It should be noted that, the count value comparator is further connected to the sampling clock generator, the count value comparator is composed of a plurality of registers, before the registers of the count value comparator are not filled, the high-low level counter is enabled to obtain data from the upper computer and perform level counting, after the registers of the count value comparator are filled, the high-low level counter is stopped to be enabled, and the sampling clock generator is expected to output the most identical level count value stored in the registers, namely the target count value.
It should be noted that, the sampling clock generator is further connected to the slave and the data control module, and the sampling clock generator is configured to generate a sampling clock according to the target count value, and calculate the target baud rate according to the sampling clock.
The data control module is connected to the upper computer TX interface, the upper computer RX (receiving) interface, the slave computer TX interface, the slave computer RX interface and the reset system, respectively, and when the target baud rate of the upper computer is identified to be successful, the upper computer TX interface, the upper computer RX interface, the slave computer TX interface and the slave computer RX interface are connected, so that the communication data sent by the upper computer and the slave computer are synchronized.
It should be noted that, after knowing the functions of the various parts of the baud rate adaptive device, those skilled in the art are familiar with how to set a specific circuit structure, and the present embodiment does not relate to a specific circuit structure improvement, and can implement the above functions and interfaces.
The following describes a control method according to an embodiment of the present invention based on the UART system shown in fig. 1.
Referring to fig. 2, fig. 2 is a flowchart of a UART communication based baud rate adaptive method according to an embodiment of the present invention, where the UART communication based baud rate adaptive method includes, but is not limited to, the following steps:
S21, when the UART system is electrified, the upper computer sends an identification frame and a reference clock to the baud rate self-adaptive device, wherein the identification frame comprises identification data and check data, the identification data is positioned before the check data, and the data quantity of the identification data is the same as the storage space of the count value comparator;
s22, enabling a high-low level counter by the count value comparator in an unfilled state, and performing level counting on identification data by the high-low level counter according to a reference clock, and outputting a plurality of level count values to the count value comparator, wherein the level count values are used for indicating the duration of the high level or the low level;
s23, when the count value comparator is filled, stopping enabling the high-low level counter, and sending a target count value to the sampling clock generator, wherein the target count value is used for indicating the maximum number of level count values with the same value;
s24, a sampling clock generator determines a sampling clock according to the reference clock and the target count value, determines a target baud rate according to the sampling clock, enables the data control module and sends the sampling clock to the data control module;
s25, the data control module performs data sampling on the data sent by the upper computer according to the sampling clock to obtain sampling data, and sends the sampling data to the upper computer;
And S26, when the sampling data and the verification data are consistent, the data control module enables the sampling clock generator to send the target baud rate and the sampling clock to the slave computer, and the upper computer interacts and communicates data with the slave computer through the data control module.
It should be noted that, since UART communication requires that the baud rates of the upper computer and the slave computer are uniform, before determining the target baud rate of the upper computer, the upper computer in this embodiment sends the identification frame to the baud rate adaptive device, and since the identification frame is sent by the upper computer according to the target baud rate, the baud rate adaptive device determines the baud rate indicated by the identification frame, and thus determines the target baud rate of the upper computer. In the embodiment, the identification frame is divided into identification data and check data, the sampling clock is identified through the identification data, whether the sampling clock is accurately checked through the check data, UART communication is performed through the target baud rate corresponding to the sampling clock if the check is successful, and otherwise, the identification is continued, so that the self-adaption of the baud rate is realized.
It should be noted that, the frame structure of the identification frame may be adjusted according to the baud rate adaptive device, and the specific group number of the identification data and the verification data may also be adjusted according to the actual requirement, so that the greater the number of the identification data, the higher the accuracy of the identification.
In order to increase the degree of automation of baud rate recognition, the present embodiment sets the data amount of the recognition data to be the same as the storage amount of the count value comparator, and switches the reception target of the recognition frame by whether the count value comparator is full or not as a change basis of the enable signal. According to the description of the embodiment shown in fig. 1, the count value comparator is composed of registers, so when the UART system is powered on, the count value comparator is not filled up, and thus an enable signal is sent to the high-low level comparator, the data control module does not acquire the enable signal, therefore, an identification frame sent by the TX interface of the upper computer is received by the high-low level counter, and identification data in front is received, the high-low level counter performs level counting on the identification data, one level count value is output to the count value comparator every time the level counter is detected, when the count value comparator is filled up with the level count value, the high-low level counter is stopped to enable and the target count value is output to the sampling clock generator, the sampling clock generator enables the data control module after determining the sampling clock according to the target count value, so that check data after the identification data are received by the data control module, comparison of the sampling data and the check data is performed, and when the sampling data are consistent with the check data, the sampling data are connected to the RX interface of the upper computer, the TX interface of the slave computer, and the RX interface of the upper computer are connected, and the communication data of the upper computer and the slave computer are realized. Based on the technical scheme of the embodiment, the upper computer only needs to send the identification frame, the baud rate self-adaptive device automatically responds to the baud rate to identify, and the upper computer and the slave are connected after the baud rate is identified correctly, so that the baud rate identification process is simplified, and the automatic degree of baud rate identification is improved.
It should be noted that the high-low level counter may detect the high level and the low level by the rising edge and the falling edge, and determine the duration of each level in combination with the reference clock, for example, after detecting the falling edge, when detecting the next rising edge, obtain the level count value according to the level number of the reference clock during this period. Each level count value enters a count value comparator, and although the high level and the low level of the identification frame are equal in width, in order to avoid count differences caused by other factors such as signal jitter, signal delay and the like, the count value comparator of the embodiment takes the count value with the largest number of times as a target count value and outputs the count value to a sampling clock generator, so that the accuracy of a sampling clock is improved.
It should be noted that the target count value can represent a duration of one level, so that the sampling clock can be determined according to the target count value and the reference clock, for example, one flip level is generated according to half of the target count value, the duration of the flip level is determined by combining the reference clock, and the obtained plurality of flip levels are determined as the sampling clock.
It should be noted that, the target baud rate is a baud rate value, and it is known to those skilled in the art that the target baud rate represents a binary bit number that can be transmitted per second, and on the basis of having a sampling clock, the target baud rate can be obtained by calculating according to the frequency of the sampling clock, where one period of the sampling clock represents the duration of transmitting data in one bit, and the specific calculation process is a technique well known to those skilled in the art, and will not be repeated herein.
It should be noted that, after the sampling clock generator determines the sampling clock and the target baud rate, the data is stored first, and the sampling clock and the enable signal are sent to the data control module, so that the data control module operates to receive the data from the TX interface of the upper computer, and the data control module receives the first bit of the check data because the identification data is already received by the high-low level counter. In order to verify the sampling clock, the embodiment samples the data through the sampling clock while receiving the verification data, if the baud rate corresponding to the sampling clock is always consistent with the baud rate of the upper computer, the embodiment verifies the accuracy of the sampling clock based on the sampled sampling data and the verification data, and when the verification is passed, the data control module sends an enabling signal to the sampling clock generator to enable the enabling signal to send the sampling clock and the target baud rate to the slave computer, so that the slave computer has the target baud rate consistent with the upper computer, and a baud rate foundation is provided for UART communication.
After the sampled data is obtained, the data control module compares the sampled data with the check data, and the data control module transmits the target baud rate to the slave machine through the backward comparison, and connects the communication interfaces of the upper computer and the slave machine.
In summary, the baud rate adaptive device in this embodiment may be divided into a baud rate identification mode and an idle mode, where the baud rate identification mode is automatically entered after the UART system is powered on or reset, and is maintained in the baud rate identification mode before the baud rate identification is not completed, all data sent by the host computer only enter the baud rate adaptive device, but not enter the slave device, and when the sampled data and the verified data pass verification, it is determined that the target baud rate is available, the baud rate adaptive device enters the idle mode, and the host computer communicates with the slave device in the data control module. For the upper computer, an identification frame is required to be sent after starting or resetting, whether the baud rate is identified is finished or not is judged according to sampling data sent by the data control module, and if the identification is not finished, the upper computer is required to continuously send the identification frame; if the identification is completed, the data of the upper computer and the slave computer are synchronized through the sampling clock of the data control module, and then normal serial communication is carried out. After the baud rate self-adaptive device of the embodiment enters an idle mode, the baud rate recognition function is turned off to reduce the power consumption of the system until the upper computer sends a reset signal.
In addition, referring to fig. 3, in an embodiment, step S21 shown in fig. 2 further includes, but is not limited to, the following steps:
S31, the upper computer generates an identification frame, and splits the identification frame into a plurality of groups of frame data according to the data receiving bit number of the baud rate self-adaptive device;
s32, the upper computer generates identification data and check data according to the frame data, wherein the identification data and the check data comprise start bits, frame data and stop bits which are sequentially arranged, and the frame data of the identification data is positioned before the frame data of the check data in the identification frame;
s33, the upper computer continuously transmits a reference clock to the baud rate self-adaptive device and sequentially transmits identification data and check data.
It should be noted that, in order to distinguish the identification data and the check data, in this embodiment, the identification frame is split according to the number of data receiving bits of the baud rate adaptive device to transmit, for example, the baud rate adaptive device may receive 8 bits of data each time, and the count value comparator is provided with 16 registers, and the identification data adopts two sets of data, then the identification frame may be set to Ox55551234, and the 4 sets of data may be transmitted, which are Ox55, ox12, and Ox34, respectively, where Ox represents 16 bins, ox55 is Ox55 as the identification data, ox12 and Ox34 are check data.
It should be noted that, after splitting the identification frame into multiple sets of frame data, in order to distinguish each set of data, a start bit needs to be added before the data, a stop bit needs to be added after the data, the data start is determined by detecting the start bit, and the data end is determined by detecting the stop bit, for example, referring to fig. 4, taking the identification data Ox55 as an example, the frame data Ox55 includes 8 bits of data, that is, 8 staggered high and low levels, a low level is set before the first high level as the start bit, a high level is set after the last low level as the stop bit, and specific durations of the start bit and the stop bit can be adjusted according to actual requirements, and can be identified as the start bit and the stop bit by the high and low level counter.
In addition, referring to fig. 5, in an embodiment, step S22 shown in fig. 2 further includes, but is not limited to, the following steps:
s51, the high-low level counter starts level counting after detecting the falling edge of the start bit;
s52, every time the high-low level counter detects a new rising edge, performing high-level counting once, and outputting a level counting value to the counting value comparator;
s53, every time the high-low level counter detects a new falling edge, performing low level counting once, and outputting a level counting value to the counting value comparator;
s54, when the high-low level counter detects the rising edge of the stop bit, the level counting is stopped.
The high-low level counter counts the high level and the low level respectively under the driving of the reference clock. As shown in the waveform diagram of fig. 4, a low-level start bit is set before the first group of identification data, the counter starts to start counting preparation after identifying the falling edge, starts to count the high level of the identification data until encountering the rising edge, starts to count the low level of the log-log data after completing the counting of the 8-bit data, triggers counting stop at the rising edge of the stop bit, and restarts counting when encountering the next start bit.
It should be noted that the high-low level counter of the present embodiment is driven by a reference clock, and according to the data structure, the first two sets of 0x55 data for identifying the baud rate can form 16 staggered high-low levels with the same duration. The count value of each level acquired by the high-low level counter is transmitted to the count value comparator. For example, referring to fig. 4, the timing is started after the falling edge of the start bit is detected once, counting is performed according to the reference clock after the first rising edge is detected, and the number of times of turning over of the reference clock is determined to be 10 after the next falling edge is detected, so that the output level count value is 10. The same is done for low level counting after detecting a new falling edge, and the description is not repeated here.
In addition, in one embodiment, the count value comparator includes a plurality of registers, and referring to fig. 6, step S22 shown in fig. 2 further includes, but is not limited to, the following steps:
s61, the counter value comparator stores the level counter value into registers, wherein each register stores one level counter value;
s62, stopping enabling the high-low level counter when all registers of the count value comparator are filled;
and S63, the counter value comparator compares the values of the level counter values stored in the register, determines a target counter value according to the level counter value with the largest number of times, and sends the target counter value to the sampling clock generator.
Note that, the counter value comparator may be provided with a plurality of registers, for example, according to the above example, a hexadecimal identification frame Ox55551234 is adopted, and the counter value comparator needs to store 16 bits of data, so 16 registers may be provided, and the specific number may be adjusted according to actual requirements.
It should be noted that, the count value comparator enables the high-low level counter before the registers are not fully filled, for example, after the system is powered on, the high-low level counter can be disabled because the characteristics of the registers are cleared, when the high-low level counter acquires the Ox55 identification data shown in fig. 4, 8 level count values are output, after the second Ox55 is level-counted, 8 level count values are output, at this time, 16 registers of the count value comparator are fully filled, the target count value is output, the enabling of the high-low level counter is stopped, and the data path from the TX interface of the upper computer to the high-low level counter is closed.
In order to avoid the count difference caused by other factors such as signal jitter and signal delay, the count value comparator starts to compare the sizes of 16 count values, and outputs the count value with the largest number of times to the sampling clock generator.
In addition, referring to fig. 7, in an embodiment, step S24 shown in fig. 2 further includes, but is not limited to, the following steps:
s71, the sampling clock generator takes a reference clock as a reference, and turns once according to the duration indicated by half of the target count value to obtain a turning level;
s72, forming a sampling clock according to all the inversion levels.
It should be noted that, according to the description of the above embodiment, the target count value is the duration between two inversions, and one clock needs to have both high level and low level, so the sampling clock may be a reference clock, and half of the level count value is used to generate one inversed level, so as to divide a sampling clock, and the waveform comparison between the sampling clock and the identification data may refer to fig. 8, where when the sampling clock is correctly identified, the rising edge and the falling edge of the sampling clock are matched with the data of the identification frame, so that it may be ensured that the baud rate is kept consistent, and if the sampling clock is incorrect, as shown in the two waveforms below in fig. 8, the rising edge or the falling edge of the sampling clock cannot be aligned with the verification data, so that the sampled sampling data is inconsistent with the verification data, and the identification of the sampling clock needs to be performed again.
In addition, referring to fig. 9, in an embodiment, step S25 shown in fig. 2 further includes, but is not limited to, the following steps:
s91, the data control module performs level sampling on data sent by the upper computer according to the rising edge of the sampling clock to obtain a sampling level;
s92, the data control module composes all sampling levels into sampling data according to the data length of the check data.
It should be noted that, the data controller samples the data sent by the TX interface of the upper computer through the sampling clock, as shown in fig. 8, if the sampling clock is correct, the rising edge or the falling edge is consistent with the waveform of the check data, and the obtained sampling data is the same as the check data.
Taking check data of 0x12 and 0x34 as an example, the level of the upper computer TX interface is sampled once every time the rising edge of the sampling clock arrives, the level value is stored as sampling data, and is fed back to the upper computer RX interface. The stored sampling data sequentially form two groups of 8-bit data, if the two groups of data are not 0x12 and 0x34, which indicate that the sampling clock is incorrect, the baud rate is not correctly identified, the data controller can send a reset signal to reset the system, wait for the next identification frame sent by the host computer, and the host computer can continue sending the identification frame because of receiving incorrect feedback data. If the match is correct, the whole system enters an idle mode, and the data controller enables the sampling clock generator to send out a sampling clock and a baud rate value. And meanwhile, the RX and TX interfaces of the slave machine are started, and the data controller synchronizes the data of the upper computer and the slave machine by using a sampling clock, so that the data interaction of the two devices under the same baud rate is completed.
In addition, in an embodiment, the baud rate adaptive device further includes a reset system, and referring to fig. 10, the method of this embodiment further includes, but is not limited to, the following steps:
s101, when a reset system acquires an internal reset signal or an external reset signal, a count value comparator is emptied to enable a high-low level counter to be enabled again by the counter comparator, wherein the internal reset signal is generated after a data control module determines that sampling data and check data are inconsistent, and the external reset signal is generated by an upper computer;
s102, the upper computer resends the identification frame and the reference clock to the baud rate self-adaptive device.
It should be noted that, according to the description of the embodiment shown in fig. 2, if the initial state of the count value comparator is null during the system power-up stage, the high-low level counter can be enabled to perform level counting. After the adaptive recognition is started, the sampling clock is not necessarily accurately recognized, and the parameters of the device may need to be adjusted in the UART communication process, and the baud rate adaptive device in this embodiment is provided with a reset system, so that the adaptive recognition of the target baud rate is repeatedly triggered by an external reset signal and an internal reset signal.
It should be noted that, the external reset signal may be sent by the upper computer at any time, and may be triggered according to the use requirement of the device, so those skilled in the art are well aware of how to send the reset signal to the device through the upper computer, and the description thereof is not repeated here. It should be noted that, when the target baud rate is successfully identified, the host computer and the slave computer perform UART communication, i.e. in the idle state described in the above embodiment, the baud rate adaptive device determines that the target baud rate is correct, so that an internal reset signal is not generated, and the baud rate adaptive device needs to be reset by an external reset signal. After the upper computer sends an external reset signal, an identification frame is sent to the baud rate self-adapting device, and the steps of the embodiment are repeated to complete the self-adaptation of the baud rate.
It should be noted that, when the internal reset signal is generated when the data control module determines that the sampling data and the verification data are inconsistent, the upper computer also synchronously determines that the verification fails at this time, so that the identification frame is retransmitted, the high-low level counter is enabled after the clear count value comparator is reset at this time, the identification data is reacquired for counting, and the specific process is only needed by referring to the description of the above embodiment, and the detailed description is not repeated here.
In addition, in order to better explain the technical solution of the present embodiment, a specific example is set forth below, in this example, the identification frame is exemplified by Ox55551234, the count value comparator is exemplified by 16 registers, and referring to fig. 11, this example includes, but is not limited to, the following steps:
s111, powering up the system, and sending an identification frame 0x55551234 to the baud rate self-adaptive device by the upper computer;
s112, the high-low level counter recognizes the falling edge of the start bit, starts to count the level in the recognition data, finishes counting one level every time the level is turned over once, and then transmits the level counting value to the counting value comparator;
s113, after the count value comparator receives 16 level count values, the enable of the high-low level counter is canceled, the high-low level counter stops working, a data path from the upper computer TX interface to the high-low level counter is closed, the count value comparator compares the 16 level count values, and the count value with the largest number is taken as a target count value to be output to the sampling clock generator;
S114, the sampling clock generator receives the target count value, generates a turnover level by using half of the target count value under the drive of the reference clock, generates the sampling clock, calculates the target baud rate according to the frequency of the sampling clock, enables the data control module while generating the sampling clock, and opens a data path from the upper computer TX interface to the data control module;
s115, the data control module takes a sampling clock as a reference to sample the last two groups of data 0x12 and 0x34 sent by the upper computer, the sampled data are sent to the upper computer after the sampling is completed, when the sampled data are consistent with the check data, the step S116 is executed, otherwise, when the sampled data are inconsistent with the check data, the data control module sends an internal reset signal once, and the step S112 is executed;
s116, the data control module sends a finishing signal to the sampling clock generator, so that the sampling clock generator outputs a sampling clock and a target baud rate to the slave, and the data control module is communicated with an interface of the upper computer and the slave.
As shown in fig. 12, fig. 12 is a block diagram of a UART communication based baud rate adaptive device according to an embodiment of the present invention. The invention also provides a baud rate self-adapting device based on UART communication, which comprises:
The processor 1201 may be implemented by a general purpose central processing unit (Central Processing Unit, CPU), a microprocessor, an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), or one or more integrated circuits, etc. for executing relevant programs to implement the technical solution provided by the embodiments of the present application;
the Memory 1202 may be implemented in the form of a Read Only Memory (ROM), a static storage device, a dynamic storage device, or a random access Memory (Random Access Memory, RAM). The memory 1202 may store an operating system and other application programs, and when the technical solutions provided in the embodiments of the present disclosure are implemented by software or firmware, relevant program codes are stored in the memory 1202, and the processor 1201 invokes the UART communication-based baud rate adaptive method according to the embodiments of the present disclosure;
an input/output interface 1203 for implementing information input and output;
the communication interface 1204 is configured to implement communication interaction between the device and other devices, and may implement communication in a wired manner (e.g., USB, network cable, etc.), or may implement communication in a wireless manner (e.g., mobile network, WIFI, bluetooth, etc.);
A bus 1205 for transferring information between various components of the device such as the processor 1201, memory 1202, input/output interface 1203, and communication interface 1204;
wherein the processor 1201, the memory 1202, the input/output interface 1203 and the communication interface 1204 enable communication connection between each other inside the device via a bus 1205.
The embodiment of the application also provides a UART system, which comprises the Baud rate self-adapting device based on UART communication.
The embodiment of the application also provides a storage medium, which is a computer readable storage medium, and the storage medium stores a computer program, and the computer program realizes the baud rate self-adaption method based on UART communication when being executed by a processor.
The memory, as a non-transitory computer readable storage medium, may be used to store non-transitory software programs as well as non-transitory computer executable programs. In addition, the memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid state storage device. In some embodiments, the memory optionally includes memory remotely located relative to the processor, the remote memory being connectable to the processor through a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof. The apparatus embodiments described above are merely illustrative, in which the elements illustrated as separate components may or may not be physically separate, implemented to reside in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
Those of ordinary skill in the art will appreciate that all or some of the steps, systems, and methods disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes both volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as known to those skilled in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Furthermore, as is well known to those of ordinary skill in the art, communication media typically include computer readable instructions, data structures, program modules, or other data in a modulated data signal, such as a carrier wave or other transport mechanism, and may include any information delivery media.
While the preferred embodiment of the present invention has been described in detail, the present invention is not limited to the above embodiments, and those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit and scope of the present invention, and these equivalent modifications or substitutions are included in the scope of the present invention as defined in the appended claims.
Claims (10)
1. The utility model provides a baud rate self-adaptation method based on UART communication, its characterized in that is applied to UART system, UART system includes baud rate self-adaptation device, host computer and slave machine, baud rate self-adaptation device includes high low level counter, count value comparator, sampling clock generator and data control module, high low level counter and data control module are connected with the host computer, sampling clock generator and data control module is connected with the slave machine, the baud rate self-adaptation method based on UART communication includes:
when the UART system is electrified, the upper computer sends an identification frame and a reference clock to the baud rate self-adaptive device, wherein the identification frame comprises identification data and check data, the identification data is positioned before the check data, and the data quantity of the identification data is the same as the storage space of the count value comparator;
The count value comparator enables the high-low level counter in an unfilled state, the high-low level counter performs level counting on the identification data according to the reference clock, and a plurality of level count values are output to the count value comparator, wherein the level count values are used for indicating the duration of high level or low level;
stopping enabling the high-low level counter when the count value comparator is filled, and sending a target count value to the sampling clock generator, wherein the target count value is used for indicating the maximum number of the level count values with the same value;
the sampling clock generator determines a sampling clock according to the reference clock and the target count value, determines a target baud rate according to the sampling clock, enables the data control module and sends the sampling clock to the data control module;
the data control module performs data sampling on the data sent by the upper computer according to the sampling clock to obtain sampling data, and sends the sampling data to the upper computer;
and when the sampling data are consistent with the verification data, the data control module enables the sampling clock generator to send the target baud rate and the sampling clock to the slave computer, and the upper computer interactively communicates data with the slave computer through the data control module.
2. The UART communication-based baud rate adaptation method according to claim 1, wherein the host computer transmits an identification frame and a reference clock to the baud rate adaptation device, comprising:
the upper computer generates the identification frame and splits the identification frame into a plurality of groups of frame data according to the data receiving bit number of the baud rate self-adapting device;
the upper computer generates the identification data and the check data according to the frame data, wherein the identification data and the check data comprise start bits, the frame data and stop bits which are sequentially arranged, and the frame data of the identification data is positioned before the frame data of the check data in the identification frame;
and the upper computer continuously transmits the reference clock to the baud rate self-adaptive device and sequentially transmits the identification data and the verification data.
3. The UART communication-based baud rate adaptation method according to claim 2, wherein the high-low level counter level-counts the identification data according to the reference clock, outputs a plurality of level count values to the count value comparator, comprising:
The high-low level counter starts level counting after detecting the falling edge of the start bit;
each time the high-low level counter detects a new rising edge, performing high level counting, and outputting a level counting value to the counting value comparator;
each time the high-low level counter detects a new falling edge, performing low level counting, and outputting a level counting value to the counting value comparator;
and stopping level counting when the high-low level counter detects the rising edge of the stop bit.
4. The UART communication-based baud rate adaptation method according to claim 3, wherein the count value comparator includes a plurality of registers, and when the count value comparator is filled, disabling the high and low level counter, transmitting a target count value to the sampling clock generator comprises:
the counter value comparator stores the level counter values into the registers, wherein each register stores one level counter value;
stopping enabling the high-low level counter when all the registers of the count value comparator are filled;
The count value comparator compares the values of the level count values stored in the register, determines the target count value according to the level count value with the largest number of times, and sends the target count value to the sampling clock generator.
5. The UART communication based baud rate adaptation method according to claim 1, wherein the sampling clock generator determining a sampling clock from the reference clock and the target count value comprises:
the sampling clock generator takes the reference clock as a reference, and turns once according to the duration indicated by half of the target count value to obtain a turning level;
and forming the sampling clock according to all the inversion levels.
6. The UART communication-based baud rate adaptive method according to claim 1, wherein the data control module performs data sampling on the data sent by the upper computer according to the sampling clock to obtain sampled data, and the method comprises:
the data control module performs level sampling on the data sent by the upper computer according to the rising edge of the sampling clock to obtain a sampling level;
and the data control module composes all the sampling levels into the sampling data according to the data length of the check data.
7. The UART communication based baud rate adaptation method according to claim 1, wherein said baud rate adaptation apparatus further comprises a reset system, said method further comprising:
when the reset system acquires an internal reset signal or an external reset signal, the count value comparator is emptied, so that the counter comparator enables the high-low level counter again, wherein the internal reset signal is generated after the data control module determines that the sampling data and the verification data are inconsistent, and the external reset signal is generated by the upper computer;
and the upper computer resends the identification frame and the reference clock to the baud rate self-adaptive device.
8. A UART communication based baud rate adaptation device comprising at least one control processor and a memory for communication connection with said at least one control processor; the memory stores instructions executable by the at least one control processor to enable the at least one control processor to perform the UART communication based baud rate adaptation method of any one of claims 1 to 7.
9. A UART system, comprising the UART communication based baud rate adaptive device of claim 8.
10. A computer-readable storage medium storing computer-executable instructions for causing a computer to perform the UART communication-based baud rate adaptation method according to any one of claims 1 to 7.
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