CN212969687U - Asynchronous serial port communication baud rate automatic checkout device - Google Patents
Asynchronous serial port communication baud rate automatic checkout device Download PDFInfo
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- CN212969687U CN212969687U CN202022422274.3U CN202022422274U CN212969687U CN 212969687 U CN212969687 U CN 212969687U CN 202022422274 U CN202022422274 U CN 202022422274U CN 212969687 U CN212969687 U CN 212969687U
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Abstract
The utility model discloses an asynchronous serial port communication baud rate automatic detection device, which comprises an edge detection module, a pulse width counting module, a minimum pulse width module and a table look-up module which are connected in sequence; the detection method comprises the steps of receiving an asynchronous serial port signal, and sampling the asynchronous serial port signal through a sampling clock signal with fixed frequency to obtain a rising edge signal and a falling edge signal of the asynchronous serial port signal; generating a counting enabling signal according to the rising edge signal or the falling edge signal, and counting the time length of the enabling signal when the enabling signal is effective in real time to obtain a bit width counting value of a high level or a low level; comparing the bit width count value of the high level or the bit width count value of the low level with the minimum pulse width count value, and keeping a smaller value to output; and inquiring a baud rate and bit width relation table stored in the minimum pulse width module according to the value output by the minimum pulse width module to obtain the baud rate of the data sent by the asynchronous serial port.
Description
Technical Field
The utility model relates to a baud rate detection technology, concretely relates to asynchronous serial communication baud rate automatic checkout device.
Background
The GPS/Beidou satellite positioning, navigation and time service and the synchronous time service among mobile communication base stations, the position, time and other information are all transmitted in a timing mode through an asynchronous serial port mode, and a device receiving the serial port TOD message acquires synchronous time information by receiving the TOD message and analyzing message data.
The baud rate of the TOD message for sending the time service information has the settable characteristic, which is usually 9600bps by default, and can also be set to other common baud rates, such as the lowest 4800bps and the highest 115200 bps. Therefore, the device receiving the TOD message needs to know the baud rate of the TOD message to be able to normally communicate, and needs to automatically detect the baud rate when the baud rate of the TOD message is unknown, and can set the baud rate when receiving the data only after detecting the correct baud rate, so as to correctly receive the data of the TOD message.
The method and the device for automatically detecting the baud rate of the serial communication at present mainly have the following defects and shortcomings:
a: software attempts to receive data using different baud rates, respectively, and speculates on the baud rate of the transmitted data depending on the number of received 0's or 1's. Electronic technology 2008,31(23)169 and 170,180 based on unknown host computer serial communication baud rate detection. The defects are that the software executes the flow in sequence, the detection time is long, and a CPU processor or an MCU microcontroller needs to run corresponding application software to complete the detection.
B: the existing patent technologies of 'automatic baud rate detection circuit and detection method thereof' CN202010167862.9 and 'automatic baud rate detection module' CN201320759120.0, etc. need to detect the baud rate of an appointed data mode, and have the defects that a sending end needs to send 'appointed data' at regular time in the serial port communication process, so that 'appointed' communication data is added, the serial port sending end and a receiving end are required to have agreement on a protocol, and unless both ends of the serial port are designed by the same development, the practicability is not high, redundant communication bytes are added, and effective communication bandwidth is wasted.
C: in the existing patent technologies of a method for automatically adapting the baud rate, an intelligent terminal and a storage medium, a method for automatically detecting the baud rate of a CAN bus and the like, CPU software is adopted to calculate the high and low level timing time of data received by a serial port, and a method for calculating and deducing the baud rate to be sent is calculated through an algorithm.
The interrupt calculation mode through the CPU occupies CPU hardware resources, software driving is not beneficial to transplantation, and the accuracy is low. In order to improve the accuracy, a data needs to be returned to verify whether the calculated baud rate is correct or not, even a data is actively sent, and whether a normal response mode exists or not is determined to probe the baud rate of the serial communication.
SUMMERY OF THE UTILITY MODEL
To the above-mentioned not enough among the prior art, the utility model provides an asynchronous serial communication baud rate automatic checkout device need not application software and treater, only just can realize the detection of baud rate through the circuit.
In order to achieve the purpose of the invention, the utility model adopts the technical scheme that:
the utility model provides an asynchronous serial communication baud rate automatic checkout device which includes:
the edge detection module is used for receiving the asynchronous serial port signal and sampling the asynchronous serial port signal through a sampling clock signal with fixed frequency to obtain a rising edge signal and a falling edge signal of the asynchronous serial port signal;
the pulse width counting module is used for generating a counting enabling signal according to the rising edge signal or the falling edge signal, and counting the effective time length of the enabling signal in real time to obtain a high-level or low-level bit width counting value;
the minimum pulse width module is used for comparing the bit width counting value of the high level or the bit width counting value of the low level with the minimum pulse width counting value and keeping a smaller value to output; and
and the table look-up module is used for inquiring the baud rate and bit width relation table stored in the table look-up module according to the value output by the minimum pulse width module to obtain the baud rate of the data sent by the asynchronous serial port.
Further, the minimum pulse width module includes:
a flip-flop U11 for aligning the received falling edge signal with the rising edge of the sampling clock signal;
a comparator U55 for comparing the low-level bit width count value with the minimum pulse width count value;
the selector A3 is used for selecting the smaller value to output according to the comparison result of the comparator U55;
a selector a4, for sending the output of the selector A3 to the flip-flop U33 when the signal output by the flip-flop U11 is valid and the signal output by the flip-flop U22 is invalid;
a flip-flop U22 for aligning the received rising edge signal with the rising edge of the sampling clock signal;
a comparator U44 for comparing the high-level bit width count value with the minimum pulse width count value;
the selector A1 is used for selecting the smaller value to output according to the comparison result of the comparator U44;
the selector A2 is used for sending the output of the selector A1 to the flip-flop U33 through the selector A4 when the signal output by the flip-flop U11 is invalid and the signal output by the flip-flop U22 is valid; and
and a flip-flop U33 for saving the smaller value of the currently inputted value and the minimum pulse width count value as the minimum pulse width count value.
The utility model has the advantages that: the detection device can find the minimum data bit width in the data of serial communication, the baud rate of serial communication is obtained by looking up the table of the minimum data bit width, the whole design is realized by adopting a hardware circuit, the help of processors or microcontrollers such as a CPU, an MCU and a DSP is not needed, application software is not needed to run, the baud rate of a sending end in the serial communication is obtained more quickly and conveniently, and the communication of any serial port is very easy to joint.
Drawings
Fig. 1 is a schematic block diagram of an asynchronous serial port communication baud rate automatic detection device.
Fig. 2 is a circuit diagram of a pulse width counting module.
FIG. 3 is a timing diagram of the pulse width counting module.
Fig. 4 is a circuit diagram of a minimum pulse width module.
Detailed Description
The following description of the embodiments of the present invention is provided to facilitate the understanding of the present invention by those skilled in the art, but it should be understood that the present invention is not limited to the scope of the embodiments, and various changes may be made apparent to those skilled in the art within the spirit and scope of the present invention as defined and defined by the appended claims.
As shown in fig. 1, the automatic detection device for the baud rate of asynchronous serial port communication includes an edge detection module, a pulse width counting module, a minimum pulse width module, and a table look-up module, which are connected in sequence.
The edge detection module is used for receiving the asynchronous serial port signal and sampling the asynchronous serial port signal through a sampling clock signal with fixed frequency to obtain a rising edge signal and a falling edge signal of the asynchronous serial port signal.
The fixed frequency is preferably 10MHz, and the selection of the fixed frequency can filter out high-frequency interference pulses with the frequency period less than 100ns, so that the filtering effect is achieved.
The pulse width counting module is used for generating a counting enabling signal according to the rising edge signal or the falling edge signal, and counting the effective time length of the enabling signal in real time to obtain a high-level or low-level bit width counting value;
the minimum pulse width module is used for comparing the bit width counting value of the high level or the bit width counting value of the low level with the minimum pulse width counting value and keeping a smaller value to output; and
and the table look-up module is used for inquiring the baud rate and bit width relation table stored in the table look-up module according to the value output by the minimum pulse width module to obtain the baud rate of the data sent by the asynchronous serial port.
In implementation, the optimal baud rate and bit width relation table in the scheme includes the baud rate, the time occupied by each data bit corresponding to the baud rate and a bit width statistic, and specifically refer to table 1.
TABLE 1 Baud Rate vs. bit Width and count tolerance
The working principle of the table look-up module is to calculate the time length of each bit according to the baud rate of serial port communication, and the table 1 is the time occupied by each data bit from 600 to 1024000 baud rate and the value counted by counting each bit with the sampling frequency of 10 MHz. Considering that jitter error of 3% may exist in serial port transceiving data, a 3% tolerance is made on statistical data (statistical data, i.e. bit width statistical value).
The table look-up module corresponds to an interval of-1.5% to + 1.5% of the data in the table look-up 1 according to the output value of the minimum pulse width module, and obtains a corresponding baud rate value in the interval.
The scheme adopts the minimum pulse width module to count, so that the situation that the statistical data cannot correctly reflect the baud rate when '1' or '0' continuously appears in the serial port signal rxd can be avoided, the minimum pulse width is the bit width of 1 bit sent by the serial port according to the baud rate, and the actual serial port baud rate is obtained by reverse thrust through the bit width (pulse width) counting value of 1 bit.
For example, in the case of fig. 3, the pulse width statistical count value at the high level is 374 (the statistical data is invalid data below 9), and the pulse width statistical count values at the low level are 174 and 176. These values are compared in the minimum pulse width module, resulting in a minimum pulse width value of 174. In the table look-up module, 174 corresponds to the range of 171 to 176, and it can be known through table look-up 1 that the baud rate of the sending data of the asynchronous serial port signal at this time is 57600.
Fig. 2 shows a circuit diagram of an edge detection module, wherein rxd: signals from asynchronous serial communication; gclk: a clock signal that samples rxd; rst _ n: a reset signal, active low; posedge _ pulse: detecting an output pulse after a rising edge of rxd; negedge _ pulse: detecting an output pulse after a falling edge of rxd; u1 and U2 are first level flip-flops and second level flip-flops, respectively; u3 and U4 are not gates; u5 and U6 are 2-input and gates.
As shown in fig. 2, the edge detection module includes two flip-flops, two not gates, and two and gates.
The trigger U1 is used for aligning the rising edge of the asynchronous serial port signal and the sampling clock signal; the flip-flop U2 is used for delaying the signal output by the flip-flop U1 in alignment by one clock cycle (the clock cycle is 100 ns); the NOT gate U3 is used for inverting the signal output by the trigger U2 after time delay; the not gate U4 is used to invert the signal output by the flip-flop U1.
The AND gate U5 is used for performing combinational logic AND operation on the signal output after the negation operation of the NOT gate U3 and the signal output by the trigger U1 in alignment to obtain the rising edge of the asynchronous serial port signal; and the AND gate U6 is used for performing combinational logic AND operation on the signal output after the inversion operation of the NOT gate U4 and the signal output by the trigger U2 in a delayed mode to obtain the falling edge of the asynchronous serial port signal.
The pulse width counting module generates a counting enabling signal through the rising edge pulse signal posedge _ pulse and the falling edge pulse signal negedge _ pulse, and counts the time length of the valid counting enabling signal in real time, wherein the time length is the pulse width of the current high level or low level of the serial port signal.
The specific working principle is as follows: the high count enable is asserted by the rising edge posedge _ pulse signal of rxd, which is not terminated until the falling edge negedge _ pulse signal occurs. Similarly, the low count enable is asserted by the falling edge of rxd, which is not terminated until the rising edge posegge _ pulse signal occurs.
The high pulse width counter starts counting when the high count enable is active (logic 1), and the maximum count value 32767, i.e. the maximum pulse time, is 32767x100 ns. The low level pulse width counter starts counting when the low level count enable is active (logic 1), and the maximum count value 32767.
The pulse width counting module comprises a high-level pulse width counter and a low-level pulse width counter, wherein the high-level pulse width counter is used for generating a counting enabling signal according to a rising edge signal and counting the time length of the enabling signal when the enabling signal is effective in real time to obtain a high-level bit width counting value; the low-level pulse width counter is used for generating a counting enabling signal according to the falling edge signal, and counting the time length of the enabling signal when the enabling signal is effective in real time to obtain a low-level bit width counting value.
Fig. 3 is a timing diagram of the operation logic of the pulse width counting module, wherein gclk is a sampling clock, rxd is serial communication data, negative _ en is a low-level bit width count enable signal for rxd, positive _ en is a high-level bit width count enable signal for rxd, negative _ cnt is a low-level bit width count value for rxd, and positive _ cnt is a high-level bit width count value for rxd.
And the pulse width counting module outputs the counted high-level bit width statistical count value and the counted low-level bit width statistical count value to the minimum pulse width module.
In fig. 4, reference is made to the designation gclk: a clock signal that samples rxd; rst _ n: a reset signal; posedge _ pulse: detecting an output pulse after a rising edge of rxd; negedge _ pulse: an output pulse following the falling edge of rxd is detected.
posedge _ cnt [14:0 ]: a high level pulse width of rxd; negedge _ cnt [14:0 ]: low level pulse width of rxd; min _ pulse [14:0 ]: a minimum pulse width; the reference symbols in the circuit diagram are as follows: u1, U2, and U3 are D flip-flops; u4 and U5 are comparators; MUX21 is an alternative selector.
As shown in fig. 4, the minimum pulse width module includes three flip-flops, two comparators, and 4 selectors.
Wherein the flip-flop U11 is configured to align the received falling edge signal with the rising edge of the sampling clock signal; the comparator U55 is used for comparing the low-level bit width count value with the minimum pulse width count value; the selector A3 is used for selecting the smaller value to output according to the comparison result of the comparator U55; the selector a4 is used to send the output of the selector A3 to the flip-flop U33 when the signal output by the flip-flop U11 is active and the signal output by the flip-flop U22 is inactive.
The flip-flop U22 is used to align the received rising edge signal with the rising edge of the sampling clock signal; the comparator U44 is used for comparing the high-level bit width count value with the minimum pulse width count value; the selector A1 is used for selecting the smaller value to output according to the comparison result of the comparator U44; the selector A2 is used for sending the output of the selector A1 to the flip-flop U33 through the selector A4 when the signal output by the flip-flop U11 is invalid and the signal output by the flip-flop U22 is valid; and the flip-flop U33 is used to save the smaller of the current input value and the minimum pulse width count value as the minimum pulse width count value.
In summary, the detection device of the scheme adopts a hardware circuit design, is very suitable for realizing a CPLD or an FPGA, does not need the intervention of a processor such as a CPU or an MCU, and does not need software to perform complex floating point calculation, and is fast and intuitive in a table look-up manner, high in circuit working stability, low in cost, and convenient to use, and can obtain an effective baud rate by receiving serial port information.
Claims (7)
1. Asynchronous serial port communication baud rate automatic checkout device, its characterized in that includes:
the edge detection module is used for receiving the asynchronous serial port signal and sampling the asynchronous serial port signal through a sampling clock signal with fixed frequency to obtain a rising edge signal and a falling edge signal of the asynchronous serial port signal;
the pulse width counting module is used for generating a counting enabling signal according to the rising edge signal or the falling edge signal, and counting the effective time length of the enabling signal in real time to obtain a high-level or low-level bit width counting value;
the minimum pulse width module is used for comparing the bit width counting value of the high level or the bit width counting value of the low level with the minimum pulse width counting value and keeping a smaller value to output; and
and the table look-up module is used for inquiring the baud rate and bit width relation table stored in the table look-up module according to the value output by the minimum pulse width module to obtain the baud rate of the data sent by the asynchronous serial port.
2. The apparatus of claim 1, wherein the edge detection module comprises:
the trigger U1 is used for aligning the rising edge of the asynchronous serial port signal and the sampling clock signal;
a flip-flop U2 for delaying the signal output by flip-flop U1 aligned by one clock cycle;
the NOT gate U3 is used for inverting the signal output by the trigger U2 after time delay;
a NOT gate U4 for inverting the signal output by the flip-flop U1;
the AND gate U5 is used for performing combinational logic AND operation on the signal output after the negation operation of the NOT gate U3 and the signal output by the trigger U1 in alignment to obtain the rising edge of the asynchronous serial port signal; and
and the and gate U6 is used for performing combinational logic AND operation on the signal output after the negation operation of the NOT gate U4 and the signal output by the trigger U2 in a delayed mode to obtain the falling edge of the asynchronous serial port signal.
3. The apparatus of claim 2, wherein the clock period is 100 ns.
4. The apparatus of claim 1, wherein the pulse width counting module comprises:
the high-level pulse width counter is used for generating a counting enabling signal according to the rising edge signal and counting the time length of the enabling signal when the enabling signal is effective in real time to obtain a high-level bit width counting value;
and the low-level pulse width counter is used for generating a counting enabling signal according to the falling edge signal and counting the time length of the enabling signal when the enabling signal is effective in real time to obtain a low-level bit width counting value.
5. The apparatus of claim 1, wherein the minimum pulse width module comprises:
a flip-flop U11 for aligning the received falling edge signal with the rising edge of the sampling clock signal;
a comparator U55 for comparing the low-level bit width count value with the minimum pulse width count value;
the selector A3 is used for selecting the smaller value to output according to the comparison result of the comparator U55;
a selector a4, for sending the output of the selector A3 to the flip-flop U33 when the signal output by the flip-flop U11 is valid and the signal output by the flip-flop U22 is invalid;
a flip-flop U22 for aligning the received rising edge signal with the rising edge of the sampling clock signal;
a comparator U44 for comparing the high-level bit width count value with the minimum pulse width count value;
the selector A1 is used for selecting the smaller value to output according to the comparison result of the comparator U44;
the selector A2 is used for sending the output of the selector A1 to the flip-flop U33 through the selector A4 when the signal output by the flip-flop U11 is invalid and the signal output by the flip-flop U22 is valid; and
and a flip-flop U33 for saving the smaller value of the currently inputted value and the minimum pulse width count value as the minimum pulse width count value.
6. The apparatus according to claim 1, wherein the baud rate and bit width relation table includes the baud rate, and a statistic of time and bit width occupied by each data bit corresponding to the baud rate.
7. The apparatus of claim 6, wherein the statistical value of bit width is set with a tolerance of 3%.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114697237A (en) * | 2022-04-15 | 2022-07-01 | 北京广利核系统工程有限公司 | Bus communication cycle test system and method |
| CN116886247A (en) * | 2023-09-01 | 2023-10-13 | 珠海芯探索微电子有限公司 | Baud rate self-adaption method and device based on UART communication, UART system and medium |
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2020
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114697237A (en) * | 2022-04-15 | 2022-07-01 | 北京广利核系统工程有限公司 | Bus communication cycle test system and method |
| CN114697237B (en) * | 2022-04-15 | 2023-12-26 | 北京广利核系统工程有限公司 | Bus communication cycle test system and method |
| CN116886247A (en) * | 2023-09-01 | 2023-10-13 | 珠海芯探索微电子有限公司 | Baud rate self-adaption method and device based on UART communication, UART system and medium |
| CN116886247B (en) * | 2023-09-01 | 2023-11-21 | 珠海芯探索微电子有限公司 | Baud rate self-adaption method and device based on UART communication, UART system and medium |
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