CN104461972B - A kind of method and apparatus of data signal samples - Google Patents
A kind of method and apparatus of data signal samples Download PDFInfo
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- CN104461972B CN104461972B CN201310415776.5A CN201310415776A CN104461972B CN 104461972 B CN104461972 B CN 104461972B CN 201310415776 A CN201310415776 A CN 201310415776A CN 104461972 B CN104461972 B CN 104461972B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4295—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using an embedded synchronisation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0002—Serial port, e.g. RS232C
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- Synchronisation In Digital Transmission Systems (AREA)
Abstract
The invention discloses a kind of method and apparatus of data signal samples, main contents include：The bell idles pulse sent by DCE according to DTE during data-signal is sent, determine that the DTE sends the clock frequency of data-signal, and utilize the clock frequency, sample the data-signal that DTE is sent, so DCE goes out the clock frequency of DTE transmission data-signals according to the DTE bell idles pulse-recoveries sent during data-signal is sent, effectively prevent due to DCE sampling clock signal and DTE send data-signal between phase relation do not know, cause DCE sampling DTE send data-signal accuracy than it is relatively low the problem of.
Description
Technical field
The present invention relates to wireless communication field, more particularly to a kind of method and apparatus of data signal samples.
Background technology
Synchronous serial interface agreement（Also referred to as x.21 agreement）In, data circuit equipment（digital circuit
Equipment, abbreviation DCE）And data terminal equipment（Digital terminal equipment, abbreviation DTE）Transmission signal
It is asymmetric, i.e. not only contain data-signal to DTE device transmission signals from dce device but also contain clock signal, but by
DTE equipment only transmits data-signal to dce device transmission signal.
Generally, during the data-signal that dce device receives that DTE equipment is sent, sampling clock needs to send out with DTE equipment
Send the clock of data-signal synchronous, i.e., dce device receives the frequency and the frequency phase of DTE equipment transmission data-signal of data-signal
Together, it is necessary to which data-signal keeps stable before clock signal is changed into high level from low level and in sampled data signal,
And a period of time is kept when clock signal is high level, to ensure the accuracy of dce device sampled data signal.
But due to only containing data-signal into dce device transmission signal from DTE equipment, therefore, how in DTE
Equipment keeps the clock signal synchronization between dce device and DTE equipment to turn into important to the dce device transmission data-signal stage
Research topic.
Usual way is：Elapsed time clock source is designed in dce device, is sent to dce device by a selection circuit
The clock signal of DTE equipment receives the clock signal of DTE equipment transmission data-signal as dce device, and DTE equipment is according to reception
The clock signal that the dce device arrived is sent sends data-signal to dce device, and number is transmitted to dce device in DTE equipment to realize
The clock signal synchronization between dce device and DTE equipment is kept according to signal phase.
But when dce device is to DTE equipment tranmitting data register signals, cabling delay and cable delay between plate so that DCE
There is uncertainty in the phase relation between the data-signal that the clock signal and DTE equipment of equipment sampling are sent, cause DCE to set
The data-signal accuracy that standby sampling DTE equipment is sent is than relatively low.
The content of the invention
The embodiments of the invention provide a kind of method and apparatus of data signal samples, for solving dce device sampling DTE
Equipment send data-signal accuracy than it is relatively low the problem of.
In a first aspect, the invention provides a kind of method of data signal samples, including：
The bell idles that data circuit equipment DCE is sent according to data terminal equipment DTE during data-signal is sent
Pulse, determine that the DTE sends the clock frequency of data-signal；
Using the clock frequency, the data-signal that the DTE is sent is sampled.
In the possible embodiment of first aspect present invention, in the first possible embodiment, the DCE is determined
DTE sends the clock frequency of data-signal, including：
The DCE detects two data rising edges continuously occur during sampling the DTE and sending data-signal
When, count continuously occur two data rising edges during high frequency clock number；
Count the first count value and low level arteries and veins of high level pulse in circuit during continuously there are two data rising edges
Second count value of punching；
When according to first count value and second count value, what 8 pulses for judging to be consecutively detected were formed
When pulse signal belongs to bell idles pulse signal, the cumulative number increase setting number of the DTE transmissions bell idles pulse will be counted
Value；
Judge whether the cumulative number of the DTE transmissions bell idles pulse is more than given threshold；
If the cumulative number that the DTE sends bell idles pulse is more than given threshold, according to the clock of high frequency clock week
The number for the high frequency clock that time value and statistics obtain, the clock cycle value that the DTE sends data-signal is calculated；According to meter
The obtained DTE sends the clock cycle value of data-signal, obtains the clock frequency value that the DTE sends data-signal.
It is described in second of possible embodiment in the first possible embodiment of first aspect present invention
Method also includes：
If the cumulative number that the DTE sends bell idles pulse is not more than given threshold, statistics is obtained into high frequency clock
Number reset, and re-execute statistics continuously occur two data rising edges during high frequency clock number.
In the possible embodiment of the first aspect of the present invention, or first aspect present invention the first is possible
In embodiment, or in second of possible embodiment of first aspect present invention, the third possible embodiment
In, it is described to utilize the clock frequency, the data-signal that the DTE is sent is sampled, including：
According to the clock frequency of determination, if it is determined that the count value in clock pulses rising edge time frequency counter is not equal to
First setting numerical value, and be not currently in and receive the rising edge that the DTE sends data-signal, by the meter of the frequency counter
Numerical value increases preset value；
If increase the count value after preset value equal to the second setting numerical value, triggering samples the data that the DTE is sent and believed
Number.
It is described in the 4th kind of possible embodiment in the third possible embodiment of first aspect present invention
Method also includes：
If it is determined that the count value in clock pulses rising edge time frequency counter is equal to the first setting numerical value, or current place
In the rising edge for receiving the DTE transmissions data-signal, the count value of the frequency counter is reset.
Second aspect, the invention provides a kind of sample devices of data-signal, including：
Clock frequency determining module, for what is sent according to data terminal equipment DTE during data-signal is sent
Bell idles pulse, determine that the DTE sends the clock frequency of data-signal；
Data signal samples module, for the clock frequency determined using the clock frequency determining module, sampling
The data-signal that the DTE is sent.
In the possible embodiment of second aspect of the present invention, in the first possible embodiment,
The clock frequency determining module, specifically for during sampling the DTE and sending data-signal, detecting
When continuously there are two data rising edges, the number of high frequency clock during continuously there are two data rising edges is counted；Statistics connects
It is continuous the first count value of high level pulse and the second count value of low level pulse in circuit occur during two data rising edges；
When according to first count value and second count value, judging the pulse signal that 8 pulses being consecutively detected are formed
When belonging to bell idles pulse signal, the cumulative number increase setting numerical value of the DTE transmissions bell idles pulse will be counted；Judge institute
Whether the cumulative number for stating DTE transmission bell idles pulses is more than given threshold；
If the cumulative number that the DTE sends bell idles pulse is more than given threshold, according to the clock of high frequency clock week
The number for the high frequency clock that time value and statistics obtain, the clock cycle value that the DTE sends data-signal is calculated；According to meter
The obtained DTE sends the clock cycle value of data-signal, obtains the clock frequency value that the DTE sends data-signal.
It is described in second of possible embodiment in the first possible embodiment of second aspect of the present invention
Clock frequency determining module, if the cumulative number for being additionally operable to the DTE transmissions bell idles pulse is not more than given threshold, it will unite
The number that meter obtains high frequency clock is reset, and re-executes time for counting high frequency clock during continuously there are two data rising edges
Number.
In the possible embodiment of second aspect of the present invention, or the first possible reality in second aspect of the present invention
Apply in mode, or in second of possible embodiment of second aspect of the present invention, in the third possible embodiment,
The data signal samples module, specifically for the clock frequency according to determination, if it is determined that in clock pulses rising edge time point
The count value of frequency counter is not currently in not equal to the first setting numerical value and receives the rising that the DTE sends data-signal
Edge, the count value of the frequency counter is increased into preset value；If increasing the count value after preset value is equal to the second setting numerical value
When, triggering samples the data-signal that the DTE is sent.
It is described in the 4th kind of possible embodiment in the third possible embodiment of second aspect of the present invention
Data signal samples module, it is additionally operable to if it is determined that the count value in clock pulses rising edge time frequency counter is set equal to first
Fixed number value, or be currently at and receive the rising edge that the DTE sends data-signal, the count value of the frequency counter is clear
Zero.
The third aspect, the invention provides a kind of data circuit equipment, including processor, memory and communication interface, its
In, processor, memory and communication interface are connected by bus,
Communication interface, for being communicated with data terminal equipment DTE；
Memory, for depositing program；
Processor, for performing the program deposited in the memory, and perform in the following manner：
The bell idles pulse periodically sent during data-signal is sent according to DTE, determine that the DTE sends number
It is believed that number clock frequency；And the clock frequency is utilized, sample the data-signal that the DTE is sent.
In the possible embodiment of third aspect present invention, in the first possible embodiment,
The bell idles pulse periodically sent during data-signal is sent according to DTE, determine the DTE hairs
The clock frequency of data-signal is sent, is specifically included：
During sampling the DTE and sending data-signal, when detecting continuously two data rising edges of appearance, statistics
The number of high frequency clock during two data rising edges of continuous appearance；
Count the first count value and low level arteries and veins of high level pulse in circuit during continuously there are two data rising edges
Second count value of punching；
When according to first count value and second count value, what 8 pulses for judging to be consecutively detected were formed
When pulse signal belongs to bell idles pulse signal, the cumulative number increase setting number of the DTE transmissions bell idles pulse will be counted
Value；
Judge whether the cumulative number of the DTE transmissions bell idles pulse is more than given threshold；
If the cumulative number that the DTE sends bell idles pulse is more than given threshold, according to the clock of high frequency clock week
The number for the high frequency clock that time value and statistics obtain, the clock cycle value that the DTE sends data-signal is calculated；According to meter
The obtained DTE sends the clock cycle value of data-signal, obtains the clock frequency value that the DTE sends data-signal.
In the first possible embodiment of third aspect present invention, in second of possible embodiment, if institute
State DTE and send the cumulative number of bell idles pulse when be not more than given threshold, the number clearing that obtains high frequency clock will be counted, and
Re-execute the number for counting high frequency clock during continuously there are two data rising edges.
In the possible embodiment of third aspect present invention, or the first possible reality in third aspect present invention
Apply in mode, or in second of possible embodiment of third aspect present invention, in the third possible embodiment,
It is described to utilize the clock frequency, the data-signal that the DTE is sent is sampled, including：
According to the clock frequency of determination, if it is determined that the count value in clock pulses rising edge time frequency counter is not equal to
First setting numerical value, and be not currently in and receive the rising edge that the DTE sends data-signal, by the meter of the frequency counter
Numerical value increases preset value；If increase the count value after preset value equal to the second setting numerical value, triggering samples what the DTE was sent
Data-signal.
In the third possible embodiment of third aspect present invention, in the 4th kind of possible embodiment, if sentencing
The count value for being scheduled on clock pulses rising edge time frequency counter is equal to the first setting numerical value, or is currently at described in reception
DTE sends the rising edge of data-signal, and the count value of the frequency counter is reset.
The present invention has the beneficial effect that：
The bell idles pulse that the embodiment of the present invention is sent by DCE according to DTE during data-signal is sent, it is determined that
The DTE sends the clock frequency of data-signal, and utilizes the clock frequency, the data-signal that sampling DTE is sent, so
DCE according to DTE periodically sent during sending data-signal bell idles pulse-recovery go out DTE send data-signal when
Clock frequency, it effectively prevent because the phase relation between the data-signal that the clock signal and DTE of DCE samplings are sent is not true
It is fixed, cause the data-signal accuracy that DCE samplings DTE is sent than it is relatively low the problem of so that DCE can automatic identification DTE send
Frequency data signal, improve the accuracy of DCE sampled data signals.
Brief description of the drawings
Fig. 1 is a kind of method flow diagram of data signal samples provided in an embodiment of the present invention；
Fig. 2 is that DCE determines that DTE sends the schematic flow sheet of the clock frequency of data-signal；
Fig. 3 is the schematic flow sheet of DCE sampled data signals；
Fig. 4 is a kind of structure chart of the sample devices of data-signal provided in an embodiment of the present invention；
Fig. 5 is a kind of structure chart of data circuit equipment provided in an embodiment of the present invention.
Embodiment
In order to realize the purpose of the present invention, the embodiments of the invention provide a kind of method and apparatus of data signal samples,
The bell idles pulse sent by DCE according to DTE during data-signal is sent, determine that the DTE sends data-signal
Clock frequency, and utilize the clock frequency, sampling DTE send data-signal, such DCE according to DTE send data
The bell idles pulse-recovery periodically sent during signal goes out the clock frequency that DTE sends data-signal, effectively prevent
Phase relation between the data-signal sent due to the clock signal and DTE of DCE samplings is not known, and causes DCE sampling DTE hairs
The data-signal accuracy sent than it is relatively low the problem of so that DCE be capable of automatic identification DTE send frequency data signal, improve
The accuracy of DCE sampled data signals.
It should be noted that the embodiment of the present invention be not limited to apply DTE using synchronous serial interface agreement X.21 agreement to DCE
During transmitting data-signal.
The each embodiment of the present invention is described in detail with reference to Figure of description.
As shown in figure 1, it is a kind of method flow diagram of data signal samples provided in an embodiment of the present invention.Methods described bag
Include：
Step 101：The bell idles pulse that DCE is sent according to DTE during data-signal is sent, determine that DTE is sent
The clock frequency of data-signal.
In a step 101, synchronous serial interface agreement is passed through between DCE and DTE（Also referred to as X.21 agreement）Communicated, and held
It is High-Level Data Link Control to carry X.21 agreement（High level date link control, abbreviation HDLC）Agreement.Profit
During with HDLC protocol transmitting data stream, typically bell idles can be all sent in line idle, data frame head and data postamble.Generally
The bell idles transmitted in HDLC protocol is 0X7e, i.e., contains two low level pulses and six high level arteries and veins in every 8 pulses
Punching.Due to the bell idles 0X7e that is transmitted in HDLC protocol regularly low and high level impulse hits, it is easier to identify, contributes to
The clock frequency that DCE sends the bell idles pulse being mingled with data-signal and determine DTE transmission data-signals by continuously detecting DTE
Rate.
Specifically, as shown in Fig. 2 DCE periodically sends bell idles arteries and veins according to DTE during data-signal is sent
Punching, determine that the DTE sends the clock frequency of data-signal, specifically include：
Step 201：DCE is detected continuously and occurred in two data during sampling the DTE and sending data-signal
Rise along when, count continuously occur two data rising edges during high frequency clock number.
It should be noted that DCE is selected well known in the art when uncertain DTE sends the clock frequency of data-signal
High frequency clock performs following operation, is also not necessarily limited to the clock frequency that selection is far longer than self transmission data-signal, does not do here
It is specific to limit.Such as：The clock frequency that the DCE sends data-signal is 20MHz, then the frequency of the high frequency clock of selection is remote
Much larger than 20MHz, such as：50MHz or 100MHz.
So, during sampling the DTE and sending data-signal, detect two data rising edges continuously occur
When, the number of high frequency clock during continuously there are two data rising edges is counted, can improve and recover DTE transmission data-signals
The accuracy of clock frequency.
Such as：DCE uses 50MHz high frequency clock, statistic mixed-state to continuous high frequency during there are two data rising edges
The number that clock occurs is 10, and DCE uses 100MHz high frequency clock, and statistic mixed-state two data rising edges occurs to continuous
The number that period high frequency clock occurs is 20, it can be seen that, meaned using the high clock of frequency to one piece of data rising edge
The granularity of division is smaller, and the later stage determines that the precision of clock frequency is higher.
It should be noted that the number of high frequency clock can be, but not limited to during statistics two data rising edges of continuous appearance
Counted with counter Count0.
Alternatively, DCE can also be during continuously two data rising edges of appearance be detected, to the non-data of DTE transmissions
Signal is detected, and counts and the number of high level pulse occurs in continuous 8 pulses and the number of low level pulse occur.
Step 202：DCE counts high level pulse in circuit during continuously two data rising edges of appearance are detected
Second count value of the first count value and low level pulse.
Such as：DCE is during continuously two data rising edges of appearance are detected, it is determined that 8 pulse signals continuously occurred
Middle high level pulse（I.e. 1）The first count value, counted with counter Count1, and low level pulse（I.e. 0）Second meter
Numerical value, counted with counter Count2.
Specifically, during continuously there are two data rising edges, often there is one " 1 ", counter Count1 increases by 1,
Often there is one " 0 ", counter Count2 increases by 1, wherein, Count1+Count2=8.
Step 203：The first count value and the second count value obtained according to statistics, judges 8 pulses being consecutively detected
Whether the pulse signal formed belongs to bell idles pulse signal, if belonging to bell idles pulse signal, performs step 204；It is no
Then, end operation.
Specifically, in step 203, because the bell idles pulse signal transmitted in HDLC protocol takes 8 bytes, form
For two " 0 ", six " 1 ", change into electric signal and meet 2 low level pulses and 6 high level pulses, therefore, detecting
In 8 pulse signals continuously occurred, the first count value for high level pulse occur and the second counting for low level pulse occur
The ratio between value meets 3:1, you can 8 pulse signals of the continuous appearance for illustrating to detect form a bell idles pulse signal；It is no
Then, 8 pulse signals of the continuous appearance for illustrating to detect are not bell idles pulse signals.
Step 204：, will if the pulse signal that 8 pulses being consecutively detected are formed belongs to bell idles pulse signal
The DTE sends the cumulative number increase setting numerical value of bell idles pulse.
Wherein, the general value of numerical value that sets is 1 or other numerical value, according to being actually needed determination, this
In do not limit.
Step 205：Judge whether the cumulative number of the DTE transmissions bell idles pulse is more than given threshold, if the DTE
The cumulative number for sending bell idles pulse is more than given threshold, then performs step 206；Otherwise, step 208 is performed.
In step 205, because cable is when plug, the data-signal of DCE samplings can produce larger shake, in order to
Error detection is prevented to bell idles pulse signal, thus, it is necessary to multiple repairing weld bell idles pulse signal, therefore, given threshold one
As require to be more than 15, can so ensure to obtain the stable bell idles pulse signal sent, be favorably improved and determine that DTE sends number
It is believed that number clock frequency accuracy.
It should be noted that given threshold can also determine according to being actually needed, do not limit here.
Step 206：If the cumulative number that the DTE sends bell idles pulse is more than given threshold, according to high frequency clock
The number for the high frequency clock that clock cycle value and statistics obtain, the clock cycle value that the DTE sends data-signal is calculated.
In step 206, the clock cycle value of high frequency clock is calculated and the product value of the number of high frequency clock that statistics obtains,
And obtained product value and 8 is made into business, obtained quotient sends the clock cycle value of data-signal as the DTE is calculated.
It should be noted that the clock cycle of high frequency clock refers to that step 201 samples used high frequency clock here
Clock cycle.
Such as：The DTE sends clock cycle value/8 of clock cycle value=Count0* high frequency clocks of data-signal.
Step 207：The calculated DTE sends the clock cycle value of data-signal, obtains the DTE and sends
The clock frequency value of data-signal.
Step 208：If the cumulative number that the DTE sends bell idles pulse is not more than given threshold, statistics is obtained
The number of high frequency clock is reset, and is redirected and performed step 201.
Specifically, in a step 208, when the cumulative number that the DTE sends bell idles pulse is not more than given threshold,
The number clearing for obtaining high frequency clock will be counted, and re-execute statistics and high frequency clock during two data rising edges continuously occur
Number and judge that the DTE sends the cumulative number of bell idles pulse and whether is more than the operation of given threshold.
Step 102：The data-signal that DCE is sent using the clock frequency determined, sampling DTE.
In a step 102, DCE using itself according to DTE send data-signal and bell idles pulse signal determine when
Clock frequency, the data-signal that sampling DTE is sent.
But because dce device is different with the signal source of DTE equipment tranmitting data register signals, in order to avoid clock frequency is present
Error, it is necessary to sampling DTE send data-signal before, to determine clock frequency it is further judged, eliminate frequency
Inclined accumulation, in time amendment determine the clock frequency of sampling, it is ensured that the accuracy of sampled data signal.
Specifically, as shown in figure 3, DCE is using the clock frequency determined, the data-signal that sampling DTE is sent includes：
Step 301：According to the clock frequency of determination, judge whether current time is in the rising edge time of clock pulses,
If so, then perform step 302；Otherwise, the arrival of the rising edge time of clock pulses is continued waiting for.
Step 302：Judge whether be equal to the first setting number in clock pulses rising edge time, the count value of frequency counter
Value, and judge the current rising edge that data-signal whether is sent in the reception DTE；
If judged result be clock pulses rising edge time frequency counter count value not equal to first setting numerical value,
And be not currently in and receive the rising edge that the DTE sends data-signal, perform step 303；If judged result is in clock arteries and veins
The count value for rushing rising edge time frequency counter is equal to the first setting numerical value, or is currently at and receives the DTE transmissions data
The rising edge of signal, perform step 306.
Wherein, described first set numerical value as determine clock cycle value subtract 1.
Step 303：If judged result is the count value in clock pulses rising edge time frequency counter not equal to first
Setting numerical value and the rising edge for being not currently in the reception DTE transmissions data-signal, by the count value of the frequency counter
Increase preset value.
Wherein, the preset value can be 1, can also determine according to being actually needed, not limit here.
Step 304：Judge whether the count value after increase preset value is equal to the second setting numerical value, if so, then performing step
305；Otherwise, redirect and perform step 301.
Wherein, the described second half for setting clock cycle value of the numerical value to determine subtracts 1.
Step 305：If judged result, which is the count value after increase preset value, is equal to the second setting numerical value, the DTE is sampled
The data-signal of transmission.
Step 306：If judged result is to be equal to described the in the count value of clock pulses rising edge time frequency counter
One setting numerical value, or be currently at and receive the rising edge that the DTE sends data-signal, by the count value of the frequency counter
Reset, and redirect and perform step 301.
By the technical scheme of the embodiment of the present invention, free time that DCE is sent according to DTE during data-signal is sent
Code pulse, determine that the DTE sends the clock frequency of data-signal, and the number sent using the clock frequency determined, sampling DTE
It is believed that number, such DCE periodically sends bell idles pulse-recovery during data-signal is sent according to DTE and goes out DTE transmissions
The clock frequency of data-signal, it effectively prevent due to the phase between the data-signal that the clock signal of DCE samplings is sent with DTE
Position relation do not know, cause DCE sampling DTE send data-signal accuracy than it is relatively low the problem of so that DCE can know automatically
The frequency data signal that other DTE is sent, improve the accuracy of DCE sampled data signals.
As shown in figure 4, it is a kind of structure chart of the sample devices of data-signal provided in an embodiment of the present invention, for realizing
The method of data signal samples shown in Fig. 1~Fig. 3 of the present invention, the sample devices include：The He of clock frequency determining module 11
Data signal samples module 12, wherein：
Clock frequency determining module 11, for being sent according to data terminal equipment DTE during data-signal is sent
Bell idles pulse, determine that the DTE sends the clock frequency of data-signal；
Data signal samples module 12, for the clock frequency determined using the clock frequency determining module, adopt
The data-signal that DTE described in sample is sent.
Specifically, the clock frequency determining module 11, specifically for sampling the process of the DTE transmissions data-signal
In, when detecting continuously two data rising edges of appearance, count time of high frequency clock during continuously there are two data rising edges
Number；Statistics continuously occurs during two data rising edges the of the first count value of high level pulse and low level pulse in circuit
Two count values；When according to first count value and second count value, what 8 pulses for judging to be consecutively detected were formed
When pulse signal belongs to bell idles pulse signal, the DTE is sent to the cumulative number increase setting numerical value of bell idles pulse；Sentence
Whether the cumulative number that the disconnected DTE sends bell idles pulse is more than given threshold；
If the cumulative number that the DTE sends bell idles pulse is more than given threshold, according to the clock of high frequency clock week
The number for the high frequency clock that time value and statistics obtain, the clock cycle value that the DTE sends data-signal is calculated；According to meter
The obtained DTE sends the clock cycle value of data-signal, obtains the clock frequency value that the DTE sends data-signal.
The clock frequency determining module 11, if the cumulative number for being additionally operable to the DTE transmissions bell idles pulse is not more than
During given threshold, the number that statistics is obtained to high frequency clock is reset, and re-executes statistics and two data rising edges continuously occur
The number of period high frequency clock.
The data signal samples module 12, specifically for the clock frequency according to determination, if it is determined that in clock pulses
The count value along moment frequency counter is risen not equal to the first setting numerical value, and is not currently in and receives the DTE transmissions data
The rising edge of signal, the count value of the frequency counter is increased into preset value；If increasing the count value after preset value is equal to the
During two setting numerical value, triggering samples the data-signal that the DTE is sent.
The data signal samples module 12, specifically for if it is determined that in clock pulses rising edge time frequency counter
Count value is equal to the first setting numerical value, or is currently at and receives the rising edge that the DTE sends data-signal, and the frequency dividing is counted
The count value of number device is reset.
It should be noted that the sample devices described in the embodiment of the present invention can be the logical block in dce device, also may be used
To be integrated in the virtual software in dce device, the object entity part with dce device independence is can also be, is not limited here
It is fixed.
As shown in figure 5, it is a kind of structure chart of data circuit equipment provided in an embodiment of the present invention, for realizing the present invention
The method of data signal samples shown in embodiment Fig. 1~Fig. 3, the equipment include：Processor 21, memory 22 and communication connect
Mouth 23, wherein, processor 21, memory 22 and communication interface 23 are connected by bus 24, specifically：
Communication interface 23, for being communicated with DTE.
Memory 22, for depositing program.Specifically, program can include program code, and described program code includes meter
Calculation machine operational order.
Memory 22 may include high-speed RAM memory, it is also possible to also including nonvolatile memory (non-volatile
Memory), a for example, at least magnetic disk storage.
Processor 21 is probably a central processor CPU, or application-specific integrated circuit ASIC（Application
Specific Integrated Circuit）, or it is arranged to implement the integrated electricity of one or more of the embodiment of the present invention
Road.
The processor 21 performs the program deposited in the memory 22, realizes data letter provided in an embodiment of the present invention
Number sampling method, including：
The bell idles pulse sent according to data terminal equipment DTE during data-signal is sent, determines the DTE
Send the clock frequency of data-signal；
Using the clock frequency, the data-signal that the DTE is sent is sampled.
Wherein, it is described that bell idles pulse is periodically sent during data-signal is sent according to DTE, it is determined that described
The clock frequency that DTE sends data-signal specifically includes：
During sampling the DTE and sending data-signal, when detecting continuously two data rising edges of appearance, statistics
The number of high frequency clock during two data rising edges of continuous appearance；
Count the first count value and low level arteries and veins of high level pulse in circuit during continuously there are two data rising edges
Second count value of punching；
When according to first count value and second count value, what 8 pulses for judging to be consecutively detected were formed
When pulse signal belongs to bell idles pulse signal, the DTE is sent to the cumulative number increase setting numerical value of bell idles pulse；
Judge whether the cumulative number of the DTE transmissions bell idles pulse is more than given threshold；
If the cumulative number that the DTE sends bell idles pulse is more than given threshold, according to the clock of high frequency clock week
The number for the high frequency clock that time value and statistics obtain, the clock cycle value that the DTE sends data-signal is calculated；According to meter
The obtained DTE sends the clock cycle value of data-signal, obtains the clock frequency value that the DTE sends data-signal；
If the cumulative number that the DTE sends bell idles pulse is not more than given threshold, statistics is obtained into high frequency clock
Number reset, and re-execute statistics continuously occur two data rising edges during high frequency clock number.
It is described to utilize the clock frequency, the data-signal that the DTE is sent is sampled, including：
According to the clock frequency of determination, if it is determined that the count value in clock pulses rising edge time frequency counter is not equal to
First setting numerical value, and be not currently in and receive the rising edge that the DTE sends data-signal, by the meter of the frequency counter
Numerical value increases preset value；
If increase the count value after preset value equal to the second setting numerical value, triggering samples the data that the DTE is sent and believed
Number；
If it is determined that the count value in clock pulses rising edge time frequency counter is equal to the first setting numerical value, or current place
In the rising edge for receiving the DTE transmissions data-signal, the count value of the frequency counter is reset.
, can be with it should be noted that the data circuit equipment described in the embodiment of the present invention can be object entity part
The logical block being integrated in dce device, is not limited here.
It will be understood by those skilled in the art that embodiments of the invention can be provided as method, apparatus（Equipment）Or computer
Program product.Therefore, in terms of the present invention can use complete hardware embodiment, complete software embodiment or combine software and hardware
Embodiment form.Moreover, the present invention can use the meter for wherein including computer usable program code in one or more
Calculation machine usable storage medium（Including but not limited to magnetic disk storage, CD-ROM, optical memory etc.）The computer journey of upper implementation
The form of sequence product.
The present invention is with reference to method, apparatus according to embodiments of the present invention（Equipment）With the flow chart of computer program product
And/or block diagram describes.It should be understood that can be by each flow in computer program instructions implementation process figure and/or block diagram
And/or square frame and the flow in flow chart and/or block diagram and/or the combination of square frame.These computer programs can be provided to refer to
The processors of all-purpose computer, special-purpose computer, Embedded Processor or other programmable data processing devices is made to produce
One machine so that produced by the instruction of computer or the computing device of other programmable data processing devices for realizing
The device for the function of being specified in one flow of flow chart or multiple flows and/or one square frame of block diagram or multiple square frames.
These computer program instructions, which may be alternatively stored in, can guide computer or other programmable data processing devices with spy
Determine in the computer-readable memory that mode works so that the instruction being stored in the computer-readable memory, which produces, to be included referring to
Make the manufacture of device, the command device realize in one flow of flow chart or multiple flows and/or one square frame of block diagram or
The function of being specified in multiple square frames.
These computer program instructions can be also loaded into computer or other programmable data processing devices so that counted
Series of operation steps is performed on calculation machine or other programmable devices to produce computer implemented processing, so as in computer or
The instruction performed on other programmable devices is provided for realizing in one flow of flow chart or multiple flows and/or block diagram one
The step of function of being specified in individual square frame or multiple square frames.
Although preferred embodiments of the present invention have been described, but those skilled in the art once know basic creation
Property concept, then can make other change and modification to these embodiments.So appended claims be intended to be construed to include it is excellent
Select embodiment and fall into having altered and changing for the scope of the invention.
Claims (8)
- A kind of 1. method of data signal samples, it is characterised in that including：The bell idles pulse that data circuit equipment DCE is sent according to data terminal equipment DTE during data-signal is sent, Determine that the DTE sends the clock frequency of data-signal, including：The DCE sends the process of data-signal sampling the DTE In, when detecting continuously two data rising edges of appearance, count time of high frequency clock during continuously there are two data rising edges Number；Statistics continuously occurs during two data rising edges the of the first count value of high level pulse and low level pulse in circuit Two count values；When according to first count value and second count value, what 8 pulses for judging to be consecutively detected were formed When pulse signal belongs to bell idles pulse signal, the DTE is sent to the cumulative number increase setting numerical value of bell idles pulse；Sentence Whether the cumulative number that the disconnected DTE sends bell idles pulse is more than given threshold；If the DTE sends the tired of bell idles pulse When metering number is more than given threshold, the number of the high frequency clock obtained according to the clock cycle value of high frequency clock and statistics, calculate Obtain the clock cycle value that the DTE sends data-signal；The clock week of data-signal is sent according to the DTE being calculated Time value, obtain the clock frequency value that the DTE sends data-signal；The DCE utilizes the clock frequency, samples the data-signal that the DTE is sent.
- 2. the method as described in claim 1, it is characterised in that methods described also includes：If the cumulative number that the DTE sends bell idles pulse is not more than given threshold, time of high frequency clock is obtained by counting Number is reset, and re-executes the number for counting high frequency clock during continuously there are two data rising edges.
- 3. method as claimed in claim 1 or 2, it is characterised in that it is described to utilize the clock frequency, sample the DTE hairs The data-signal sent, including：According to the clock frequency of determination, if it is determined that the count value in clock pulses rising edge time frequency counter is not equal to first Numerical value is set, and is not currently in and receives the rising edge that the DTE sends data-signal, by the count value of the frequency counter Increase preset value；If increase the count value after preset value equal to the second setting numerical value, triggering samples the data-signal that the DTE is sent.
- 4. method as claimed in claim 3, it is characterised in that methods described also includes：If it is determined that the count value in clock pulses rising edge time frequency counter is equal to the first setting numerical value, or it is currently at and connects The rising edge that the DTE sends data-signal is received, the count value of the frequency counter is reset.
- A kind of 5. sample devices of data-signal, it is characterised in that including：Clock frequency determining module, for the free time sent according to data terminal equipment DTE during data-signal is sent Code pulse, determine that the DTE sends the clock frequency of data-signal, be specifically used for：Data-signal is sent sampling the DTE During, detect that continuously high frequency clock during two data rising edges continuously occurs in statistics when there are two data rising edges Number；Count the first count value and low level pulse of high level pulse in circuit during continuously there are two data rising edges The second count value；When according to first count value and second count value, judging 8 pulse institute shapes being consecutively detected Into pulse signal belong to bell idles pulse signal when, by the DTE send bell idles pulse cumulative number increase setting number Value；Judge whether the cumulative number of the DTE transmissions bell idles pulse is more than given threshold；If the DTE sends bell idles arteries and veins When the cumulative number of punching is more than given threshold, time of the high frequency clock obtained according to the clock cycle value of high frequency clock and statistics Number, the clock cycle value that the DTE sends data-signal is calculated；Data-signal is sent according to the DTE being calculated Clock cycle value, obtain the clock frequency value that the DTE sends data-signal；Data signal samples module, for the clock frequency determined using the clock frequency determining module, described in sampling The data-signal that DTE is sent.
- 6. sample devices as claimed in claim 5, it is characterised in thatThe clock frequency determining module, if being additionally operable to the DTE sends the cumulative number of bell idles pulse no more than setting threshold During value, the number that statistics is obtained to high frequency clock is reset, and re-executes statistics and height during two data rising edges continuously occur The number of frequency clock.
- 7. the sample devices as described in claim 5 or 6, it is characterised in thatThe data signal samples module, specifically for the clock frequency according to determination, if it is determined that in clock pulses rising edge The count value of frequency counter is carved not equal to the first setting numerical value, and is not currently in and receives the DTE transmissions data-signal Rising edge, the count value of the frequency counter is increased into preset value；If increasing the count value after preset value is equal to the second setting During numerical value, triggering samples the data-signal that the DTE is sent.
- 8. sample devices as claimed in claim 7, it is characterised in thatThe data signal samples module, it is additionally operable to if it is determined that in count value of clock pulses rising edge time frequency counter etc. Numerical value is set in first, or is currently at and receives the rising edge that the DTE sends data-signal, by the meter of the frequency counter Numerical value is reset.
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| GB2539443B (en) * | 2015-06-16 | 2020-02-12 | Advanced Risc Mach Ltd | A transmitter, a receiver, a data transfer system and a method of data transfer |
| CN108667757A (en) * | 2017-03-27 | 2018-10-16 | 航天信息股份有限公司 | Manchester code sampling processing method, module and decoder |
| CN108958701A (en) * | 2017-05-22 | 2018-12-07 | 深圳市中兴微电子技术有限公司 | A kind of data transfer control method, device and storage medium |
| CN109194459B (en) * | 2018-10-08 | 2020-11-06 | 惠科股份有限公司 | Data extraction method and device of transmission signal and storage medium |
| CN110635892A (en) * | 2019-10-12 | 2019-12-31 | 天津津航计算技术研究所 | Data sampling system based on synchronization 422 standard |
| CN110750479A (en) * | 2019-10-12 | 2020-02-04 | 天津津航计算技术研究所 | Data sampling method based on synchronization 422 standard |
| CN111711445B (en) * | 2020-06-24 | 2024-05-10 | 中国地质科学院地球物理地球化学勘查研究所 | Correction method and device for nominal frequency error and electronic equipment |
| CN112564693B (en) * | 2020-12-18 | 2024-01-05 | 北京自动化控制设备研究所 | Self-adaptive time keeping time service method |
| CN114265811B (en) * | 2022-03-03 | 2022-06-17 | 北京数码视讯技术有限公司 | FPGA-based data sampling clock edge adaptive system and method |
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