CN110635854A

CN110635854A - Transmission protocol self-adaptive decoding system and method

Info

Publication number: CN110635854A
Application number: CN201911016741.8A
Authority: CN
Inventors: 刘盛彬; 李科举
Original assignee: Limited Co Of Fu Man Electronics Group Of Shenzhen
Current assignee: Limited Co Of Fu Man Electronics Group Of Shenzhen
Priority date: 2019-10-24
Filing date: 2019-10-24
Publication date: 2019-12-31

Abstract

In the transmission protocol self-adaptive decoding system provided by the invention, the internal oscillator is used for generating a clock and providing the clock to the detection module and the pulse generation module; the detection module is used for generating an enabling control signal and transmitting the enabling control signal to the counter when a preset learning field is detected on the data line; the counter is used for counting the time length of the learning field on the data line when receiving the enabling control signal, and carrying out division operation on the counting result to output a quotient and a remainder; the judging module is used for determining the sampling pulse period according to the quotient and the remainder output by the counter; and the pulse generation module is used for generating sampling pulses according to the sampling pulse period determined by the judgment module. The system can realize the self-adaptive error-free decoding of the transmission rate in a wide range under the condition that the speed of an internal oscillator is not too high, and simultaneously reduces the consumption of hardware resources to the maximum extent so as to reduce the cost.

Description

Transmission protocol self-adaptive decoding system and method

Technical Field

The invention belongs to the technical field of integrated circuits, and particularly relates to a transmission protocol self-adaptive decoding system and a transmission protocol self-adaptive decoding method.

Background

The DMX512-1990 communication protocol is a digital multiplexing protocol that is supported by almost all light/stage equipment manufacturers today. As a widely adopted digital light data protocol, DMX512-1990 has also become an international standard for light control. The equipment of each manufacturer can be connected with each other due to the unification of the DMX512 protocol, the compatibility is improved to a great extent, in addition, the DMX512 protocol adopts a serial mode to transmit digital signals, only one signal wire is needed between a console and the equipment, and the connecting wire between a controller and the equipment is greatly simplified.

The DMX512 protocol allows for the brightness control of lighting devices by sending data packets over the bus, while the protocol itself imposes extremely strict rules on the timing of each portion of the data packet. Each field has 11 bits including a 0 start bit, an 8 bit data bit and a 2 bit stop bit. Wherein, the 0 start bit is low level, the stop bit is high level, the data in the data bit is 0, the corresponding time period is low level, the data is 1, and the corresponding time period is high level. The bit durations of the 0 start bit, stop bit and data bit must be the same. The timing diagram of DMX512 is shown in FIG. 1.

A complete DMX512 packet format consists of an MTBP signal, a BREAK signal, a MAB signal and an SC signal, and data frames. The meaning is as follows:

MTBP: the indication mark that a complete DMX512 data packet is sent is finished, and at the same time, the indication mark is the mark bit for the next data packet to start, and the high level is effective, which indicates that the current transmission line is in an idle state and no data is transmitted. BREADK: the data packet start control signal corresponds to a reset stage after one data packet is finished, data of the next packet should be sent after the reset is finished, the BREAK signal is effective in low level, and the duration time is not less than 88 uS. MAB: the protocol specifies MAB as two Bit durations, high level active. SC: i.e. the start code, which is the same as the normal data frame, but whose 8-bit data bits are all 0, indicating the start of the data frame in the data packet.

One conventional protocol decoding method is: the time width of each subsequent byte, namely the SC segment, is determined by detecting the time width of the starting byte of each frame of data, the field consists of 1 starting flag bit, 8 full zero Bits and 2 ending flags, and the time width of 9Bits 0 is easier to detect because 9Bits 0 in the starting field are between the MAB segment and 2 Bits ending flag Bits. And counting the 9Bits 0 time by a built-in oscillator, and performing division operation in the sampling process to obtain the time width of each bit. The time width is an integer multiple of the period of the oscillator, and it is common to keep an integer number of bits, but errors are accumulated when decoding each Bit of data. As shown in fig. 1, sampling is generally performed at a data center position, and a residue error is accumulated once when each Bit is decoded, for example, if a residue value is large, the accumulated error may cause a decoding error. In the method, in order to sample the time width of the initial field more accurately, the frequency of the oscillator is continuously increased, and the higher the frequency is, the smaller the maximum accumulated error obtained by using the retained integer method is relative to the sampling period.

Another existing protocol decoding method is as follows: the time width of each Bit is also obtained by detecting the time widths of 9Bits 0. However, when division is performed, a quotient and a remainder are retained, and a sampling period is determined according to the quotient and the remainder, wherein the sampling period comprises two sampling pulse intervals, namely NT is used as one sampling pulse interval and (N +1) T is used as the other sampling pulse interval, namely, the remainder in the division operation is uniformly inserted into different Bit samples so as to realize accurate data sampling. The scheme can accurately decode DMX512 data, but consumes larger hardware resources in the implementation process.

Disclosure of Invention

Aiming at the defects in the prior art, the invention provides a transmission protocol self-adaptive decoding system and a transmission protocol self-adaptive decoding method, which can realize the self-adaptive error-free decoding of a wide range of transmission rate under the condition that the speed of an internal oscillator is not too high, and simultaneously reduce the consumption of hardware resources to the maximum extent so as to reduce the cost.

In a first aspect, a transmission protocol adaptive decoding system includes an internal oscillator, a detection module, a counter, a judgment module, and a pulse generation module;

the internal oscillator is used for generating a clock and providing the clock to the detection module and the pulse generation module;

the detection module is used for generating an enabling control signal and transmitting the enabling control signal to the counter when a preset learning field is detected on the data line;

the counter is used for counting the time length of a learning field on a data line when the enabling control signal is received, carrying out division operation on a counting result and outputting a quotient and a remainder;

the judging module is used for determining a sampling pulse period according to the quotient and the remainder output by the counter;

the pulse generating module is used for generating sampling pulses according to the sampling pulse period determined by the judging module.

Preferably, the counter is specifically configured to:

performing K division operation on the counting result; where K is the number of bits of the learning field.

Preferably, the determining module is specifically configured to:

when the monitored remainder M output by the counter is larger than K/2, the sampling pulse period is set to NT, and when the monitored remainder M output by the counter is smaller than or equal to K/2, the sampling pulse period is set to (N-1) T, wherein T is the clock period generated by the internal oscillator, and N is the quotient of the output of the counter.

Preferably, the counter includes a remainder counter, and the remainder counter specifically includes L first flip-flops, first and gates, and a first logic unit connected in series; therein, 2^L≥K；

The output end of the internal oscillator is connected with the clock end of a first trigger, the forward output end of the previous first trigger is connected with the clock end of the next first trigger, the forward output end of each first trigger is connected with different input ends of the first logic unit, and the reverse output end of each first trigger is connected with the data end of the first trigger;

the output end of the detection module is connected with one input end of the first AND gate, the residue counting overflow output end of the first logic unit is connected with the other input end of the first AND gate, and the output ends of the first AND gates are connected to the reset end of the first trigger;

and the remainder counting overflow output end, the remainder output end and the quotient counting end of the first logic unit are connected to the judging module.

Preferably, the counter further comprises a quotient counter, and the quotient counter comprises P second flip-flops, a second and gate and a second logic unit connected in series;

the output end of the detection module is connected with one input end of the second AND gate, the quotient counting end of the first logic unit is connected with the other input end of the second AND gate, the output end of the second AND gate is connected with the clock end of the first second trigger, the forward output end of the front second trigger is connected with the clock end of the rear second trigger, the forward output end of each second trigger is connected with different input ends of the second logic unit, and the reverse output end of each second trigger is connected with the data end of the second trigger; the reset ends of all the second triggers are connected to the output end of the detection module;

and the quotient output end of the second logic unit is connected to the judgment module.

Preferably, the first flip-flop and the second flip-flop are both D flip-flops.

In a second aspect, a method for adaptive decoding of a transmission protocol includes the steps of:

the detection module generates an enabling control signal and transmits the enabling control signal to the counter when detecting a preset learning field on a data line;

when the counter receives the enabling control signal, the time length of a learning field on the data line is counted, the counting result is divided, and a quotient and a remainder are output;

the judging module determines a sampling pulse period according to the quotient and the remainder output by the counter;

and the pulse generation module generates sampling pulses according to the sampling pulse period determined by the judgment module.

Preferably, the dividing operation of the counter on the counting result specifically includes:

the counter performs K division operation on the counting result; where K is the number of bits of the learning field.

Preferably, the determining, by the determining module, a sampling pulse period according to a quotient and a remainder output by the counter specifically includes:

when monitoring that the remainder M output by the counter is larger than K/2, the judging module sets the sampling pulse period to be NT, and when monitoring that the remainder M output by the counter is smaller than or equal to K/2, the sampling pulse period is set to be (N-1) T, wherein T is the clock period generated by the internal oscillator, and N is the quotient output by the counter.

According to the technical scheme, the transmission protocol self-adaptive decoding system and the transmission protocol self-adaptive decoding method provided by the invention have the advantages that the time length of the preset learning field is calculated, division operation is carried out, the sampling pulse is generated by rounding the remainder, and the subsequent data of the learning field is sampled. Under the condition that the speed of the internal oscillator is not required to be too high, the self-adaption error-free decoding of the transmission rate in a wide range can be realized, and meanwhile, the consumption of hardware resources is reduced to the maximum extent so as to reduce the cost.

Drawings

In order to more clearly illustrate the detailed description of the invention or the technical solutions in the prior art, the drawings that are needed in the detailed description of the invention or the prior art will be briefly described below. Throughout the drawings, like elements or portions are generally identified by like reference numerals. In the drawings, elements or portions are not necessarily drawn to scale.

Fig. 1 is a diagram illustrating a packet format of the DMX512 protocol mentioned in the background art.

Fig. 2 is a block diagram of a system according to an embodiment of the present invention.

Fig. 3 is a circuit diagram of the counter of fig. 2.

Fig. 4 is a timing diagram of the circuit of fig. 3.

FIG. 5 is a timing diagram of the remainder M being greater than K/2.

FIG. 6 is a timing diagram of the remainder M being equal to or less than K/2.

Fig. 7 is a flowchart of a method provided in the third embodiment of the present invention.

Detailed Description

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The following examples are only for illustrating the technical solutions of the present invention more clearly, and therefore are only examples, and the protection scope of the present invention is not limited thereby. It is to be noted that, unless otherwise specified, technical or scientific terms used herein shall have the ordinary meaning as understood by those skilled in the art to which the invention pertains.

It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the specification of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

As used in this specification and the appended claims, the term "if" may be interpreted contextually as "when", "upon" or "in response to a determination" or "in response to a detection". Similarly, the phrase "if it is determined" or "if a [ described condition or event ] is detected" may be interpreted contextually to mean "upon determining" or "in response to determining" or "upon detecting [ described condition or event ]" or "in response to detecting [ described condition or event ]".

The first embodiment is as follows:

a transmission protocol adaptive decoding system, see fig. 2, includes an internal oscillator, a detection module, a counter, a judgment module, and a pulse generation module;

In particular, the SC field may be selected as the learning field, for example, for the DMX512 protocol. The system can be applied to decoding of any protocol, when the system is used, only the start code in the protocol needs to be set as the learning field, and after the system learns the sampling period of the learning field, the sampling period of the protocol can be obtained, and the sampling pulse in the subsequent field decoding process is determined.

Aiming at the DMX512 protocol, a detection module samples and clocks transmission data on a data line through high-speed clock frequency division, when the duration of the transmission data on the data line is detected to be low level and exceeds 88uS, namely the received data packet is considered to be a start control signal MTBP, the detection module continues to monitor a MAB signal, and when the transmission data on the data line is detected to be low level after the MAB is finished, the detection module considers that the SC field starts to be received, generates an enabling control signal and transmits the enabling control signal to a counter, and controls the counter to start timing.

Counting the time length of the SC start code when the counter starts to count, and performing K-removing operation on the counting result; where K is the number of digits of the learning field, where K ═ 9. And the judging module determines the sampling pulse period according to the quotient and the remainder output by the counter. For example, when the remainder M of the monitored counter output is greater than K/2, the sampling pulse period is set to NT, and when the remainder M of the monitored counter output is less than or equal to K/2, the sampling pulse period is set to (N-1) T, where T is the clock period generated by the internal oscillator and N is the quotient of the counter output.

To further illustrate the accuracy of the system decoding, error analysis was performed using the DMX512 protocol described above. When the learning field data is 9Bits, the remainder range is 1-8, and after the system processing, the error range is reduced to 1-4. Assuming that the maximum error value 4 is calculated, the SC error of the start Bit is ((4/9)/2) T, and the error of (4/9) T is accumulated when decoding each Bit, i.e. the sampling error of the last Bit of each frame of data is 8.5 × T (4/9) 3.78T. Therefore, all Bit bits are guaranteed to be correctly sampled by only satisfying (N/2) T > 3.78T. In the current application requirement, the rate of the DMX512 protocol is 250Kbps to 750Kbps, that is, the minimum time width of each bit is 1.3us, and if N is 8, the internal oscillator frequency only needs to reach 6.2MHz to ensure that data is normally sampled. When the frequency is raised to 20MHz, the adaptive error-free decoding of DMX512 with higher transmission rate can be supported.

The system samples subsequent data of the learning field by calculating the time length of the preset learning field, performing division operation and generating sampling pulses for remainders in a rounding mode. Under the condition that the speed of the internal oscillator is not required to be too high, the self-adaption error-free decoding of the transmission rate in a wide range can be realized, and meanwhile, the consumption of hardware resources is reduced to the maximum extent so as to reduce the cost.

Example two:

the second embodiment provides the following contents on the basis of the first embodiment:

referring to fig. 3, the counter includes a remainder counter, and the remainder counter specifically includes L first flip-flops, first and gates, and a first logic unit connected in series; therein, 2^L≥K；

An output end OSC of the internal oscillator is connected with a clock end of a first trigger, a forward output end Q of the first trigger is connected with a clock end of the second trigger, a forward output end Q of each first trigger is connected with different input ends of the first logic unit, and a reverse output end QN of each first trigger is connected with a data end D of the first trigger;

an output end CNT _ EN of the detection module is connected with one input end of the first AND gate, a remainder count Overflow output end M _ Overflow of the first logic unit is connected with the other input end of the first AND gate, and the output ends of the first AND gate are connected to a reset end R of the first trigger;

the remainder count Overflow output end M _ Overflow, the remainder output end M _ CNT and the quotient count end N _ CLK of the first logic unit are connected to the judging module.

Specifically, OSC is the clock output from the internal oscillator, and CNT _ EN is the output terminal of the detection module, and is used to output the enable control signal to the counter. When the entry start code SC is received, CNT _ EN is set to 1, and the counter starts counting. M _ Overflow is a remainder counter Overflow mark, when the remainder counter overflows, a pulse signal is generated at a remainder count Overflow output end M _ Overflow, the remainder counter is reset, and the counting is started again. At this point, an N _ CLK pulse is output as a quotient counter clock indicating that one count cycle period has been received.

an output end CNT _ EN of the detection module is connected with one input end of the second AND gate, a quotient counting end N _ CLK of the first logic unit is connected with the other input end of the second AND gate, an output end of the second AND gate is connected with a clock end of a first second trigger, a forward output end Q of the previous second trigger is connected with a clock end of the next second trigger, a forward output end Q of each second trigger is connected with different input ends of the second logic unit, and a reverse output end QN of each second trigger is connected with a data end D of the second trigger; the reset terminals R of all the second flip-flops are connected to the output terminal CNT _ EN of the detection module;

the quotient output end N _ CNT of the second logic unit is connected to the judging module.

Preferably, the first flip-flop and the second flip-flop are both D flip-flops.

Specifically, the number of second flip-flops in the quotient counter depends on the length of the SC field and the internal oscillator frequency. The remainder counter overflows once and the quotient counter performs an increment operation of 1 to generate the quotient N of the division operation, the timing of which is shown in fig. 4.

After the counter finishes counting, the determining module sets the sampling pulse period to NT or (N-1) T according to whether the remainder counter result is greater than K/2, and writes the sampling pulse period into the latch of the pulse generating module to generate the sampling pulse of the corresponding frequency, for example, for the DMX512 protocol, when the remainder M is greater than K/2, the timing diagram thereof is shown in fig. 5, and when the remainder M is less than or equal to K/2, the timing diagram thereof is shown in fig. 6.

For the sake of brief description, the system provided by the embodiment of the present invention may refer to the corresponding content in the foregoing embodiments.

Example three:

a method for adaptive decoding of a transmission protocol, see fig. 7, comprising the steps of:

s1: the detection module generates an enabling control signal and transmits the enabling control signal to the counter when detecting a preset learning field on a data line;

s2: when the counter receives the enabling control signal, the time length of a learning field on the data line is counted, the counting result is divided, and a quotient and a remainder are output;

s3: the judging module determines a sampling pulse period according to the quotient and the remainder output by the counter;

s4: and the pulse generation module generates sampling pulses according to the sampling pulse period determined by the judgment module.

The method comprises the steps of calculating the time length of a preset learning field, carrying out division operation, generating sampling pulses by rounding a remainder, and sampling subsequent data of the learning field. Under the condition that the speed of the internal oscillator is not required to be too high, the self-adaption error-free decoding of the transmission rate in a wide range can be realized, and meanwhile, the consumption of hardware resources is reduced to the maximum extent so as to reduce the cost.

For the sake of brief description, the method provided by the embodiment of the present invention may refer to the corresponding contents in the foregoing embodiments.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention, and they should be construed as being included in the following claims and description.

Claims

1. A self-adaptive decoding system of a transmission protocol is characterized by comprising an internal oscillator, a detection module, a counter, a judgment module and a pulse generation module;

2. The transport protocol adaptive decoding system of claim 1, wherein the counter is specifically configured to:

3. The system according to claim 2, wherein the determining module is specifically configured to:

4. The system according to claim 2, wherein the counter comprises a remainder counter, and the remainder counter specifically comprises L first flip-flops, first and gates, and a first logic unit connected in series; therein, 2^L≥K；

5. The adaptive decoding system according to claim 4, wherein the counter further comprises a quotient counter, the quotient counter comprising P second flip-flops, a second AND gate, and a second logic unit connected in series;

6. The transport protocol adaptive decoding system of claim 5,

the first trigger and the second trigger are both D triggers.

7. A method for adaptive decoding of a transmission protocol, comprising the steps of:

8. The method according to claim 7, wherein the dividing the counting result by the counter specifically comprises:

9. The adaptive decoding method for transmission protocol according to claim 8, wherein the determining, by the determining module, the sampling pulse period according to the quotient and the remainder output by the counter specifically comprises: