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CN103561008A - Method and device for decoding transport protocol and transport protocol decoding chip - Google Patents

Method and device for decoding transport protocol and transport protocol decoding chip Download PDF

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CN103561008A
CN103561008A CN 201310513788 CN201310513788A CN103561008A CN 103561008 A CN103561008 A CN 103561008A CN 201310513788 CN201310513788 CN 201310513788 CN 201310513788 A CN201310513788 A CN 201310513788A CN 103561008 A CN103561008 A CN 103561008A
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signal
decoding
sampling
period
quotient
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CN 201310513788
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CN103561008B (en )
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胡富斌
李照华
石磊
符传汇
杨亚吉
戴文芳
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深圳市明微电子股份有限公司
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    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02BINDEXING SCHEME RELATING TO CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. INCLUDING HOUSING AND APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B20/00Energy efficient lighting technologies
    • Y02B20/40Control techniques providing energy savings
    • Y02B20/42Control techniques providing energy savings based on timing means or schedule

Abstract

The invention belongs to the field of communication, and provides a method and device for decoding a transport protocol and a transport protocol decoding chip. The method comprises the following steps that an oscillator signal is generated; a frame start signal is detected, and a sampling control signal is output when the frame start signal is detected; after the sampling control signal is received, the oscillation period of the oscillator signal is counted within the time period of a frame start byte low-level digit, a division operation is carried out on count values, and a quotient and a remainder are output; a sampling period is determined according to the quotient and the remainder to generate a sampling pulse, and a data byte is decoded according to the sampling pulse. The oscillation period of the oscillator signal is counted within the time period of the frame start byte low-level digit, the division operation is carried out on the count values to obtain the quotient and the remainder, decoding is carried out according to the quotient and the remainder, no accumulation error is generated, decoding accuracy is greatly improved, achievement is simple, cost is low, and stability is good.

Description

一种传输协议解码方法、装置及传输协议解码芯片技术领域[0001] 本发明属于通信领域,尤其涉及一种传输协议解码方法、装置及传输协议解码芯片。 A transmission protocol decoding method, decoding apparatus and transmission protocol chip Technical Field [0001] The present invention belongs to the field of communications, particularly to a transmission protocol decoding method, decoding apparatus and transmission protocol chip. 背景技术[0002] 随着数字技术及计算机技术的应用和普及,出现了电脑调光台,并先后出现了D54、AVAB, CMX、PMX、EMX等模拟及数字通信协议。 [0002] With the application of digital technology and popularization of computer technology and the emergence of computer lighting console, and has appeared D54, AVAB, CMX, PMX, EMX and other analog and digital communication protocols. 由于以上协议标准是各生产厂家各自的协议标准,因而它们之间的兼容性不好,设备之间的相互通用存在问题。 Due to the above protocol standard is the manufacturers of the respective protocol standards, compatibility between them is not good and therefore, a problem common to each other between the devices. 后来,为了解决各个厂家设备通用性的问题,美国剧场技术协会(United State Institute for Theatre Technology,USITT)于20世纪80年代初制定了DMX512协议。 Later, in order to solve the common problem of all manufacturers equipment, American Theater Technology Association (United State Institute for Theatre Technology, USITT) DMX512 protocol developed in the early 1980s. DMX512协议是一种数字多路复用(Digital Multiplex, DMX)协议。 DMX512 protocol is a digital multiplexer (Digital Multiplex, DMX) protocol. 协议制定后,经过修改,USITT于1990年将DMX512 协议更规范,形成了DMX512-1990。 After the agreement is made, modified, USITT DMX512 protocol in 1990 will be more standardized, forming a DMX512-1990. 目前几乎所有的灯光及舞台设备生产厂商都支持此控制协议,作为广泛采用的数字灯光数据协议,DMX512-1990也成为灯光控制的国际标准。 Almost all of the lighting and stage equipment manufacturers to support this protocol control, as digital lighting data protocol widely used, DMX512-1990 also become the international standard for light control. [0003] DMX512协议的统一使得各厂家的设备可相互连接,兼容性大大提高。 Uniform [0003] DMX512 protocol so that the manufacturers of devices can be connected to each other, greatly improved compatibility. 同时,由于DMX512协议采用串行方式传送数字信号,控台与设备之间只要一根信号线即可,大大简化了控制台与设备之间的连接线。 Meanwhile, since the DMX512 protocol employed serially transmitting digital signals, as long as a control signal line between the station and the devices can greatly simplify the connection line between the console and the device. [0004] DMX512协议可通过在总线上发送数据包来实现对灯光设备的亮度调节。 [0004] DMX512 protocol by sending packets over the bus to allow adjustment of the brightness of the lighting device. 协议对数据包的每一部分的时序都做了极为严格的规定。 The timing of each part of the protocol packets have done a very stringent requirements. 每字节有11位数据,I位低电平起始位,8 位数据位和2位高电平停止位。 11 bits per byte, the I-bit low-level start bit, 8 data bits and 2 stop bits high. 一帧数据包含I个地址的亮度数据,第I帧是第I个地址的数据,第2帧是第2个地址的数据,以此类推,512帧可以传送512个地址的数据。 A luminance data includes address data I, the first data of the I frame is the I-th address, the second frame is the data of the second address, and so on, data can be transmitted 512 512 addresses. DMX512 时序图如图1所示。 DMX512 timing chart shown in Fig. [0005] 说明如下表:[0006]编号 说明 时隙要求1 帧起始或结束 88us2 帧起始标志位 8us3 I个完整字节 Ilbits数据4 字节起始标志位,必需为“O” Ibits数据5 字节的LSB Ibits数据6 字节的MSB Ibits数据7 字节结束标志位,必需为“I`” I`bits数据 [0005] described as follows: [0006] Number Description slot starting or ending in claim 1 88us2 8us3 I frame start flag byte Ilbits complete data 4-byte start flag is necessary to "O" Ibits Data 5 LSB Ibits data bytes 6 bytes 7 bytes MSB Ibits end data flag, it is necessary to "i`" I`bits data

Figure CN103561008AD00051

[0007] 标准的DMX512协议中,每个bits的数据宽度是固定的,为4us,也就是数据传输速率为250Kbps (每秒钟传输250Kbits数据)。 [0007] standard DMX512 protocol, the data width of each of the bits is fixed for 4us, i.e. a 250Kbps data transmission rate (per second data transmission 250Kbits). [0008] 现有的协议解码方式为:[0009] 通过监测每帧数据的起始字节时间宽度,来确定后续每个字节的时间宽度。 [0008] The conventional way protocol decoder: [0009] By monitoring the starting time of each frame data byte width, the width of each subsequent time is determined byte. 以标准的DMX512协议为例,起始字节的组成为:1个起始标志位(“O”)+8个字节数据位(8个“O”)+2个结束标志位(2个“I”)。 A standard DMX512 protocol as an example, the composition of the starting byte: a start flag bit ( "O") + 8 bytes of data bits (8 "O") + 2 th bit end flag (2 "I"). 按照标准DMX512协议,该起始字节的宽度为44us。 According to standard DMX512 protocol, the start byte width of 44us. 由于在起始字节中的9个bits “O”是介于帧起始标志位(“I”)和2个字节结束标志位(2个“I”)之间的,那么这9个bits “O”的时间宽度比较好监测。 Since the start byte is 9 bits "O" is between the start of frame flag ( "I") between the flag (2 "I") and the end of 2 bytes, then this 9 bits "O" time width is better monitored. [0010] 现有做法其一是根据采样数据,来选择采样周期的方式,例如,通过内部振荡器, 产生几种采样周期Tl,T2,T3,通过对起始字节的采样,来选取最适合的一种采样周期。 [0010] One conventional approach is based on the sampling data, the sampling period of the selected mode, e.g., by an internal oscillator, to produce several sampling periods Tl, T2, T3, by sampling the starting byte to select the most for a sampling period. 该方法简单,但是针对多种采样数据下选择相同的预设采样周期,使得解码误差很大,特别是不能够做到对频率提升后的采样全覆盖。 The method is simple, but the same preset for the selected plurality of sampled data at sampling period, the decoding error so large, in particular not able to do the sampling frequency to enhance full coverage. 也就是说,在某些频段内可采样,某些频段内不能采样,例如在200~300Kbps,400~500Kbps内能采样,但是在300~400Kbps内不能采样。 That is, in certain frequency bands can be sampled, the sampling is not certain frequency bands, for example, can be sampled in the 200 ~ 300Kbps, 400 ~ 500Kbps, but not in samples 300 ~ 400Kbps. [0011] 另外一种做法是从机内包含一个内置振荡器(周期为T),通过对起始字节的9个bits “O”时间计数,例如,时间为T9bits,除以9,得到每个bit的时间宽度Tbit。 [0011] Another approach is from the machine contains a built-in oscillator (period T), the time counted by nine bits start byte "O", e.g., time T9bits, by 9, to give each a bit time width Tbit. 当然,也可以在采样过程中进行除法运算。 Of course, the division may be performed during the sampling process. 而由于采样通常采用数字处理方式,该时间宽度Tbit应为振荡器周期的整数倍N*T以避免误差产生,而实际情况中N—般为T9bits/9得到,难以控制为整除数,假设T9bits/9=8.6。 And because usually sampled digital processing, the time width Tbit should be a multiple of N * T in order to avoid an error generated as a whole oscillator cycle, the actual situation as to give N- T9bits / 9, is difficult to control divisible assumed T9bits /9=8.6. [0012]目前通常采用保留整数位的做法,那么上述数据,选取N=8,在进行每个字节数据解码时,会有积累误差。 [0012] It usually reserved bit integer practice, the above data, select N = 8, each byte of data during decoding, an error will be accumulated. 如图1所示,一般会在数据字节的中心位置采样,采样点位置为N (1/2+1) T,这样,在解码每个字节的起始位时,会有[(8.6-8)/2] T=0.3T的误差;在解码每个字节的第I个数据位时,会有[(8.6-8) X 1.5] T=0.9T的误差;以此类推,在解码每个字节的第8个数据位时,积累误差为:[(8.6-8) X8.5]T=4.1T的误差;特别的,在极端情况下当T9bits/9=8.99,在解码每个字节的第8个数据位时,积累误差约为8.5T,这样会产生解码错误。 As illustrated, typically one sample in the central position of the data byte, as the sampling point position N (1/2 + 1) T, so that, when decoding the start bit of each byte, there is [(8.6 -8) / 2] T = 0.3T of error; at decoding I-th byte of each data bit, there will be [(8.6-8) X 1.5] T = 0.9T error; and so on, in decoding each byte of 8 bits of data, the accumulated error is: [(8.6-8) X8.5] T = 4.1T error; in particular, and in extreme cases when T9bits / 9 = 8.99, decoding each byte is 8 data bits, accumulation of error is about 8.5t, so that decoding errors occur. 因此一般选取采样位置为(N/2) T>8.5Τ。 Selecting a sampling location is therefore generally (N / 2) T> 8.5Τ. 以保证在解码每个字节的第8个数据位时, 不会采样到第7个数据位上。 In order to ensure the decoding of each byte is 8 data bits, is not sampled onto the first 7 data bits. [0013] 然而,为了更精确地对起始字节时间宽度采样,不断提高从机振荡器的频率越高越好。 [0013] However, in order to more accurately to the width of the sampling time of the start byte, the frequency of the local oscillator to continuously improve the higher the better. 因为频率越高,采用保留整数法所得到的最大积累误差,相对于采样周期而言会越小。 Because the higher the frequency, the maximum accumulated error using reserved method integer obtained relative terms the smaller the sampling period. 在上述例子中,在标准DMX512协议中,每个bit的时间宽度为4us,如果N=16,那么内部振荡器的周期为4us/16=0.25us,频率为4MHz。 In the above example, the standard DMX512 protocol, each bit of the time width 4us, if N = 16, then the internal oscillator period 4us / 16 = 0.25us, a frequency of 4MHz. [0014] 在实际应用中,在保证刷新率情况下,需要连接更多的从机。 [0014] In practice, to ensure the refresh rate, it is necessary to connect more slaves. 也就是说,需要将数据传输速率提升。 In other words, the data transfer rate needs to be improved. 如果在上述内部振荡频率基础上解更高频率的码,譬如解码率达到500Kbps,那么最大的积累误差仍然为8.5T,而如果N=8,就会解码错误。 If the solution in said internal oscillation frequency on the basis of a higher frequency code, such as the decoding rate of 500Kbps, then the maximum accumulated error still 8.5t, if N = 8, a decoding error will be. 那么只有通过提升芯片内部振荡器频率的做法。 Then only by raising chip internal oscillator frequency approach. 振荡器频率从4MHz提升到8MHz,这样N=16。 The oscillator frequency from 4MHz to lift 8MHz, so that N = 16. 以此类推,如果需要解码率达到1Mbps,那么需要内部振荡器的频率至少是16MHz。 So, if desired decoding rate of 1Mbps, then the required frequency of the internal oscillator is at least 16MHz. 但是在现有集成电路基础上,达到上兆赫兹的频率,频率越大,芯片在不同时期生产的稳定性越难保证。 However, in the conventional integrated circuit on the basis of the megahertz frequency is reached, the larger the frequency, the chip at different times more difficult to ensure the stability of production. [0015] 因此,现有传输协议解码方法由于采样周期的积累误差导致难以保证解码的准确率,并且通过提升芯片内部振荡器频率的做法来提升数据传输率以降低解码误差成本高, 实现复杂,稳定性差。 [0015] Thus, the conventional transmission protocol decoding method due to the accumulation error sampling period makes it difficult to guarantee the accuracy of decoding and to improve the data transfer rate by increasing the frequency of the internal oscillator chip approach to reduce the high cost of the decoding error, implementation complexity, poor stability. 发明内容[0016] 本发明实施例的目的在于提供一种传输协议解码方法,旨在解决目前解码方法存在采样周期积累误差导致解码不精确,实现复杂、成本高、稳定性差的问题。 SUMMARY OF THE INVENTION [0016] The object of embodiments of the present invention is to provide a transmission protocol decoding method, to solve the problems existing decoding method of decoding sampling period leads to accumulation of errors inaccurate, implementation complexity, high cost, poor stability. [0017] 本发明实施例是这样实现的,一种传输协议解码方法,所述方法包括下述步骤:[0018] 生成振荡信号;[0019] 检测帧起始信号,并在检测到所述帧起始信号时,输出采样控制信号;[0020] 接收到所述采样控制信号后,在帧起始字节低电平位数的时间周期内对所述振荡信号的振荡周期进行计数,并对所述计数值进行除法运算,输出商和余数;[0021] 根据商和余数确定采样周期,以生成采样脉冲,并根据所述采样脉冲对传输数据中的数据字节进行解码。 [0017] Example embodiments of the present invention is implemented as a transmission protocol decoding, the method comprising the steps of: [0018] generating an oscillating signal; [0019] a frame start signal is detected, and the detected frame when the start signal, sampling the output control signal; [0020] after receiving the sampling control signal, for counting the oscillation period of the oscillating signal is within the low byte of the number of bits of the frame start time period, and the division count value, outputting the quotient and remainder; [0021] the quotient and remainder determine the sampling period, to generate a sampling pulse, and decodes the data byte of the transmission data in accordance with the sampling pulses. [0022] 本发明实施例的另一目的在于提供一种传输协议解码装置,所述装置与驱动单元连接,包括:[0023] 振荡器,用于生成振荡信号;[0024] 控制器,用于检测帧起始信号,并在检测到所述帧起始信号时,输出采样控制信号,所述控制器的输入端接收传输数据;[0025] 除法运算单元,用于在接收到所述采样控制信号后,在帧起始字节低电平位数的时间周期内对所述振荡信号的振荡周期进行计数,并对所述计数值进行除法运算,输出商和余数,所述除法运算单元的控制端与所述控制器的输出端连接,所述除法运算单元的输入端与所述振荡器的输出端连接;[0026] 解码单元,用于根据所述商和余数确定采样周期,以生成采样脉冲,并根据所述采样脉冲对传输数据中的数据字节进行解码,所述解码单元的第一输入端与所述除法运算单元的第一输出端连接,所述 [0022] Another object of an embodiment of the present invention is to provide a transmission protocol decoding apparatus, the apparatus is connected with the drive unit, comprising: [0023] an oscillator for generating an oscillation signal; [0024] a controller for detecting a frame start signal, and upon detection of the frame start signal, sampling the output control signal input of the controller receives the transmission data; [0025] division unit for receiving the control samples after the signal is carried out at a low number of bits of the frame start byte time period of the oscillation period of the oscillation signal count, and the count value of the division operation, the output quotient and the remainder, the division unit control terminal and an output terminal connected to said controller, said input connected to the output of the oscillator division unit; [0026] decoding unit, for determining a sampling period based on the quotient and remainder to generate sampling pulse, and the sampling pulses according to the data byte transmission data decoding, said decoding unit, a first output terminal of the first input terminal is connected to the division means, the 码单元的第二输入端与所述除法运算单元的第二输出端连接,所述解码单元的第三输入端与所述控制器的输入端连接以接收传输数据,所述解码单元的时钟端与所述振荡器的输出端连接,所述解码单元的输出端与所述驱动单元连接。 A second input coupled to said code division means connected to the second output unit, the decoding unit and the input of the third input terminal of the controller connected to receive the transmission data, said decoding clock terminal unit an output terminal connected to the oscillator, the output of the decoding unit is connected to the driving unit. [0027] 本发明实施例的另一目的在于提供一种采用上述传输协议解码装置的传输协议解码芯片。 [0027] Another object of an embodiment of the present invention to provide a transport protocol decoder chip using the above-described transmission protocol decoding apparatus. [0028] 本发明实施例通过在帧起始字节低电平位数的时间周期内对振荡信号的振荡周期进行计数,并对计数值进行除法运算,得到商和余数,根据商和余数进行解码,没有积累误差产生,无需通过提升数据传输率降低解码误差,大大提高了解码的准确率,并且实现简单,成本低,稳定性好。 [0028] Example embodiments of the present invention, by counting the oscillation period of the oscillation signal in the low byte of the number of bits of the frame start time period, and the count value of the division is performed to obtain the quotient and remainder, according to the quotient and remainder decoding, there is no accumulation error is generated, by increasing the data transfer rate without lowering the decoding error, greatly improving the accuracy of decoding, and simple, low cost, good stability. 附图说明[0029] 图1为DMX512协议时序解码不意图;[0030] 图2为本发明一实施例提供的传输协议解码方法的流程图;[0031] 图3为本发明另一实施例提供的传输协议解码方法的流程图;[0032] 图4为本发明实施例提供的传输协议解码装置的结构图;[0033] 图5为本发明实施例提供的传输协议解码装置中除法运算单元的一实现示例电路图;[0034] 图6示出了本发明实施例提供的传输协议解码装置中解码单元的一实现示例结构图;[0035] 图7为本发明实施例提供的由状态机实现传输协议解码方法的流程图。 BRIEF DESCRIPTION [0029] Figure 1 is not intended to DMX512 protocol decoding timing; flowchart transmission protocol decoding method according to an embodiment of [0030] the present invention, FIG. 2; a further embodiment of the [0031] present invention provides 3 a flowchart of a method for transmitting protocol decoding; [0032] FIG 4 is a configuration diagram of the transmission protocol decoding device according to an embodiment of the invention; [0033] FIG. 5 of the present invention provide a transmission protocol decoding apparatus according to the embodiment of the cell division a circuit diagram of the implementation example; [0034] FIG. 6 illustrates an implementation example of the present invention is a configuration diagram of the transmission protocol decoding apparatus provided in the embodiment of the decoding unit; [0035] FIG. 7 realize the transmission of the present invention is provided by the state machine of the embodiment flowchart protocol decoding method. 具体实施方式[0036] 为了使本发明的目的、技术方案及优点更加清楚明白,以下结合附图及实施例,对本发明进行进一步详细说明。 DETAILED DESCRIPTION [0036] To make the objectives, technical solutions and advantages of the present invention will become more apparent hereinafter in conjunction with the accompanying drawings and embodiments of the present invention will be further described in detail. 应当理解,此处所描述的具体实施例仅仅用以解释本发明,并不用于限定本发明。 It should be understood that the specific embodiments described herein are only intended to illustrate the present invention and are not intended to limit the present invention. [0037] 本发明实施例在帧起始字节低电平位数的时间周期内对振荡信号的振荡周期进行计数,并对计数值进行除法运算,根据商和余数进行解码,没有积累误差产生,大大提高了解码的准确率。 [0037] Example embodiments of the present invention is carried out at a low number of bits of the frame start byte time period for counting the oscillation period of the oscillation signal, and the count value of the division is performed, according to the decoding quotient and a remainder, no accumulation of errors generated , greatly improving the accuracy of decoding. [0038] 图2示出了本发明一实施例提供的传输协议解码方法的流程,为了便于说明,仅不出了与本发明相关的部分。 [0038] FIG. 2 shows a flow of transmission protocol decoding method according to an embodiment of the present invention, for convenience of description, not only the parts related to the present invention. [0039] 在步骤SlOl中,振荡器生成振荡信号OSC ;[0040] 在步骤S102中,控制器检测帧起始信号,并在检测到帧起始信号时,输出采样控制信号;[0041 ] 在本发明实施例中,该帧起始信号为传输数据中每一帧的第一个低电平,参见图1 中的编号I,控制器检测传输数据的每一巾贞中的巾贞起始信号的低电平时间宽度,当低电平时间大于预设时间宽度时,控制器确认检测到帧起始信号,并输出采样控制信号,例如,在标准DMX512协议中,该帧起始信号低电平时间宽度大于88US,而对于类DMX512协议,控制器也可以根据该协议的帧起始信号低电平时间宽度设定检测预设时间宽度。 [0039] In step SlOl, the oscillator generates an oscillation signal OSC; [0040] In step S102, the controller detects a frame start signal, and upon detection of a frame start signal, the control signal output sampling; [0041] in embodiments of the present invention, the frame start signal is a low level for the first transmission data of each frame, see FIG. 1 in number I, Fok each towel in the transmission data controller detects the starting towel Fok low-level time width of the signal, when the low time is greater than the predetermined time width, the controller detects a frame start signal is confirmed, and outputs the sampling control signal, for example, in standard DMX512 protocol, the frame start signal is low 88US level period is greater than the width, and for class DMX512 protocol, the controller may set the predetermined time width based on the detection of the frame start signal of a low level protocol time width. [0042] 在步骤S103中,除法运算单元接收到采样控制信号后,在帧起始字节低电平位数的时间周期内对振荡信号OSC的振荡周期T进行计数,并对计数值Naits进行除法运算,输出商和余数;[0043] 在本发明实施例中,帧起始字节为传输数据每一帧的帧起始信号后第一个字节(包括I位低电平起始位、8位数据位和2位高电平停止位),参见图1中第一个编号3所标示的部分,除法运算单元当接收到采样控制信号后,以振荡周期为单位,以帧起始字节的下降沿作为计数开始,以帧起始字节的上升沿作为计数结束,在帧起始字节低电平位数的采样时间周期内对振荡周期T进行计数,得到与帧起始字节低电平位数的采样时间周期相对应的时钟个数(计数值NKbits),那么起始字节的时间宽度为Nkbits.T,其中T是振荡器周期。 After [0042] In step S103, the division unit receives the sampling control signal, the start byte in the frame digit of the time period of low oscillation period T of the oscillation signal OSC is counted, and the count value for Naits division, the quotient and remainder output; [0043] in an embodiment of the present invention, a frame start byte as the first byte after the start of each frame transmission of the signal frame data (including the low-level start bit bit I , 8 data bits and 2 stop bits after the high level), see figure 1 a first portion as indicated by number 3, the division unit when receiving sampling control signal to the oscillation period as a unit, the frame start as byte count start falling to the rising edge of the frame as a start byte count end, the oscillation period T counted during the sampling time period of a frame start byte low number of bits, the frame start obtained clock low median number of bytes corresponding to the sampling time period (count value NKbits), then the time for the start byte width Nkbits.T, where T is the period of the oscillator. [0044] 进而,除法运算单元对该计数值Naits做除法运算,得到商N和余数M,即N.K+M=Nkbits。 [0044] Furthermore, the division of the count value of the unit do Naits division, quotient and remainder N M, i.e., N.K + M = Nkbits. 其中,K为帧起始字节低电平的对应的位数。 Wherein, K is the number of bits corresponding byte frame start low.

[0045] 以标准DMX512协议为例,由于该协议帧起始字节低电平位为9位(参考图1和表1),除法运算单元在接收到采样控制信号和振荡周期T后,以帧起始字节的下降沿作为计数开始,以振荡器输出的振荡周期T为单位,以起始字节的上升沿作为计数结束,检测到帧起始字节的时间宽度N9bits.T,对N9bits做除9运算,得到商N和余数M,其中9.N+M=N9bits。 [0045] In standard DMX512 protocol as an example, since the low-level protocol frame start byte is 9 bits (refer to FIG. 1 and Table 1), division means after receiving a sampling control signal and the oscillation period with T, as the fall of the frame start byte count start to the oscillation period T of the oscillator output units to the rising edge of start byte as the end count of the detected frame start byte time width N9bits.T, for 9 do N9bits addition operation, quotient and remainder N M, where 9.N + M = N9bits.

[0046] 当然,类DMX512协议中,可以任意设定帧起始字节低电平的时间宽度Nkbits.T及低电平对应的位数K,也可以任意设定传输数据字节位数j。 [0046] Of course, the class DMX512 protocol, may be arbitrarily set the frame start time width Nkbits.T low byte and a low level corresponding to the number of bits K, may be arbitrarily set the number of bits of transmitted data bytes j . 相应的,除法运算为Nkbits^K, 它由两部分组成,其中N为商,M为余数,并且N.K+M=Nkbits,其中M为O至(k-Ι)内的任意整数。 Accordingly, the division of Nkbits ^ K, which consists of two parts, where N is a supplier, M is the remainder, and N.K + M = Nkbits, wherein M is O to (k-Ι) within an arbitrary integer. 由于通常在数据字节的中心位置采样,因此后续起始位的采样周期为(N/2)T,数据字节(有j个位)中的采样周期为Tsamp=TN或Tsamp=T.(N+1),其中有(jX)个Tsamp=TN和X 个Tsamp=T.(N+1),其中,X=M.(j+K)。 Since the sample is generally the central position of the data byte, subsequent sampling period of the start bit (N / 2) T, the data bytes (with j bits) of the sampling period Tsamp = TN or Tsamp = T. ( N + 1), which (jX) one of X and Tsamp = TN Tsamp = T. (N + 1), wherein, X = M. (j + K).

[0047] 在步骤S104中,解码单元根据商和余数确定采样周期,以生成采样脉冲,并根据该采样脉冲对传输数据中的数据字节进行解码。 [0047] In step S104, the decoding unit in accordance with the sampling period is determined quotient and a remainder, to generate a sampling pulse, and decodes the data byte of the transmission data in accordance with the sampling pulses.

[0048] 在本发明实施例中,解码单元根据商N和余数M,确定采样周期,该采样周期包括两种采样脉冲间隔,进而根据这两种采样脉冲间隔对每一帧中的数据字节采样,进行解码, 上述数据字节是指在每一帧首字节后面的多个字节,以标准DMX512协议为例,帧起始字节的位数为9,每个数据字节的位数也为9 (其中第I位为1'bO)。 [0048] In an embodiment of the present invention, a decoding unit according to the supplier and I N M number, determine the sampling period, the sampling cycle comprises two sampling pulses, and thus each frame interval data bytes in accordance with the sampling pulse of both samples, decoding the plurality of bytes of data bytes in the back refers to the first byte of each frame, the standard DMX512 protocol as an example, a frame start byte is 9 bits, each data byte bit 9 is also the number (where I is the bit 1'bO). 每个数据字节对应9个采样脉冲,每个脉冲间的时间宽度,通过N和M控制。 Each data byte corresponds to nine sampling pulses, the time between each pulse width, controlled by N and M. 其中,为了采样准确,一般在每个bit的中心位置采样,即起始位的采样点距离该数据字节起始位下降沿宽度为(N/2) T,后续的8 个数据位采样脉冲间隔为(N+1) T或者NT,其中N+1的个数为M,N的个数为(9-M),并且可以通过插值法设置采样脉冲间隔为(N+1) T或者NT。 Wherein, for accurate sampling, sampling generally at the center of each bit, i.e., the start bit of the data byte from the sample point falling start bit width (N / 2) T, the subsequent eight bits of data sampling pulse interval of (N + 1) T or NT, where N + 1 number is M, the number of N (9-M), and the sampling pulses may be provided by interpolation interval (N + 1) T or NT .

[0049] 作为本发明一实施例,解码单元可以采用多个解码器、递减器、状态机以及控制模块实现,例如,采用第一递减器递减数据字节位数j,第二递减器递减余数M,第三递减器递减采样周期。 [0049] As an embodiment of the present invention, the decoding unit may employ a plurality of decoders, decrementer, and a control module implemented state machine, e.g., using a first byte of data bits decrementer decrements j, the second remainder decrementer decrements M, decrementer decrements the third sampling period.

[0050] 该状态机的状态转换图可以为:[0051] 0000 — 0001 — 0010 — 0011 — 0100 — 0101 — 0110 — 0111 — 1000 — 0000......。 [0050] The state transition diagram of the state machine may be: [0051] 00 --0001--0010-- 0011 --0100--0101-- 0110 --0111--1000-- 0000 ....... [0052] 例如,采样到起始字节的时间宽度为176T,那么经过除9处理后,得到N=19,M=5, 用二进制表示为N=5,blOOll, M=4,bOlOl。 [0052] For example, the sampling time of the start byte width 176T, 9 then removed therefrom to give N = 19, M = 5, with the binary representation of N = 5, blOOll, M = 4, bOlOl. [0053] 采样起始位时,将采样点设定为5' b01001。 [0053] When the start bit sampling, sampling point is set to 5 'b01001. 其后的数据位采样周期分别为5次5' bl0100,3次5' blOOll。 Subsequent data bit sampling period were 5 times 5 'bl0100,3 times 5' blOOll. 并且,在分布时,尽量采用插入分布的方式,譬如从起始位到第8数据位的采样周期如图7所示。 Further, when the distribution, distribution as far as possible inserted, such as from the start bit to 8-bit data of the sampling period as shown in FIG. [0054] 具体采样过程为:以每个数据字节的下降沿作为采样数据开始,起始位的采样点为(N/2)T,若M=3,通过状态机设置插值,例如,设置第2个采样脉冲与第I个采样脉冲的间隔为(N+1) T,第3个采样脉冲与第2个采样脉冲的间隔为(N+1) T,第4个采样脉冲与第3 个采样脉冲的间隔为(N+1) T,第5个采样脉冲与第4个采样脉冲的间隔为NT,第6个采样脉冲与第5个采样脉冲的间隔为NT,第7个采样脉冲与第6个采样脉冲的间隔为NT,第8个采样脉冲与第7个采样脉冲的间隔为NT,第9个采样脉冲与第8个采样脉冲的间隔为NT。 [0054] DETAILED sampling process is as follows: the falling edge of each byte of data as the sampling data start, start bit sample points (N / 2) T, if M = 3, the interpolation is provided via a state machine, for example, provided the second sampling pulse and the I-th sampling pulse interval of (N + 1) T, the interval of three sampling pulse and the second sampling pulse is (N + 1) T, the fourth sample pulse 3 interval sampling pulse is (N + 1) T, an interval of five sampling pulses and the fourth sampling pulse is NT, the interval of six sampling pulse of the fifth sampling pulse is NT, seventh sampling pulse and sixth sampling pulse interval is NT, the eighth sampling pulse interval of the first sampling pulse 7 is NT, and the ninth sampling pulse interval of the eighth sample pulse is NT. 可以理解地,上述每个采样脉冲间隔的选择可以通过改变状态机的状态转换值的设置而变化设置,例如将第3个采样脉冲与第2个采样脉冲的间隔设置为NT,第8个采样脉冲与第7 个采样脉冲的间隔设置为(N+1)T,而每发出一次采样脉冲,第一递减器、第二递减器和第三递减器应相应地递减数据字节位数j、余数M以及采样周期。 Understandably, each of said sampling pulse selection interval may be varied by changing the set value of the setting state transition of the state machine, for example, the third interval and the second sampling pulse sample pulse is NT, the eighth sample pulse interval and the second sampling pulse for seven (N + 1) T, and each time the sampling pulse is emitted, a first down, a second and a third decrementer decrements accordingly be decremented byte data bits j, remainder M and the sampling period. [0055] 本发明实施例通过在帧起始字节低电平位数的时间周期内对振荡信号的振荡周期进行计数,并对计数值进行除法运算,得到商和余数,根据商和余数确定确定采样周期(采样脉冲间隔),进而根据该采样周期对每一帧中的数据字节采样,进行解码,没有积累误差产生,无需通过提升数据传输率降低解码误差,大大提高了解码的准确率,并且实现简单,成本低,稳定性好。 [0055] Example embodiments of the present invention, by counting the oscillation period of the oscillation signal in the low byte of the number of bits of the frame start time period, and the count value of the division operation, the quotient and remainder obtained, determined according to the quotient and remainder determine the sampling period (sampling pulse interval), and further based on the sampling period sampling the data bytes in each frame is decoded, there is no accumulation error is generated, without lowering the decoding error by increasing the data transfer rate, greatly improving the accuracy of decoding and simple, low cost and good stability. [0056] 图3示出了本发明另一实施例提供的传输协议解码方法的流程,为了便于说明, 仅不出了与本发明相关的部分。 [0056] FIG. 3 shows a flow of transmission protocol decoding method according to another embodiment of the present invention, for convenience of description, not only the parts related to the present invention. [0057] 在步骤S201中,振荡器生成振荡信号OSC ;[0058] 在步骤S202中,控制器检测帧起始信号,并在检测到帧起始信号时,输出采样控制信号;[0059] 在步骤S203中,除法运算单元接收到采样控制信号后,在帧起始字节低电平位数的时间周期内对振荡信号OSC的振荡周期T进行计数,并对计数值Naits进行除法运算,输出商和余数;[0060] 在步骤S204中,根据商N生成第一采样周期和第二采样周期;[0061] 在步骤S205中,将数据字节位数j写入第一递减器,将余数M写入第二递减器;[0062] 在步骤S206中,根据第一递减器和第二递减器的递减结果,将第一采样周期或第二采样周期写入第三递减器;[0063] 在步骤S207中,根据第三递减器的递减结果生成采样脉冲;[0064] 在步骤S208中,根据采样脉冲对传输数据中的每一帧中的数据字节采样,进行解码。 [0057] In step S201, the oscillator generates an oscillation signal OSC; [0058] In step S202, the controller detects a frame start signal, and upon detection of a frame start signal, the control signal output sampling; [0059] in after step S203, the division unit receives the sampling control signal, the start byte in the frame digit of the time period of low oscillation period T of the oscillation signal OSC is counted, and the counted value Naits a division operation, the output quotient and a remainder; [0060] in step S204, the provider generates N first sampling period and the second period based on sampling; [0061] in step S205, the data written in the first byte bits j decrementer, the remainder a second write decrementer M; [0062] in step S206, according to the result of the decrement of the first and second decrementer decrements, the sampling period of the first or the second sampling period a third write decrementer; [0063] in step S207, the result of the decrement is generated according to the third sampling pulse decrementer; [0064] in step S208, the data according to a sampling pulse in each frame in the transmission data byte samples, decoded. [0065] 在本发明实施例中,根据商N和振荡信号OSC的周期生成初始采样周期(N/2) T, 将数据字节位数j (此例中为9)写入第一递减器,并将该初始采样周期(N/2) T写入第三递减器,第一递减器根据振荡信号OSC的周期开始减I操作,此时第三递减器也在振荡信号OSC的周期控制下进入递减程序,并在递减为O时输出第一个采样脉冲,同时,根据商N生成第一采样周期(N+1 )T和第二采样周期ΝΤ,并将余数M写入第二递减器,在状态机的控制下将第一采样周期(N+1) T或第二采样周期NT写入第三递减器,当状态机控制第一采样周期(N+1) T写入第三递减器时,第二递减器均递减I,而第三递减器在被写入第一采样周期(N+DT或第二采样周期NT后进行递减,直到递减为O时输出第二个采样脉冲,同时再次将第一采样周期(N+1 )Τ或第二采样周期NT写入第三递减器中,直到第一递减器递减为零 [0065] In an embodiment of the present invention, generates an initial sampling cycle periods according to N and the supplier of the oscillation signal OSC (N / 2) T, the number of bits of data bytes j (9 in this example) written in the first decrementer period, and the initial sample period (N / 2) T is written down a third, a first decrement begins I Save operation according to the period of the oscillation signal OSC, at this time the third decrementer also under the control of the oscillation signal OSC down into the program and is decremented when the output of the first sampling pulse is O, simultaneously, a first supplier to generate N sampling period according to (N + 1) T and the second sampling period ΝΤ, and writes the remainder of the second decrementer M , under the control of the state machine of the first sampling cycle (N + 1) T or the second sampling period a third write decrementer NT, when the state machine controls the first sampling cycle (N + 1) T is written down a third when, a second decrementer decrements both I, and the third is written down in the first sampling cycle (N is decremented after a second sampling period DT or NT +, is decremented when the output of the second sampling pulse is O, again the first sample period while the (N + 1) Τ second or third sampling period NT write decrementer, the decrementer decrements to zero until the first 而每一次在第一采样周期(N+1) T被写入第三递减器中时,第二递减器均减I,直到第二递减器递减为零,如此循环将依次输出j个采样脉冲,完成整个数据字节的采样操作。[0066] 若不采用状态机,也可以先对第三状态机写入第一采样周期(N+1)T,并判断第二递减器是否为零,若第二递减器不为零,则继续向第三递减器写入第一采样周期(N+1)T, 直到第二递减器递减为零,再将第二采样周期NT写入第三递减器,直到第一递减器递减为零。当第一递减器递减为零时,则表示该数据字节采样完成。[0067] 本发明实施例通过在帧起始字节低电平位数的时间周期内对振荡信号的振荡周期进行计数,并对计数值进行除法运算,得到商和余数,根据商和余数确定确定采样周期(采样脉冲间隔),进而根据该采样周期对每一帧中的数据字节采样,进行解码,没有积累误差产生 Every time when the third decrementer is written in the first sampling cycle (N + 1) T, both the second decrementer Save I, until the second decrementer decrements to zero, and so the sampling pulses are sequentially output j , complete the sampling operation of data bytes. [0066] if state machine, may be first written in the first sampling cycle (N + 1) T of a third state machine, and determines whether a second down to zero, If the second does not decremented to zero, then continue to write down the first to the third sampling cycle (N + 1) T, until the second decrementer decrements to zero, then the second sampling period a third write down NT it is, until the first down is decremented to zero. when the first decrementer decrements to zero, it indicates that the complete data byte sample. embodiment [0067] the present invention is illustrated by the low byte of the frame start digit the oscillation period of the oscillation signal of the counting time period, and the count value of the division operation, the quotient and a remainder the quotient and the remainder is determined to determine the sampling period (sampling pulse interval), and further based on the sampling cycle of each frame sampling data bytes, decoding, there is no accumulation error is generated 无需通过提升数据传输率降低解码误差,大大提高了解码的准确率,并且实现简单,成本低,稳定性好。[0068] 图4示出了本发明实施例提供的传输协议解码装置的结构,为了便于说明,仅示出了与本发明相关的部分。[0069] 作为本发明一实施例,该传输协议解码装置与驱动单元202连接,包括:[0070] 振荡器102,用于生成振荡信号OSC ;[0071] 在本发明实施例中,可以在芯片内集成内置振荡器102,用来提供预设振荡周期T 的振荡信号0SC,也可以从外部接收具有预设振荡周期T的振荡信号。[0072] 控制器101,用于检测帧起始信号,并在检测到帧起始信号时,输出采样控制信号, 控制器101的输入端接收传输数据;[0073] 在本发明实施例中,该帧起始信号为传输数据中每一帧的第一个低电平,参见图1 中的编号I,控制器检测传输数据的每一巾贞中的巾贞起始信号的低电 By increasing the data transfer rate without lowering the decoding error, greatly improving the accuracy of decoding, and simple, low cost, good stability. [0068] FIG. 4 shows the structure of the present invention, the transmission protocol decoding apparatus according to an embodiment, for ease of description, only the parts related to the present invention [0069] as an embodiment of the present invention, the transmission protocol decoding apparatus 202 is connected with the drive unit, comprising: [0070] oscillator 102 for generating an oscillating signal OSC; [0071] in an embodiment of the present invention, may be integrated within the chip internal oscillator 102 for providing an oscillation signal 0SC preset oscillation period T, you may also receive a predetermined oscillation signal having an oscillation period T from the outside. [0072] the controller 101, for detecting the frame start signal, and upon detection of a frame start signal, sampling the output control signal input terminal of the controller 101 receives the transmission data; [0073] in the embodiment of the present invention, the frame start signal of the first low transmission data of each frame, see figure 1 numbered I, Fok towel low start signal of each towel Zhen controller detects data transmission 时间宽度,当低电平时间大于预设时间宽度时,控制器101确认检测到帧起始信号,并输出采样控制信号。 Time width when the width of the low time is greater than a preset time, the controller 101 detects a frame start signal is confirmed, and outputs the sampling control signals. [0074] 作为本发明一实施例,控制器101可以采用状态机或时间检测装置实现。 [0074] As an embodiment of the present invention, the state machine controller 101 or the time detecting means may be employed to achieve. [0075] 除法运算单元103,用于在接收到采样控制信号后,在帧起始字节低电平位数的时间周期内对振荡信号OSC的振荡周期T (脉冲)进行计数,并对计数值Naits进行除法运算, 输出商和余数,除法运算单兀103的控制纟而与控制器101的输出纟而连接,除法运算单兀103 的输入端与振荡器102的输出端连接;[0076] 在本发明实施例中,帧起始字节为传输数据每一帧的帧起始信号后第一个字节, 除法运算单元103当接收到采样控制信号后,以振荡周期为单位,以帧起始字节的下降沿作为计数开始,以帧起始字节的上升沿作为计数结束,在帧起始字节低电平位数的采样时间周期内对振荡周期T进行计数,得到与帧起始字节低电平位数的采样时间周期相对应的时钟个数(计数值NKbits),并对该计数值NKbits做除法运算,得到商N和余数M,即N.K+M=Nkbits。 [0075] dividing unit 103, after receiving a sampling control signal, counting the oscillation period of the oscillation signal OSC T (pulses) in frame start byte low number of bits of the time period, and the count Naits value for division, the output of the quotient and remainder, division Si single control Wu and 103 connected to the output of the controller 101 of Si, Wu division single input terminal and the output terminal 103 is connected to the oscillator 102; [0076] in an embodiment of the present invention, a frame start byte is the first byte of each frame after the frame start signal of data transmission, the division unit 103 when receiving a sampling control signal to the oscillation unit of cycle, frame as the edges of the start byte count start, the rising edge of the frame as a start byte count end, the oscillation period T counted during the sampling time period of a frame start byte low number of bits, the frame obtained the number of clock start byte low number of bits corresponding to the sampling time period (count value NKbits), and make the division count value NKbits, quotient and remainder N M, i.e., N.K + M = Nkbits . 其中,K为帧起始字节低电平的对应的位数。 Wherein, K is the number of bits corresponding byte frame start low. 那么起始字节的时间宽度为Nkbits.T,其中T是振荡器102周期。 Then the time for the start byte width Nkbits.T, where T is the period of the oscillator 102. [0077] 作为本发明一实施例,除法运算单元103可以通过除法器和计数器实现。 [0077] As the present invention, division section 103 may be implemented by a counter and a divider embodiment. [0078] 解码单元104,用于根据商和余数确定采样周期,以生成采样脉冲,并根据该采样脉冲对传输数据中的数据字节进行解码,解码单元104的控制端与控制器101的输出端连接,解码单元104的第一输入端与除法运算单元103的第一输出端连接,解码单元104的第二输入端与除法运算单元103的第二输出端连接,解码单元104的第三输入端与控制器101 的输入端连接以接收传输数据,解码单元104的时钟端与振荡器102的输出端连接,解码单元104的输出端与驱动单元202连接。 [0078] decoding unit 104, in accordance with the sampling period for determining the quotient and remainder to generate a sampling pulse, and the transmission data of the data bytes for output control of the decoder, and the decoding unit 104 of the controller 101 according to the sampling pulse terminal is connected, a first output of the decoder unit 104 and a first input terminal connected to the division unit 103, a second output of the decoder unit 104 and a second input terminal connected to the division unit 103, a third input of the decoding unit 104 terminal and the input terminal of the controller 101 is connected to receive the transmission data, the decoding unit 104 and an output of the clock oscillator 102 is connected to the output terminal of the decoding unit 104 and driving unit 202 is connected. [0079] 在本发明实施例中,解码单元104根据商N和余数M,确定采样周期,该采样周期包括两种采样脉冲间隔,进而根据这两种采样脉冲间隔对每一帧中的数据字节采样,进行解码,上述数据字节是指在每一帧首字节后面的多个字节,以标准DMX512协议为例,帧起始字节的位数为9,每个数据字节的位数也为9 (其中第I位为1'bO)。 [0079] In an embodiment of the present invention, the decoding unit 104 according to the supplier and the remainder N M, determine the sampling period, the sampling cycle comprises two sampling pulses, and thus the data word for each frame in accordance with a sampling pulse interval of two section samples, decoding the plurality of bytes of data bytes in the back refers to the first byte of each frame, the standard DMX512 protocol as an example, a frame start byte is 9 bits, each data byte 9 is also the number of bits (bit where I is 1'bO). 每个数据字节对应9个采样脉冲,每个脉冲间的时间宽度,通过N和M控制。 Each data byte corresponds to nine sampling pulses, the time between each pulse width, controlled by N and M. 其中,为了采样准确,一般在每个bit的中心位置采样,即起始位的采样点距离该数据字节起始位下降沿宽度为(N/2) T,后续的8个数据位采样脉冲间隔为(N+1) T或者NT,其中N+1的个数为M,N的个数为(9-M), 并且可以通过插值法设置采样脉冲间隔为(N+1) T或者NT。 Wherein, for accurate sampling, sampling generally at the center of each bit, i.e., the start bit of the data byte from the sample point falling start bit width (N / 2) T, the subsequent eight bits of data sampling pulse interval of (N + 1) T or NT, where N + 1 number is M, the number of N (9-M), and the sampling pulses may be provided by interpolation interval (N + 1) T or NT . [0080] 本发明实施例通过在帧起始字节低电平位数的时间周期内对振荡信号的振荡周期进行计数,并对计数值进行除法运算,得到商和余数,根据商和余数进行解码,没有积累误差产生,无需通过提升数据传输率降低解码误差,大大提高了解码的准确率,并且实现简单,成本低,稳定性好。 [0080] Example embodiments of the present invention, by counting the oscillation period of the oscillation signal in the low byte of the number of bits of the frame start time period, and the count value of the division is performed to obtain the quotient and remainder, according to the quotient and remainder decoding, there is no accumulation error is generated, by increasing the data transfer rate without lowering the decoding error, greatly improving the accuracy of decoding, and simple, low cost, good stability. [0081] 图5示出了本发明实施例提供的传输协议解码中除法运算单元的一实现示例电路,为了便于说明,仅示出了与本发明相关的部分。 [0081] FIG. 5 shows a circuit example of the present invention to achieve a transport protocol division decoding unit according to an embodiment, for convenience of explanation, only the parts related to the present invention. [0082] 作为本发明一实施例,该除法运算单元103采用除法器和计数器实现,可以通过触发器实现除法电路,也可以采用其他逻辑器件实现,以标准DMX512协议为例,可以采用四个D触发器实现的除九电路,其中D触发器DFFl和D触发器DFF2组成了除3电路,该电路的状态转换为:00 — 01 — 10 — 00……[0083] D触发器DFF3和D触发器DFF4也组成除3电路,进而组成了除9电路。 [0082] As an embodiment of the present invention, the division unit 103 is implemented using a counter and a divider, the division can be implemented by the flip-flop circuit, may also use other logic device, the standard DMX512 protocol as an example, may be employed four D flip-flop circuit implemented in addition to nine, wherein D flip-flops DFF2 DFFl and D flip-flop circuit 3 in addition to the composition, the state of the circuit is converted to: 00 - 01 - 10 - 00 ...... [0083] D and D flip-flops DFF3 trigger composition 3 is also DFF4 circuit other, and then form the addition circuit 9. [0084] 该除法运算单元103包括:[0085] 第一D触发器DFFl、第二D触发器DFF2、第三D触发器DFF3、第四D触发器DFF4、 第一或非门0R1、第二或非门0R2、二进制计数器131以及逻辑运算模块132 ;[0086] 第一D触发器DFFl的复位端RD1、第二D触发器DFF2的复位端RD2、第三D触发器DFF3的复位端RD3、第四D触发器DFF4的复位端RD4同时为除法运算单元13的控制端, 第一D触发器DFFl的时钟输入端CKl、第二D触发器DFF2的时钟输入端CK2为除法运算单元13的输入端,第二D触发器DFF2的触发端D2与第一D触发器DFFl的正向输出端QO连接,第一或非门ORl的第一输入端与第一D触发器DFFl的正向输出端QO连接,第一或非门ORl的第二输入端与第二D触发器DFF2的正向输出端Ql连接,第一或非门ORl的输出端同时与第一D触发器DFFl的触发端D1、第三D触发器DFF3的时钟输入端CK3、第四D触发器DFF4的时钟输入端CK4连接,第四D触 [0084] The division unit 103 comprises: [0085] a first D flip-flop DFFl, a second D flip-flops DFF2, the third D flip-flops DFF3, a fourth D flip-flop DFF4, a first NOR gate 0R1, second NOR gate 0R2, binary counter 131 and logic operation module 132; [0086] a first D flip-flop RD1 DFFl a reset terminal of the second D flip-flop reset terminal RD2 DFF2, DFF3 third D flip-flop reset terminal RD3, the fourth D flip-flop reset terminal RD4 DFF4 while the control terminal of division unit 13, a clock input CKl of the first D-flipflop DFFl, DFF2 second D flip-flop clock input terminal CK2 is inputted division unit 13 end, trigger terminal D2 of the second D flip-flop DFF2 and the positive output terminal of the first D flip-flop DFFl QO is connected to the positive output of the first NOR gate a first input of the first D flip-ORl of DFFl QO is connected, a first NOR gate ORl a second input terminal connected to the positive output terminal of the second D flip-flop DFF2 Ql, the output of the first NOR gate ORl while the trigger input of a first D flip-flop D1 DFFl , a third clock input CK3 of the D flip-flops DFF3, CK4 clock input terminal of the fourth D flip-flop DFF4 is connected to a fourth D flip- 器DFF4的触发端D4与第三D触发器DFF3的正向输出端Q2连接,第二或非门0R2的第一输入端与第三D触发器DFF3的正向输出端Q2 连接,第二或非门0R2的第二输入端与第四D触发器DFF4的正向输出端Q3连接,第二或非门0R2的输出端同时与第三D触发器DFF3的触发端D3和二进制计数器131的时钟输入端CK连接,二进制计数器131的输出端为除法运算单元13的第一输出端,第一D触发器DFFl 的正向输出端Q0、第二D触发器DFF2的正向输出端Q1、第三D触发器DFF3的正向输出端Q2、第四D触发器DFF4的正向输出端Q3依次于逻辑运算模块132的第一输入端、第二输入端、第三输入端、第四输入端连接,逻辑运算模块132的输出端为除法运算单元13的第二输出端。 DFF4 trigger terminal D4 is forward of the third D flip-flop output terminal Q2 the DFF3 is connected, 0R2 of the second NOR gate first input terminal connected to the positive output terminal of the third D flip-flop Q2 the DFF3, a second or the second input of NAND gate 0R2 positive output of the fourth D flip flop DFF4 Q3 is connected to the output terminal of the second NOR gate 0R2 while the third D flip-flops DFF3 and the trigger terminal D3 of the binary counter 131 clock an input terminal CK connected to the output terminal of the binary counter 131 to a first output of division unit 13, a first positive output terminal Q0 of the D flip-DFFl, a second positive output terminal Q1 of the D flip-flops DFF2, third the positive output terminal Q2 of the D flip-flops DFF3, the positive output terminal of the fourth D flip-flop DFF4 Q3 sequentially to the first input terminal of the logic operation module 132, a second input terminal, a third input, a fourth input terminal is connected , the output terminal of the logic operation module 132 for dividing the output of the second arithmetic unit 13. [0087] 在本发明实施例中,振荡器102输出的振荡信号OSC通过四个D触发器DFF1-DFF4 进行计数并除九运算后,通过二进制计数器131得到商N,而余数M需要经过逻辑运算模块132的逻辑转换后得到,M用二进制数表示为M3M2M1Mtl,其逻辑转换式为:[0088] [0087] In an embodiment of the present invention, the oscillation signal OSC outputted from the oscillator 102 is counted by the four D flip-flops DFF1-DFF4 and the nine other operation, the binary counter 131 by the quotient N, M and go through the remainder logic operation after the logic conversion module 132 is obtained, M a binary number M3M2M1Mtl, logic conversion equation is: [0088]

Figure CN103561008AD00111
Figure CN103561008AD00121

[0092] 其中,Q0-Q3分别为D触发器DFF1-DFF4正向输出端输出的逻辑状态,并由该逻辑转换式得到如下对应表格: [0092] where, Q0-Q3 are D flip-flops DFF1-DFF4 positive output terminal of the logic state output by the logic conversion table corresponding to obtain the following formula:

Figure CN103561008AD00122

[0094] 在本发明实施例中,逻辑运算模块132可由多个逻辑门根据余数M的逻辑表达式连接而成,此处不再赘述。 [0094] In an embodiment of the present invention, a logic operation module 132 may be a plurality of logic gates connected in accordance with the logical expression of M residue, is not repeated here. [0095] 图6示出了本发明实施例提供的传输协议解码中解码单元的一实现示例结构,为了便于说明,仅示出了与本发明相关的部分。 [0095] FIG. 6 illustrates an implementation example of the present invention, a transport protocol decoder structure in the decoder provided in the embodiment, for convenience of description, only the parts related to the present invention. [0096] 作为本发明一实施例,解码单元104包括:[0097] 第一递减器141、第二递减器142、第三递减器143、控制模块144、状态机145以及解码器146 ;[0098] 控制模块144的第一输入端为解码单元104的第一输入端,控制模块144的第二输入端为解码单兀104的第二输入端,控制模块144的第一输出端与第一递减器141的输入端连接,控制模块144的第二输出端与第二递减器142的输入端连接,控制模块144的第三输出端与第三递减器143的输入端连接,状态机145的输出端与控制模块144的第三输入端连接,控制模块144的时钟端为译码单元的时钟端,控制模块144的输出端与解码器146的第一输入端连接,解码器146的第二输入端为解码单元104的第三输入端,解码器146的输出端为解码单元104的输出端。 [0096] As an embodiment of the present invention, the decoding unit 104 comprises: [0097] a first decrementer 141, 142 down the second, third decrementer 143, the control module 144, a state machine 145 and a decoder 146; [0098 ] the first input terminal of the control module 144 to a first input of a decoding unit 104, a second input terminal of the control module 144 is a decoding unit 104 Wu second input terminal, a first output terminal of the control module 144 and a first down an output connected to an input terminal 141, the control module 144 a second input terminal and the second output terminal is connected to decrementer 142, the control module 144 of the third output terminal and the third input of decrementer 143 is connected to the state machine 145 a third input terminal connected to the control module 144, a control module 144 to the clock terminal clock terminal of the decoding unit, the control module 144 of the output of the decoder 146 is connected to a first input terminal, a second input 146 of the decoder a third input terminal of the decoding unit 104, the output of the decoder 146 of the decoding unit 104 is an output terminal. [0099] 在本发明实施例中,控制模块144根据商N生成第一采样周期和第二采样周期,并将数据字节位数j写入第一递减器141,将接收的余数M写入第二递减器142,控制模块144根据第一递减器141和第二递减器142的递减结果,将第一采样周期(N+1)T或第二采样周期NT写入第三递减器143,并根据第三递减器143的递减结果生成采样脉冲,根据该采样脉冲解码器146对传输数据中的每一帧中的数据字节采样,进行解码。 [0099] In an embodiment of the present invention, the control module 144 generates a first sampling period and the sampling period according to a second supplier N, and the data written in the first byte bits j decrementer 141, the number M of the received write I the second decrementer 142, the control module 144 according to the result of the decrement the first and second decrement decrementer 141 142, the first sampling cycle (N + 1) T or a second sampling period NT third write decrementer 143, and generating a sampling pulse according to the result of the decrement third decrementer 143, the data bytes of each frame of the transmission data of the 146 pairs of sampling pulse decoder in the sample, is decoded. [0100] 作为本发明一实施例,可以通过状态机145设置第一采样周期(N+1)T或第二采样周期NT的插值,该状态机145的状态转换图可以为:[0101] 0000 — 0001 — 0010 — 0011 — 0100 — 0101 — 0110 — 0111 — 1000 — 0000......。 [0100] As an embodiment of the present invention may be provided a first sampling period 145 (N + 1) T or interpolation of the second sampling period NT via a state machine, the state machine 145 may be converted to: [0101] 0000 --0001--0010-- 0011 --0100--0101-- 0110 --0111--1000-- 0000 ....... [0102] 例如,采样到起始字节的时间宽度为176T,那么经过除9处理后,得到N=19,M=5, 用二进制表示为N=5,blOOll, M=4,bOlOl。 [0102] For example, the sampling time of the start byte width 176T, 9 then removed therefrom to give N = 19, M = 5, with the binary representation of N = 5, blOOll, M = 4, bOlOl. [0103] 采样起始位时,将采样点设定为5' bOlOOl。 [0103] When the start bit sampling, sampling point is set to 5 'bOlOOl. 其后的数据位采样周期分别为5次5' bl0100,3次5' blOOll。 Subsequent data bit sampling period were 5 times 5 'bl0100,3 times 5' blOOll. 并且,在分布时,尽量采用插入分布的方式,譬如从起始位到第8数据位的采样周期如图7所示。 Further, when the distribution, distribution as far as possible inserted, such as from the start bit to 8-bit data of the sampling period as shown in FIG. [0104] 具体采样过程为:以每个数据字节的下降沿作为采样数据开始,起始位的采样点为(N/2)T,若M=3,通过状态机设置插值,例如,设置第2个采样脉冲与第I个采样脉冲的间隔为(N+1) T,第3个采样脉冲与第2个采样脉冲的间隔为(N+1) T,第4个采样脉冲与第3 个采样脉冲的间隔为(N+1) T,第5个采样脉冲与第4个采样脉冲的间隔为NT,第6个采样脉冲与第5个采样脉冲的间隔为NT,第7个采样脉冲与第6个采样脉冲的间隔为NT,第8个采样脉冲与第7个采样脉冲的间隔为NT,第9个采样脉冲与第8个采样脉冲的间隔为NT。 [0104] DETAILED sampling process is as follows: the falling edge of each byte of data as the sampling data start, start bit sample points (N / 2) T, if M = 3, the interpolation is provided via a state machine, for example, provided the second sampling pulse and the I-th sampling pulse interval of (N + 1) T, the interval of three sampling pulse and the second sampling pulse is (N + 1) T, the fourth sample pulse 3 interval sampling pulse is (N + 1) T, an interval of five sampling pulses and the fourth sampling pulse is NT, the interval of six sampling pulse of the fifth sampling pulse is NT, seventh sampling pulse and sixth sampling pulse interval is NT, the eighth sampling pulse interval of the first sampling pulse 7 is NT, and the ninth sampling pulse interval of the eighth sample pulse is NT. 可以理解地,上述每个采样脉冲间隔的选择可以通过改变状态机的状态转换值的设置而变化设置,例如将第3个采样脉冲与第2个采样脉冲的间隔设置为NT,第8个采样脉冲与第7 个采样脉冲的间隔设置为(N+1)T,而每发出一次采样脉冲,第一递减器、第二递减器和第三递减器应相应地递减数据字节位数j、余数M以及采样周期。 Understandably, each of said sampling pulse selection interval may be varied by changing the set value of the setting state transition of the state machine, for example, the third interval and the second sampling pulse sample pulse is NT, the eighth sample pulse interval and the second sampling pulse for seven (N + 1) T, and each time the sampling pulse is emitted, a first down, a second and a third decrementer decrements accordingly be decremented byte data bits j, remainder M and the sampling period. [0105] 具体递减过程为:[0106] 控制模块根据商N和振荡信号OSC的周期生成初始采样周期(N/2)T,将数据字节位数j (此例中为9)写入第一递减器141,并将该初始采样周期(N/2) T写入第三递减器143,第一递减器141根据振荡信号OSC的周期开始减I操作,此时第三递减器143也在振荡信号OSC的周期控制下进入递减程序,并在递减为O时输出第一个采样脉冲,同时,控制模块144根据商N生成第一采样周期(N+1) T和第二采样周期NT,并将余数M写入第二递减器142,在状态机145的控制下控制模块144将第一采样周期(N+1)T或第二采样周期NT 写入第三递减器143,当状态机145控制第一采样周期(N+1) T写入第三递减器143时,第二递减器142均递减I,而第三递减器143在被写入第一采样周期(N+1)T或第二采样周期NT后进行递减,直到递减为O时输出第二个采样脉冲,同时再次由控制模块144将第一采样周期 [0105] DETAILED down process: [0106] The control module generates an initial sample period (N / 2) T and N according to the period of the oscillation signal OSC supplier of the data byte bits j (in this example 9) first write a decrementer 141, and the initial sample period (N / 2) T third write decrementer 143, decrementer 141 starts a first operation I Save the period of the oscillation signal OSC, are now the third decrementer 143 into the next cycle of the oscillation signal OSC decreasing control program, and outputs a first down sampling pulse is O, simultaneously, the control module 144 (N + 1) T and the second sampling period to generate a first N NT supplier according sampling period, M and the remainder of the second write decrementer 142, the state machine 145 under the control of the control module 144 of the first sampling cycle (N + 1) T or a second sampling period NT third write decrementer 143, when the state machine 145 controls the first sampling cycle (N + 1) T third write decrementer 143, 142 are decremented down the second I, third decrementer 143 is written in the first sampling cycle (N + 1) T or the second sampling period after NT is decremented until the output of the second down sampling pulses is O, while the control module 144 of the first sampling cycle again (N+1 )T或第二采样周期NT写入第三递减器143中,直到第一递减器141递减为零,而每一次在第一采样周期(N+1) T被写入第三递减器143中时,第二递减器142均减1,直到第二递减器142递减为零,如此循环将依次输出j个采样脉冲,完成整个数据字节的采样操作。 (N + 1) T or a second sampling period NT third write decrementer 143, 141 until a first decrementer decrements to zero, while the third is written each time in the first sampling cycle (N + 1) T when the decrementer 143, the second 142 are decremented by 1, until a second decrementer 142 decrements to zero, and so the sampling pulses are sequentially output j, to complete the sampling operation of data bytes. [0107] 若不采用状态机145,也可以先对第三状态机143写入第一采样周期(N+1) T,并判断第二递减器142是否为零,若第二递减器142不为零,则继续向第三递减器143写入第一采样周期(N+1)T,直到第二递减器142递减为零,再将第二采样周期NT写入第三递减器143,直到第一递减器141递减为零。 [0107] If state machine 145, 142 may be first checked for zero third state machine 143 written in the first sampling cycle (N + 1) T, and determines a second descending, a decrementer 142 when the second does not is zero, then continue to write to the third decrementer 143 first sampling period (N + 1) T, until the second decrementer 142 decrements to zero, then the second sampling period NT third write decrementer 143, until The first decrementer 141 decrements to zero. [0108] 当第一递减器141递减为零时,则表示该数据字节采样完成。 [0108] When the first decrementer 141 decrements to zero, it indicates that the complete data byte samples. [0109] 需要说明的是,如果N的二进制最后I位为1,而M古0,那么可以将M减1,而起始位的采样点为[N/2]+l。 [0109] Incidentally, if the final I N bit binary 1, 0 and M old, then M may be decremented by one, and the start bit sampling point [N / 2] + l. 其中[N/2]是指其整数部分。 Where [N / 2] means the integer part. [0110] 本发明实施例通过在帧起始字节低电平位数的时间周期内对振荡信号的振荡周期进行计数,并对计数值进行除法运算,得到商和余数,根据商和余数进行解码,没有积累误差产生,无需通过提升数据传输率降低解码误差,大大提高了解码的准确率,并且实现简单,成本低,稳定性好。 [0110] Example embodiments of the present invention, by counting the oscillation period of the oscillation signal in the low byte of the number of bits of the frame start time period, and the count value of the division is performed to obtain the quotient and remainder, according to the quotient and remainder decoding, there is no accumulation error is generated, by increasing the data transfer rate without lowering the decoding error, greatly improving the accuracy of decoding, and simple, low cost, good stability. [0111] 以上仅为本发明的较佳实施例而已,并不用以限制本发明,凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等,均应包含在本发明的保护范围之内。 [0111] The above description is only preferred embodiments of the present invention but are not intended to limit the present invention, any modifications within the spirit and principle of the present invention, equivalent substitutions and improvements should be included in the present invention. within the scope of protection.

Claims (7)

1.一种传输协议解码方法,其特征在于,所述方法包括下述步骤:生成振荡信号;检测帧起始信号,并在检测到所述帧起始信号时,输出采样控制信号;接收到所述采样控制信号后,在帧起始字节低电平位数的时间周期内对所述振荡信号的振荡周期进行计数,并对所述计数值进行除法运算,输出商和余数;根据商和余数确定采样周期,以生成采样脉冲,并根据所述采样脉冲对传输数据中的数据字节进行解码。 1. A transmission protocol decoding method, characterized in that the method comprises the steps of: generating an oscillation signal; a frame start signal is detected, and upon detection of the frame start signal, the control signal output sampling; received after the sampling control signal, the start byte in the frame digit of the time period of low oscillation period of the oscillation signal count, and the count value of the division operation, the output of the quotient and remainder; the commercially remainder and determine the sampling period, to generate a sampling pulse, and decodes the data byte of the transmission data in accordance with the sampling pulses.
2.如权利要求1所述的方法,其特征在于,所述根据商和余数确定采样周期,以生成采样脉冲,并根据所述采样脉冲对传输数据中的数据字节进行解码的步骤具体为:根据所述商生成第一采样周期和第二采样周期;将数据字节位数写入第一递减器,将所述余数写入第二递减器;根据所述第一递减器和所述第二递减器的递减结果,将所述第一采样周期或所述第二采样周期写入第三递减器;根据所述第三递减器的递减结果生成采样脉冲;根据所述采样脉冲对传输数据中的每一帧中的数据字节采样,进行解码。 2. The method according to claim 1, wherein said quotient and a remainder determined according to the sampling period, to generate a sampling pulse, and the step of decoding the data byte transmission data of the sampling pulses is particularly : the quotient generating a first sampling period and the second period based on sampling; the number of bits written in the first data byte is decreasing, the remainder of the second write decrementer; according to said first and said decrementing decrementer decrements the result of the second, the sampling period of the first or the second sampling period a third write decrementer; generating a sampling pulse according to the result of the decrement of the third decrementer; transmission in accordance with the sampling pulses each frame of data bytes in the data sample is decoded.
3.一种传输协议解码装置,所述装置与驱动单元连接,包括:振荡器,用于生成振荡信号;控制器,用于检测帧起始信号,并在检测到所述帧起始信号时,输出采样控制信号,所述控制器的输入端接收传输数据;除法运算单元,用于在接收到所述采样控制信号后,在帧起始字节低电平位数的时间周期内对所述振荡信号的振荡周期进行计数,并对所述计数值进行除法运算,输出商和余数,所述除法运算单元的控制端与所述控制器的输出端连接,所述除法运算单元的输入端与所述振荡器的输出端连接;解码单元,用于根据所述商和余数确定采样周期,以生成采样脉冲,并根据所述采样脉冲对传输数据中的数据字节进行解码,所述解码单元的第一输入端与所述除法运算单元的第一输出端连接,所述解码单元的第二输入端与所述除法运算单元的第二输出端连 Controller for detecting a frame start signal, and detecting the frame start signal; oscillator for generating an oscillation signal: A transport protocol decoding apparatus, the apparatus is connected with the drive unit, comprising , the output sampling control signal input terminal, the controller receives the transmission data; division means configured to, after receiving the control signal is sampled in the low byte of the number of bits of the frame start time of the period the oscillation period of the oscillating signal are counted, and the count value of the division operation, the output of the quotient and remainder of the division means the control terminal and the output terminal is connected to said controller, said input unit division connected to the output of the oscillator; a decoding unit, for determining a sampling period based on the quotient and remainder to generate a sampling pulse, and decodes the data byte of the transmission data in accordance with said sampling pulse, said decoding a first output terminal of the first input unit and the unit is connected to the division, the second decoding unit output of a second input coupled to said division means connected ,所述解码单元的第三输入端与所述控制器的输入端连接以接收传输数据,所述解码单元的时钟端与所述振荡器的输出端连接,所述解码单元的输出端与所述驱动单元连接。 , A third input terminal of the input decoding unit is connected to the controller to receive the data transmission, the clock output terminal of the decoding unit is connected to the oscillator, the output of the decoding unit of the said drive unit is connected.
4.如权利要求3所述的装置,其特征在于,所述控制器为状态机或时间检测装置。 4. The apparatus according to claim 3, wherein said controller is a state machine, or time detection means.
5.如权利要求3所述的装置,其特征在于,所述除法运算单元包括:第一D触发器、第二D触发器、第三D触发器、第四D触发器、第一或非门、第二或非门、 二进制计数器以及逻辑运算模块;所述第一D触发器的复位端、所述第二D触发器的复位端、所述第三D触发器的复位端、所述第四D触发器的复位端同时为所述除法运算单元的控制端,所述第一D触发器的时钟输入端、所述第二D触发器的时钟输入端为所述除法运算单元的输入端,所述第二D触发器的触发端与所述第一D触发器的正向输出端连接,所述第一或非门的第一输入端与所述第一D触发器的正向输出端连接,所述第一或非门的第二输入端与`所述第二D触发器的正向输出端连接,所述第一或非门的输出端同时与所述第一D触发器的触发端、所述第三D 触发器的时钟输入端、所述第四D触发器的时钟输入端连接 5. The apparatus according to claim 3, wherein the division unit comprises: a first D flip-flop, a second D flip-flop, a third D flip-flop, a fourth D flip-flop, the first NOR gate, the second NOR gate, a binary counter and a logic operation module; reset terminal reset terminal of said first D flip-flop, said second D flip-flop, the third D flip-flop reset terminal, said a reset terminal of the fourth D flip-flop of the divider while said control arithmetic unit, a clock input of the first D flip-flop, a clock input terminal of the second flip-flop to the D input of the division means end, the second end of the D flip-flop is connected to the positive output terminal of said first D flip-flop, said first NOR gate a first input terminal of said first D flip-forward an output terminal connected to a second input of the first NOR gate is connected to the positive output terminal of the second `D flip-flop is connected to an output terminal of said first NOR gate while said first D flip-flop clock input terminal of the trigger device, the third D flip-flop, a clock input terminal of the fourth D flip flop 所述第四D触发器的触发端与所述第三D触发器的正向输出端连接,所述第二或非门的第一输入端与所述第三D触发器的正向输出端连接,所述第二或非门的第二输入端与所述第四D触发器的正向输出端连接,所述第二或非门的输出端同时与所述第三D触发器的触发端和所述二进制计数器的时钟输入端连接,所述二进制计数器的输出端为所述除法运算单元的第一输出端,所述第一D 触发器的正向输出端、所述第二D触发器的正向输出端、所述第三D触发器的正向输出端、 所述第四D触发器的正向输出端依次于所述逻辑运算模块的第一输入端、第二输入端、第三输入端、第四输入端连接,所述逻辑运算模块的输出端为所述除法运算单元的第二输出端。 Trigger terminal of the fourth D flip-flop and the positive output terminal of said third D-flip-flop is connected to the positive output of the first input terminal of said second NOR gate and the third D flip-flop connected to a second input of the second NOR gate is connected to the positive output terminal of the fourth D flip-flop, the second output terminal of NOR gate triggered simultaneously with the third D-flipflop and a clock input terminal connected to said binary counter, the binary counter output is the output of a first division unit, the positive output of the first D flip-flop, said second D flip-flop the positive output terminal of the device, the positive output terminal of the third D-flip-flop, the fourth D flip-flop to the positive output terminal of the logic sequentially first input terminal of the operational module, a second input terminal, a third input, a fourth input terminal, an output terminal of the logic operation module to the second division output terminal means.
6.如权利要求3所述的装置,其特征在于,所述解码单元包括:第一递减器、第二递减器、第三递减器、控制模块、状态机以及解码器;所述控制模块的第一输入端为所述解码单元的第一输入端,所述控制模块的第二输入端为所述解码单元的第二输入端,所述控制模块的第一输出端与所述第一递减器的输入端连接,所述控制模块的第二输出端与所述第二递减器的输入端连接,所述控制模块的所述第三输出端与所述第三递减器的输入端连接,所述状态机的输出端与所述控制模块的第三输入端连接,所述控制模块的时钟端为所述译码单元的时钟端,所述控制模块的输出端与所述解码器的第一输入端连接,所述解码器的第二输入端为所述解码单元的第三输入端, 所述解码器的输出端为所述解码单元的输出端。 6. The apparatus according to claim 3, wherein said decoding unit comprises: a first down, a decrementer second, third down, a control module, a state machine and a decoder; of the control module the first input is a first input of the decoding unit, a second input of the control module to said decoding unit, a second input, a first output terminal of the control module with the first decrement an input terminal is connected, the control module of the second output and the second input of decrementer connected to said control module, said third output terminal connected to the third input of decrementer, the first output of the state machine with the control module connected to a third input terminal, a clock terminal of the control module to the clock terminal of the decoding unit, the output of the control module of the decoder an input terminal, a second input terminal of the decoder to decode said third input terminal means, said output of said decoder for decoding the output of the unit.
7.一种传输协议解码芯片,其`特征在于,所述设备包括如权利要求3至6任一项所述的传输协议解码装置。 A transport protocol decoder chip, which `characterized in that said apparatus comprises a transmission protocol decoding apparatus as claimed in any one of claims 3 to 6.
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