CN109167736B - High-uniformity data packet sending method and device - Google Patents
High-uniformity data packet sending method and device Download PDFInfo
- Publication number
- CN109167736B CN109167736B CN201810817261.0A CN201810817261A CN109167736B CN 109167736 B CN109167736 B CN 109167736B CN 201810817261 A CN201810817261 A CN 201810817261A CN 109167736 B CN109167736 B CN 109167736B
- Authority
- CN
- China
- Prior art keywords
- packet
- sending
- data packet
- time
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/50—Queue scheduling
- H04L47/62—Queue scheduling characterised by scheduling criteria
- H04L47/625—Queue scheduling characterised by scheduling criteria for service slots or service orders
- H04L47/628—Queue scheduling characterised by scheduling criteria for service slots or service orders based on packet size, e.g. shortest packet first
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/0078—Avoidance of errors by organising the transmitted data in a format specifically designed to deal with errors, e.g. location
- H04L1/0083—Formatting with frames or packets; Protocol or part of protocol for error control
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/10—Flow control; Congestion control
- H04L47/22—Traffic shaping
- H04L47/225—Determination of shaping rate, e.g. using a moving window
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/10—Flow control; Congestion control
- H04L47/30—Flow control; Congestion control in combination with information about buffer occupancy at either end or at transit nodes
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/10—Flow control; Congestion control
- H04L47/36—Flow control; Congestion control by determining packet size, e.g. maximum transfer unit [MTU]
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L5/00—Arrangements affording multiple use of the transmission path
- H04L5/003—Arrangements for allocating sub-channels of the transmission path
- H04L5/0078—Timing of allocation
- H04L5/0082—Timing of allocation at predetermined intervals
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Computer Networks & Wireless Communication (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
The invention discloses a high-uniformity data packet issuing method and a high-uniformity data packet issuing device, which comprise the following steps of: s1: reading a package sending parameter input by a user; s2: generating a plurality of data packets; s3: calculating the expected sending time of each data packet in the S2 according to the packet sending rule; s4: transmitting the data packet in the S2 and the estimated transmission time calculated in the S3 to a buffer area; s5: detecting whether a data packet exists in a cache region; s6: after detecting the data packet, reading the data packet and the predicted sending time Ts; s7: reading a current real-time clock value Tr; s8: comparing the predicted sending time Ts with a real-time clock value Tr, and sending a data packet when Ts is less than or equal to Tr; the data packet is sent at fixed time according to the predefined sending time, so that the packet sending uniformity and accuracy are greatly improved, and data with larger packet frequency can be sent by using a high-precision clock; compared with an import instrument, the method can also simulate to send a service data packet and increase service processes, such as frame counting and the like.
Description
Technical Field
The invention relates to the technical field of network communication, in particular to a high-uniformity data packet sending method and device.
Background
Currently, in network testing, sometimes it is necessary to send data packets, for example: flow test or simulation service data are required to be sent according to a specified packet frequency; but it is difficult to precisely control the transmission frequency due to technical limitations.
Many test software using network card to send out package can generate data package and transmit to the network card, the network card will send out all at once, then wait for the next round.
The special packet sending hardware such as the test instrument can only be approximately uniform, and the packet sending number of one second is satisfied, when the packet frequency is an integer, that is, when the packet frequency is divided by 1000000, for example: when the packet frequency is 2000 frames/second, then 500 microseconds sends a packet on average, the hardware can be made uniform, if: when the packet frequency is 3000 frames/second, it is 333 microseconds one on average, because the accumulated error occurs due to incomplete division.
An effective solution to the problems in the related art has not been proposed yet.
Disclosure of Invention
In view of the above technical problems in the related art, the present invention provides a method and an apparatus for packet distribution with high uniformity.
The technical scheme of the invention is realized as follows:
a high-uniformity data packet sending method comprises the following steps:
s1: reading a packet sending parameter input by a user, wherein the packet sending parameter at least comprises a packet frequency, a protocol and a packet sending quantity;
s2: generating a plurality of data packets;
s3: calculating the expected sending time of each data packet in the S2 according to a packet sending rule, wherein the packet sending rule comprises that the number of the required packets is equal to the packet frequency value within a period of one second, and the sending time interval between each two adjacent data packets is equal;
s4: transmitting the data packet in the S2 and the estimated transmission time calculated in the S3 to a buffer area;
s5: detecting whether a data packet exists in a cache region;
s6: after detecting the data packet, reading the data packet and the predicted sending time Ts;
s7: reading a current real-time clock value Tr;
s8: and comparing the expected sending time Ts with the real-time clock value Tr, and sending the data packet when the Ts is less than or equal to the Tr.
Further, the method also includes the steps of accumulating the number of the data packets sent to the buffer, comparing the number of the data packets sent to the buffer with the number of the data packets sent in S1, and returning to step S2 when the number of the data packets sent to the buffer is smaller than the number of the data packets sent in S1; when the number of packets sent to the buffer is greater than the number of packets sent in S1, the sending of packets is finished.
Further, in step S3, in one of the periods, the initial time value of the period is taken as the expected transmission time of the first packet in the period.
Further, in step S5, it is detected whether there is a packet in the buffer, and when no packet is detected, the process returns to step S5 to repeat the detection.
Further, in step S8, comparing the expected transmission time Ts with the real-time clock value Tr, and returning to step S7 when Ts > Tr; when Ts is not more than Tr, the packet is transmitted and the process returns to step S5.
A high uniformity packet forwarding device, comprising:
the upper computer is used for reading the packet sending parameters input by a user, wherein the packet sending parameters at least comprise packet frequency, protocols and packet sending quantity; generating a plurality of data packets; calculating the expected sending time of each data packet according to a packet sending rule, wherein the packet sending rule comprises that the number of the required packets is equal to a packet frequency value within a period of one second, and the sending time interval between each two adjacent data packets is equal; sending the data packet and the expected sending time to a board card cache area in an upper computer;
the FPGA chip is used for detecting whether a data packet exists in the board card cache region or not; after detecting the data packet, reading the data packet and the predicted sending time Ts; reading a current real-time clock value Tr; and comparing the expected sending time Ts with the real-time clock value Tr, and sending the data packet when the Ts is less than or equal to the Tr.
Further, the upper computer is further configured to accumulate the number of the data packets sent to the cache area, compare the number of the data packets sent to the cache area with the number of the data packets sent to the cache area, and continue to generate data packets when the number of the data packets sent to the board card cache area is smaller than the number of the data packets sent to the cache area; and when the number of the data packets sent to the buffer area is larger than the packet sending number, ending the packet sending.
Furthermore, the upper computer is further configured to take the initial time value of the period in one period as the expected sending time of the first data packet of the period.
Further, the FPGA chip is further configured to detect whether there is a data packet in the buffer, and return to re-detection when no data packet is detected.
Further, the FPGA chip is also used for comparing the expected sending time Ts with a real-time clock value Tr, and when Ts is larger than Tr, the real-time clock value Tr is read again; and when Ts is less than or equal to Tr, returning to detect whether the data packet exists in the buffer area or not after the data packet is sent.
The invention has the beneficial effects that: the data packet is sent at fixed time according to the predefined sending time, so that the packet sending uniformity and accuracy are greatly improved; by utilizing a high-precision clock, data with larger packet frequency can be sent; compared with an import instrument, the method can also simulate to send a service data packet and increase service processes, such as frame counting and the like.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
FIG. 1 is a flow diagram of a prior art hardware packet sending;
FIG. 2 is a graph illustrating cumulative error in packet transmission according to the present invention;
FIG. 3 is a schematic diagram of memory allocation for packet transmission according to the method and apparatus for packet transmission with high uniformity;
fig. 4 is a flow chart of a method and apparatus for packet distribution with high uniformity according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments that can be derived by one of ordinary skill in the art from the embodiments given herein are intended to be within the scope of the present invention.
As shown in fig. 1-4, a method for sending packets with high uniformity according to an embodiment of the present invention includes the following steps:
s1: reading a packet sending parameter input by a user, wherein the packet sending parameter at least comprises a packet frequency, a protocol and a packet sending quantity;
s2: generating a plurality of data packets;
s3: calculating the expected sending time of each data packet in the S2 according to a packet sending rule, wherein the packet sending rule comprises that the number of the required packets is equal to the packet frequency value within a period of one second, and the sending time interval between each two adjacent data packets is equal;
s4: transmitting the data packet in the S2 and the estimated transmission time calculated in the S3 to a buffer area;
s5: detecting whether a data packet exists in a cache region;
s6: after detecting the data packet, reading the data packet and the predicted sending time Ts;
s7: reading a current real-time clock value Tr;
s8: and comparing the expected sending time Ts with the real-time clock value Tr, and sending the data packet when the Ts is less than or equal to the Tr.
In this embodiment, the method further includes accumulating the number of packets sent to the buffer, comparing the number of packets sent to the buffer with the number of packets sent in S1, and returning to step S2 when the number of packets sent to the buffer is smaller than the number of packets sent in S1; when the number of packets sent to the buffer is greater than the number of packets sent in S1, the sending of packets is finished.
In this embodiment, in step S3, in one of the periods, the initial time value of the period is taken as the expected transmission time of the first packet of the period.
In this embodiment, in step S5, it is detected whether there is a packet in the buffer, and when no packet is detected, the process returns to step S5 to repeat the detection.
In this embodiment, in step S8, comparing the expected transmission time Ts with the real-time clock value Tr, and returning to step S7 when Ts > Tr; when Ts is not more than Tr, the packet is transmitted and the process returns to step S5.
A high uniformity packet forwarding device, comprising:
the upper computer is used for reading the packet sending parameters input by a user, wherein the packet sending parameters at least comprise packet frequency, protocols and packet sending quantity; generating a plurality of data packets; calculating the expected sending time of each data packet according to a packet sending rule, wherein the packet sending rule comprises that the number of the required packets is equal to a packet frequency value within a period of one second, and the sending time interval between each two adjacent data packets is equal; sending the data packet and the expected sending time to a board card cache area in an upper computer;
the FPGA chip is used for detecting whether a data packet exists in the board card cache region or not; after detecting the data packet, reading the data packet and the predicted sending time Ts; reading a current real-time clock value Tr; and comparing the expected sending time Ts with a real-time clock value Tr, and sending a data packet when Ts is less than or equal to Tr.
In this embodiment, the upper computer is further configured to accumulate the number of the data packets sent to the cache area, compare the number of the data packets sent to the cache area with the number of the data packets sent to the cache area, and continue to generate the data packets when the number of the data packets sent to the board card cache area is smaller than the number of the data packets sent to the cache area; and when the number of the data packets sent to the buffer area is larger than the packet sending number, ending the packet sending.
In this embodiment, the upper computer is further configured to take the initial time value of the period in one period as the expected sending time of the first data packet of the period.
In this embodiment, the FPGA chip is further configured to detect whether there is a data packet in the buffer, and return to re-detection when no data packet is detected.
In this embodiment, the FPGA chip is further configured to compare the expected sending time Ts with the real-time clock value Tr, and when Ts > Tr, re-read the real-time clock value Tr; and when Ts is less than or equal to Tr, returning to detect whether a data packet exists in the buffer area or not after the data packet is sent.
In the process of reading the real-time clock value in the step S7, the read and write of the real-time clock value are realized at high speed by using the dual-port RAM of the FPGA itself; the clock circuit analyzes and acquires accurate year, month, day, time, minute and second values from an IRIG-B code format, and millisecond, microsecond and nanosecond values below the second are provided with a pulse source through a high-precision oscillation circuit to realize counting, wherein the highest resolution is 100 nanoseconds; updating the real-time clock value every other time, writing new value
As shown in fig. 1, a flow chart of hardware packet sending is generally implemented, and a counter is decremented to 0 to generate an interrupt for data packet sending. Mathematically, 3 packets are sent every second, then the interval between two adjacent packets is 0.3333333333 seconds; in the circuit, the counting is completed by a counter, the frequency of a crystal oscillator is 1MHz, and the duration of each counting pulse is 0.000001 second, namely 1 microsecond.
The first packet starts to be sent, and the counter value is set to 333333, and is decremented every 1 microsecond until 0 is reduced, triggering the interruption of sending the second packet, and resetting the counter value to 333333. The data packet with uniform packet frequency is obtained by the circular operation.
Mathematically, the packet interval is 0.333333333. It is not possible to eliminate this error physically on the circuit because of technical limitations. When a receiver receives the data, the number of the packets is counted according to one second, digital jumping occurs, and some packets are more than one second, some packets are less than one second, and even inaccurate;
because the packet frequency value is specified by the user, in the method of the invention, in a period, the interval time of adjacent packets is 1 ÷ packet frequency value, and the unit is second, so that the interval time can be hardly divided; if the division is incomplete, an integer needs to be taken on a circuit, errors inevitably occur, and therefore errors are accumulated; the method of the invention has the principle that the error is controlled within 1 second when the incomplete division is faced. Within the packet frequency number, an integer is taken, and when the packet frequency number is reached, the sending time must be adjusted to be aligned in seconds.
In this embodiment, assuming that the current is 9:00:00, the sending packet frequency is taken to be 3 frames/second, and it is expected that the data packet is sent from the next second, and table 1 is a time comparison table of the method of the present invention and the existing packet sending method:
TABLE 1
The method of the invention is illustrated in connection with FIG. 2: frame 1 is aligned in seconds, frame 2 has errors, and frame 3 has errors; frame 4 is aligned seconds, frame 5 is in error, and frame 6 is in error. By analogy, errors always do not accumulate within one second.
When the receiving party receives the data packets, the number is stable and does not jump when the packet number is counted according to one second, because the error is in fixed distribution, the number is counted from any place, and the data packet number in one second is fixed.
In addition, the method does not use a counter, does not have the operation of loading the initial value of the counter, and does not have the operation of subtracting one and interrupting triggering, so the running speed of the FPGA program is higher and more stable.
In addition, if Ts is set to 0, any Tr is greater than 0, and is sent immediately, which is the network card packet sending mode; if the upper computer needs to send immediately, only the expected sending time Ts needs to be set to 0.
If the traffic packet is to send fixed content, a repeated traffic packet can be generated without an upper computer; the transmission is only carried out once, then the subsequent expected sending time of the flow packet is automatically modified by an FPGA program, and the flow packet with high uniformity can be sent as long as the packet sending rule is met.
Therefore, by means of the technical scheme, the data packets are sent at fixed time according to the predefined sending time, so that the packet sending uniformity and accuracy are greatly improved; by utilizing a high-precision clock, data with larger packet frequency can be sent; compared with an import instrument, the method can also simulate to send a service data packet and increase service processes, such as frame counting and the like.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (2)
1. A method for sending a data packet with high uniformity is characterized by comprising the following steps:
s1: reading a packet sending parameter input by a user, wherein the packet sending parameter at least comprises a packet frequency, a protocol and a packet sending quantity;
s2: generating a plurality of data packets;
s3: calculating the expected sending time of each data packet in the S2 according to a packet sending rule, wherein the packet sending rule comprises that the number of the required packets is equal to the packet frequency value within a period of one second, and the sending time interval between each two adjacent data packets is equal;
s4: transmitting the data packet in the S2 and the estimated transmission time calculated in the S3 to a buffer area;
s5: detecting whether a data packet exists in a cache region;
s6: after detecting the data packet, reading the data packet and the predicted sending time Ts;
s7: reading a current real-time clock value Tr;
s8: comparing the predicted sending time Ts with a real-time clock value Tr, and sending a data packet when Ts is less than or equal to Tr;
accumulating the number of packets transmitted to the buffer, comparing the number of packets transmitted to the buffer with the number of packets transmitted in S1, and returning to step S2 when the number of packets transmitted to the buffer is less than the number of packets transmitted in S1; when the number of the data packets sent to the buffer area is larger than the packet sending number in the S1, ending the packet sending;
in step S3, in one of the periods, the initial time value of the period is taken as the expected sending time of the first data packet of the period;
in step S5, detecting whether there is a packet in the buffer, and returning to step S5 to repeat the detection when no packet is detected;
in step S8, comparing the expected sending time Ts with the real-time clock value Tr, and returning to step S7 when Ts is more than Tr; when Ts is less than or equal to Tr, returning to the step S5 after the data packet is sent;
the reading of the current real-time clock value Tr in step S7 is specifically: the reading and writing of a real-time clock value are realized by utilizing a dual-port RAM of the FPGA; the clock circuit analyzes and obtains accurate year, month, day, hour, minute and second values from an IRIG-B code format, and millisecond, microsecond and nanosecond values below the second are provided for a pulse source through a high-precision oscillation circuit to realize counting.
2. A high uniformity packet forwarding device, comprising:
the upper computer is used for reading the packet sending parameters input by a user, wherein the packet sending parameters at least comprise packet frequency, protocols and packet sending quantity; generating a plurality of data packets; calculating the expected sending time of each data packet according to a packet sending rule, wherein the packet sending rule comprises that the number of the required packets is equal to a packet frequency value within a period of one second, and the sending time interval between each two adjacent data packets is equal; sending the data packet and the expected sending time to a board card cache area in an upper computer;
the FPGA chip is used for detecting whether a data packet exists in the board card cache region or not; after detecting the data packet, reading the data packet and the predicted sending time Ts; reading a current real-time clock value Tr; comparing the predicted sending time Ts with a real-time clock value Tr, and sending a data packet when Ts is less than or equal to Tr;
the upper computer is also used for accumulating the number of the data packets sent to the cache area, comparing the number of the data packets sent to the cache area with the number of the data packets sent to the cache area, and continuously generating the data packets when the number of the data packets sent to the board card cache area is smaller than the number of the data packets sent to the cache area; when the number of the data packets sent to the cache region is larger than the packet sending number, ending packet sending;
the upper computer is also used for taking the initial time value of the period in one period as the expected sending time of the first data packet of the period;
the FPGA chip is also used for detecting whether a data packet exists in the cache region or not, and returning to re-detection when the data packet is not detected;
the FPGA chip is also used for comparing the predicted sending time Ts with a real-time clock value Tr, and when Ts is larger than Tr, the real-time clock value Tr is read again; when Ts is less than or equal to Tr, returning to detect whether a data packet exists in the buffer area or not after the data packet is sent;
the reading of the current real-time clock value Tr specifically includes: the reading and writing of a real-time clock value are realized by utilizing a dual-port RAM of the FPGA; the clock circuit analyzes and acquires accurate year, month, day, hour, minute and second values from an IRIG-B code format, and millisecond, microsecond and nanosecond values below the second value are provided for a pulse source through a high-precision oscillation circuit to realize counting.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810817261.0A CN109167736B (en) | 2018-07-24 | 2018-07-24 | High-uniformity data packet sending method and device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810817261.0A CN109167736B (en) | 2018-07-24 | 2018-07-24 | High-uniformity data packet sending method and device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109167736A CN109167736A (en) | 2019-01-08 |
| CN109167736B true CN109167736B (en) | 2022-05-17 |
Family
ID=64898264
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810817261.0A Active CN109167736B (en) | 2018-07-24 | 2018-07-24 | High-uniformity data packet sending method and device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109167736B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109766282B (en) * | 2019-01-31 | 2020-09-25 | Oppo广东移动通信有限公司 | Stuck detection method, stuck detection device and terminal equipment |
| CN115665044A (en) * | 2022-10-19 | 2023-01-31 | 中国人民解放军63921部队 | High-uniformity ten-gigabit flow generation system, method, equipment and medium |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101141320A (en) * | 2007-08-07 | 2008-03-12 | 中兴通讯股份有限公司 | Method and device for generating network flux |
| CN103560928A (en) * | 2013-10-22 | 2014-02-05 | 东软集团股份有限公司 | Method and system for testing forwarding performance of network equipment |
| CN105207954A (en) * | 2015-08-25 | 2015-12-30 | 东软集团股份有限公司 | Transmitting data packet and throughput test method and device |
| CN106209499A (en) * | 2016-06-28 | 2016-12-07 | 醴陵恒茂电子科技有限公司 | A kind of Ethernet of stablizing is given out a contract for a project the method and apparatus of tester flow |
| CN106487606A (en) * | 2015-08-28 | 2017-03-08 | 阿里巴巴集团控股有限公司 | A kind of dispatching method for network tester and system |
-
2018
- 2018-07-24 CN CN201810817261.0A patent/CN109167736B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101141320A (en) * | 2007-08-07 | 2008-03-12 | 中兴通讯股份有限公司 | Method and device for generating network flux |
| CN103560928A (en) * | 2013-10-22 | 2014-02-05 | 东软集团股份有限公司 | Method and system for testing forwarding performance of network equipment |
| CN105207954A (en) * | 2015-08-25 | 2015-12-30 | 东软集团股份有限公司 | Transmitting data packet and throughput test method and device |
| CN106487606A (en) * | 2015-08-28 | 2017-03-08 | 阿里巴巴集团控股有限公司 | A kind of dispatching method for network tester and system |
| CN106209499A (en) * | 2016-06-28 | 2016-12-07 | 醴陵恒茂电子科技有限公司 | A kind of Ethernet of stablizing is given out a contract for a project the method and apparatus of tester flow |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109167736A (en) | 2019-01-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105187148B (en) | A kind of network clock synchronization system and method based on ARM | |
| CN109669899B (en) | Method for adaptively adjusting serial port communication baud rate and serial port device | |
| EP1961186B1 (en) | Using travel-time as means for improving the accuracy of simple network time protocol | |
| CN109167736B (en) | High-uniformity data packet sending method and device | |
| CN104461972B (en) | A kind of method and apparatus of data signal samples | |
| CN114285515B (en) | Method and device for realizing arbitrary TSN time window period | |
| CN101951300B (en) | Method for realizing accurate time tick of Ethernet | |
| CN1965270B (en) | Measuring clock jitter | |
| JP5936716B2 (en) | Signal processing device | |
| CN109283833A (en) | A kind of time statistical system and method | |
| CN112395231A (en) | Method and device for calculating data delay time among multiple processors | |
| CN112822226B (en) | Data transmission method and device, electronic equipment and machine-readable storage medium | |
| US10784976B2 (en) | Nanosecond accuracy of timestamping by leveraging alignment marker and method for producing the same | |
| CN113271168B (en) | Power distribution network clock synchronization implementation method based on satellite common view | |
| US11146273B2 (en) | Electronic device and electronic product | |
| CN113515165A (en) | Trigger control method and device | |
| CN102855172B (en) | Method for recording network card receiving time at high precision | |
| CN102413017A (en) | time delay performance monitoring method and device | |
| US6801505B1 (en) | Method of using computer equipment to send a time-stamped frame | |
| CN113259081B (en) | Cross-time domain data synchronization system and method | |
| US20240267196A1 (en) | Methods, systems and computer readable media for generating dynamic time error | |
| CN114070762B (en) | Network monitoring probe assembly, synchronization method and data acquisition and analysis device | |
| KR100218467B1 (en) | Automatic dial signal recognition apparatus for telephone | |
| CN117908630A (en) | High-precision time service system and method based on PCIE board card | |
| Peuhkuri et al. | Clock synchronisation in industry-standard computer hardware |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |