CN101764669A - CRC code check method in data receiving process - Google Patents
CRC code check method in data receiving process Download PDFInfo
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- CN101764669A CN101764669A CN200810237265A CN200810237265A CN101764669A CN 101764669 A CN101764669 A CN 101764669A CN 200810237265 A CN200810237265 A CN 200810237265A CN 200810237265 A CN200810237265 A CN 200810237265A CN 101764669 A CN101764669 A CN 101764669A
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Abstract
The invention relates to the URAT asynchronous communication field, in particular to a CRC code check method in data receiving process. The technical proposal of the invention includes the steps of receiving data byte by byte from the initial byte of the information frame after starting to receive information frame, and calculating CRC codes, storing the byte data into an FIFO module, and temporarily storing intermediate value of the CRC codes obtained by calculating into a CRC code calculator , extracting the CRC codes from the CRC code calculator and checking whether the CRC codes are correct or not after finishing receiving the information frame. The invention applies the method of circularly receiving the byte of the information frame so as to automatically calculate CRC checking codes while receiving information frame, and provides status bit to judge whether the CRC is correct or not after finishing receiving the information frame, thereby omitting the process of calculating CRC codes after finishing receiving frame data by a CPU, therefore, the speed to confirm whether the received data is correct or not is improved, thereby significantly improving the receiving efficiency.
Description
Technical field
The present invention relates to URAT asynchronous communication field, the CRC code check method in particularly a kind of DRP data reception process.
Background technology
The common control chip of universal asynchronous communication has 16C450,16C550,16C750 etc.Interfaces such as 3 bit address buses, 8 bit address buses, read-write control bus can realize that baud rate setting, position of rest number are provided with, the setting of data bit number, have the various functions that report an error simultaneously.Universal asynchronous communication control chip traffic rate per second up to the number megabit, can be realized high-speed communication.
Existing asynchronous communication is applied in the multi-computer communication network of RS485 interface, when to the verification of reception The data CRC sign indicating number (cyclic redundancy check (CRC) code), needs to calculate the CRC sign indicating number after finishing receiving, and has judged whether error of transmission.Expend time in owing to calculate the process need of CRC sign indicating number, particularly when information frame is than long and high-speed communication, this consuming time more obvious, cause the receiving efficiency of data to be had a strong impact on.
Summary of the invention
The present invention has overcome above-mentioned shortcoming, and the CRC in the DRP data reception process that a kind of control procedure is simple, efficient is high is provided code check method.
The present invention solves the technical scheme that its technical problem takes: the CRC code check method in a kind of DRP data reception process comprises the steps:
After receiving information frame and beginning, begin byte-by-byte reception data from the start byte of information frame, and calculate the CRC sign indicating number respectively;
The storage that byte-by-byte calculating is obtained arrives fifo module, and the CRC sign indicating number stores in the CRC calculator;
After information frame receives, from the CRC calculator, extract the CRC sign indicating number, carry out the inspection of correctness.
Described byte-by-byte reception data, and calculate in the step of CRC sign indicating number, each byte is to receive data by turn, and the calculating CRC sign indicating number that distributes.
Described receive the step of data by turn after, also comprise judging whether the bit data receive effective, effective bit data is calculated the CRC sign indicating number.
After the step of byte-by-byte reception data, also comprise, receive parity check bit, and described parity check bit is write fifo module.
Begin at start byte also to comprise before the step of byte-by-byte reception data, the CRC sign indicating number is carried out initialized step from information frame.
The present invention receives by the circulation to byte and information frame, make when receiving information frame, automatically calculate the CRC check sign indicating number, when receiving, information frame provides the whether correct mode bit of CRC, saved CPU calculates the CRC sign indicating number again after receiving frame data process, make confirm to receive whether correct speeding up of data, thereby improved receiving efficiency greatly.
Description of drawings
Fig. 1 is the applied receiver module block diagram of the present invention;
Fig. 2 is a control flow chart of the present invention.
Embodiment
The present invention can be applicable in as shown in fig. 1 the receiver module, described receiver module is made of serial received control module and 9 bit data storage FIFO (first in first out) module, the serial received control module converts serial data to parallel data, calculate the CRC sign indicating number simultaneously, the byte that receives is deposited in the described fifo module.
Wherein, the function declaration of each signal end is as follows:
RESET: reset;
SIN: serial input;
16XCLK: 16 times of clocks of baud rate;
STAcrc:CRC sign indicating number state;
Wrf: the serial received control module is write; The FIFO control signal;
The Dr:9 bit data bus, the 9th bit parity check position;
RDf:CPU reads the FIFO control line;
The DA:9 bit data bus, the 9th bit parity check position;
Based on said structure, carry out detailed process that Frame receives as shown in Figure 2.
Step 207,208 receives parity check bit and position of rest respectively.
From above-mentioned control procedure as can be known, receive by circulation byte and information frame, make when receiving information frame, automatically calculate the CRC check sign indicating number, when receiving, information frame provides the whether correct mode bit of CRC, saved CPU calculates the CRC sign indicating number again after receiving frame data process, made and confirm to receive whether correct speeding up of data, thereby improved receiving efficiency greatly.In addition, adopt 9 bit data bus between CPU and the asynchronous communication controller, the 9th promptly is to send, receive the data parity check position, improves the reliability of data and CPU parallel transmission.
More than the CRC code check method in the DRP data reception process provided by the present invention is described in detail, used specific case herein principle of the present invention and execution mode are set forth, the explanation of above embodiment just is used for helping to understand method of the present invention and core concept thereof; Simultaneously, for one of ordinary skill in the art, according to thought of the present invention, the part that all can change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention.
Claims (5)
1. the CRC code check method in the DRP data reception process is characterized in that: comprise the steps:
After receiving information frame and beginning, begin byte-by-byte reception data from the start byte of information frame, and calculate the CRC sign indicating number respectively;
The byte-by-byte information stores that receives to fifo module, is calculated the CRC sign indicating number that obtains and is temporarily stored in the CRC sign indicating number calculator;
After information frame receives, from CRC sign indicating number calculator, extract the CRC sign indicating number, carry out the inspection of correctness.
2. the CRC code check method in the DRP data reception process according to claim 1 is characterized in that: described byte-by-byte reception data, and calculate in the step of CRC sign indicating number, each byte is to receive data by turn, and the calculating CRC sign indicating number that distributes.
3. the CRC code check method in the DRP data reception process according to claim 2 is characterized in that: described receive the step of data by turn after, also comprise judging whether the bit data receive effective, effective bit data is calculated the CRC sign indicating number.
4. according to the CRC code check method in claim 1 or the 2 or 3 described DRP data reception processes, it is characterized in that: after the step of byte-by-byte reception data, also comprise, receive parity check bit, and described parity check bit is write fifo module.
5. according to the CRC code check method in claim 1 or the 2 or 3 described DRP data reception processes, it is characterized in that: begin at start byte also to comprise before the step of byte-by-byte reception data, the CRC sign indicating number is carried out initialized step from information frame.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810237265A CN101764669A (en) | 2008-12-21 | 2008-12-21 | CRC code check method in data receiving process |
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| Application Number | Priority Date | Filing Date | Title |
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| CN200810237265A CN101764669A (en) | 2008-12-21 | 2008-12-21 | CRC code check method in data receiving process |
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| CN101764669A true CN101764669A (en) | 2010-06-30 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102055555A (en) * | 2010-12-17 | 2011-05-11 | 天津曙光计算机产业有限公司 | Method for filling and checking data frames of 10 Gigabit Ethernet based on FPGA |
| CN102567276A (en) * | 2011-12-19 | 2012-07-11 | 华为技术有限公司 | Data transmission method based on multiple channels, related nodes and system |
| CN103326820A (en) * | 2013-05-28 | 2013-09-25 | 中国电子科技集团公司第十研究所 | Order code on-line binding method |
| CN103546240A (en) * | 2013-09-24 | 2014-01-29 | 许继集团有限公司 | Ethernet CRC (cyclic redundancy check) checking method |
| CN104378174A (en) * | 2014-10-31 | 2015-02-25 | 苏州德鲁森自动化系统有限公司 | Communication data package check method based on grinding machine system |
-
2008
- 2008-12-21 CN CN200810237265A patent/CN101764669A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102055555A (en) * | 2010-12-17 | 2011-05-11 | 天津曙光计算机产业有限公司 | Method for filling and checking data frames of 10 Gigabit Ethernet based on FPGA |
| CN102055555B (en) * | 2010-12-17 | 2013-07-31 | 曙光信息产业股份有限公司 | Method for filling and checking data frames of 10 Gigabit Ethernet based on FPGA |
| CN102567276A (en) * | 2011-12-19 | 2012-07-11 | 华为技术有限公司 | Data transmission method based on multiple channels, related nodes and system |
| WO2013091536A1 (en) * | 2011-12-19 | 2013-06-27 | 华为技术有限公司 | Data transmission method, relevant node and system based on multi-channel |
| CN102567276B (en) * | 2011-12-19 | 2014-03-12 | 华为技术有限公司 | Data transmission method based on multiple channels, related nodes and system |
| CN103326820A (en) * | 2013-05-28 | 2013-09-25 | 中国电子科技集团公司第十研究所 | Order code on-line binding method |
| CN103326820B (en) * | 2013-05-28 | 2016-02-24 | 中国电子科技集团公司第十研究所 | The online method for stitching of command code |
| CN103546240A (en) * | 2013-09-24 | 2014-01-29 | 许继集团有限公司 | Ethernet CRC (cyclic redundancy check) checking method |
| CN104378174A (en) * | 2014-10-31 | 2015-02-25 | 苏州德鲁森自动化系统有限公司 | Communication data package check method based on grinding machine system |
| CN104378174B (en) * | 2014-10-31 | 2020-08-11 | 台州宝诚科技服务有限公司 | Communication data packet checking method based on grinder system |
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Application publication date: 20100630 |