CN102055555B - Method for filling and checking data frames of 10 Gigabit Ethernet based on FPGA - Google Patents
Method for filling and checking data frames of 10 Gigabit Ethernet based on FPGA Download PDFInfo
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- CN102055555B CN102055555B CN 201010598071 CN201010598071A CN102055555B CN 102055555 B CN102055555 B CN 102055555B CN 201010598071 CN201010598071 CN 201010598071 CN 201010598071 A CN201010598071 A CN 201010598071A CN 102055555 B CN102055555 B CN 102055555B
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Abstract
The invention discloses a method for filling and checking data frames of 10 Gigabit Ethernet based on a field programmable gate array (FPGA). The method comprises the following steps of: filling when minimum frames are insufficient, sequentially checking the filled valid data stream or original data stream by using a parallel 64-bit cyclic redundancy check (CRC)-32 circuit and a serial 8-bit CRC-32 circuit, sequentially checking a 64-bit CRC-32 circuit and valid data stream in an incomplete period by using an 8-bit CRC-32 circuit, simply coding a check result (4bytes) to form a frame check sequence (FCS), filling into the end of the valid data stream, pushing the data stream to a downstream module and sending. Through the technical scheme, the data frames which meet a media access control (MAC) layer of the 10 Gigabit Ethernet can be generated and sent, and the checked data frames are pushed to a next bus or a buffer area without delay.
Description
Technical field
The present invention relates to the Data Detection of ten thousand mbit ethernet high-speed data communication agreements, be specifically related to a kind of filling method of calibration of ten thousand mbit ethernet Frames based on FPGA.
Background technology
In the high-speed data communications system since data flow (comprising pay(useful) load and control flows) can Yin Wendu when transmitting on the line, extraneous interference such as ray, inconsistent phenomenon appears in the data flow that data flow of receiving the recipient and transmit leg send.Error code occurs for guaranteeing to receive to identify wrong data flow and notify on the transmit leg circuit, then need communication process is carried out error control.The error control method that uses on the line has ARQ (request retransmission mode automatically), FEC (forward error correction mode) and HEC (hybrid error correction) at present.More use be the ARQ mode, the error control of this pattern only needs error detection function.
CRC cyclic redundancy check (CRC) code (Cyclic Redundancy Check) is a kind of error check code the most frequently used in the data communication field, it is characterized in that the length of information field and check field can be selected arbitrarily.Because its error monitoring ability is strong, the antijamming capability excellence is widely used in the error control of circuit.
Generate the basic principle of CRC sign indicating number: any one code of being made up of bit string can be only corresponding one by one with the multinomial of ' 1 ' value for ' 0 ' with a coefficient.For example: the multinomial of code 1010111 correspondences is x
6+ x
4+ x
2+ x+1, and multinomial is x
5+ x
3+ x
2The code 101111 of+x+1 correspondence.
The principle that CRC sign indicating number collection is selected: if establishing code word size is N, information field is the K position, and check field is R position (N=K+R), and then there is and only exists a R order polynomial g (x) in arbitrary code word of concentrating for the CRC sign indicating number, makes
V(x)＝A(x)g(x)＝xRm(x)+r(x)；
Wherein: m (x) is K-1 message polynomial, and r (x) is R-1 check polynomial,
G (x) is called generator polynomial:
g(x)＝g
0+g
1x1+g
2x2+...+g
(R-1)x(R1)+g
R×R
Transmit leg produces the CRC code word by the g (x) of appointment, and the recipient then verifies the CRC code word of receiving by this g (x).
Listed CRC and its multinomial of some standards below:
CRC-4：X
1+X+1
CRC-12：x
12+x
11+x
3+x+1
CRC-16：x
16+x
15+x
2+1
CRC-ITU：x
16+x
12+x
5+1
CRC-32：x
32+x
26+x
23+...+x
2+x+1
CRC-32c：x
32+x
28+x
27+...+x
8+x
6+1
Summary of the invention
The object of the invention is to overcome MAC layer data stream and can sends and the timely FCS check information that adds based on CRC-32 by linear speed 10G/b.
A kind of filling method of calibration of ten thousand mbit ethernet Frames based on FPGA comprises following steps:
A, state machine start by the upstream transmission asks to trigger, and data are pushed ahead, and enter format analysis processing for the first time;
B, valid data are carried out bytes calculate, enter step D operation more than or equal to minimum frame, otherwise, execution in step C;
C, according to the frame length polishing of the active traffic of required transmission to minimum frame length;
D, parallel 64 the CRC-32 circuit of application and 8 CRC-32 circuit of serial carry out the flowing water verification to active traffic or original data stream after filling, the active traffic of 8 64 CRC-32 circuit of CRC-32 circuit flowing water verification and non-complete cycle, check results carries out forming FCS after the simple code, be filled into the active traffic ending, data flow be advanced to downstream module send;
E, waiting for IFG all after date, reenter idle condition, repeat this process.
A kind of optimal technical scheme of the present invention is: described C step data adopt 7 road parallel pipelining process data, adopt 64 CRC-32 circuit and 8 CRC-32 circuit when filling.
Another optimal technical scheme of the present invention is: the active traffic that adopts 8 lane of ping pong scheme verification MAC layer transmit leg when data send.
By means of technical scheme of the present invention, can generate and send the Frame that meets ten thousand mbit ethernet MAC layers, the Frame with after the verification that there is no time-delay is advanced to next bus or buffering area.
Description of drawings
Fig. 1 is the state machine transfer process of filling of MAC layer and verification;
Fig. 2 carries out padding scheme less than 7 cycles to frame for frame length;
Fig. 3 carries out padding scheme for frame length equaled for 8 cycles to frame;
Fig. 4 is the sequential flow chart of check part of the present invention.
Embodiment
Below in conjunction with the drawings and specific embodiments method of the present invention is described.
By the upstream driving data, the middle reaches data analysis is advanced to the downstream with data flow again on the link.In Fig. 1, the startup of state machine sends request by the upstream and triggers, and enters into the filling that primary data processing is a lead code.Behind this state, just begin frame format requirement according to Ethernet, Frame with an integral body fill, verification packing sends, and waiting for IFG all after date, reenters idle condition.Wait state is the time that is full of of primary traffic pipelining-stage, by increasing this state, can realize the lasting transmission of follow-up data.At first the function to each module in the communication port elaborates.
In standard ten thousand mbit ethernets, the frame length of each frame must be more than or equal to 64bytes, comprising the FCS verification filler of 4bytes; The demarcation of frame is identified by lead code: 010101 ... 0101011 totally 8 bytes; Fill circuit and adopt the counter way to manage, pad_cnt[3:0] count from the frame preamble sign indicating number, if receiving cycle is smaller or equal to 7 cycles, it is Fig. 2 mode, the situation that equals the need filling in 8 cycles has only three kinds, and is promptly shown in Figure 3, inoperative position added PADDINGbytes form filler, content is random, more than two kinds of the 8th cycles of filling situations be that 4bytes is FCS at last.Data flow after the filling is carried out depositing for 7 times to the data of 8 lane of mac frame with 7 64 bit registers and is duplicated, 64 CRC-32 circuit carry out verification to 8 lane data removing last cycle, verification is to liking the initial data of not duplicating, i.e. fifo[63:0] register; 8 lane data in last week have the situation of 8 valid data, and 8 in full force and effect then continuation of lane adopt 64 CRC-32 circuit that it is carried out verification; All the other situations: 1-7 lane data effectively then adopt 8 CRC-32 circuit serial verifications, each cycle goes out an interim check value, maximum 7 cycle verifications finish, verification to as if the 7th part 64 register value duplicating, here also need a shift register, with 8 CRC-32 circuit of cycle data immigration of effective lane; In the process of 8 CRC-32 circuit to the N frame check, 64 CRC-32 circuit also can carry out verification work simultaneously, the N+1 frame are removed 8 lane data in last cycle and carry out verification, carry out the purpose that ping-pong operation reaches adjacent two frames of linear speed verification with this; The 4bytes data of last 64 CRC32 and one 8 CRC32 circuit associating verifications are added the MAC ending to and are formed FCS.
Claims (3)
1. filling method of calibration based on the ten thousand mbit ethernet Frames of FPGA is characterized in that: comprise following steps:
A, state machine start by the upstream transmission asks to trigger, and data are pushed ahead, and enter format analysis processing for the first time;
B, valid data are carried out bytes calculate, enter step D operation more than or equal to minimum frame, otherwise, execution in step C;
C, according to the frame length polishing of the active traffic of required transmission to minimum frame length;
D, the data flow after filling are carried out depositing for 7 times to the data of 8 lane of mac frame with 7 64 bit registers and are duplicated, 64 CRC-32 circuit carry out verification to 8 lane data removing last cycle, and verification is to liking the initial data of not duplicating: then continue to adopt 64 CRC-32 circuit that it is carried out verification when 8 lane in last cycle are in full force and effect; When the 7th part 64 the register value that 1-7 the lane data in last cycle effectively then adopt 8 CRC-32 circuit serial verifications to duplicate, be provided with shift register simultaneously the cycle data of effective lane is moved into 8 CRC-32 circuit; In the process of 8 CRC-32 circuit to the N frame check, 64 CRC-32 circuit remove 8 lane data in last cycle to the N+1 frame simultaneously and carry out verification, carry out ping-pong operation with this and reach adjacent two frames of linear speed verification; The 4bytes data of last 64 CRC32 and 8 CRC32 circuit associating verifications are added the MAC ending to and are formed FCS; Be filled into the active traffic ending, data flow be advanced to downstream module send.
E, waiting for IFG all after date, reenter idle condition, repeat this process.
2. a kind of according to claim 1 filling method of calibration of ten thousand mbit ethernet Frames based on FPGA is characterized in that: data adopt 7 road parallel pipelining process data, adopt 64 CRC-32 circuit and 8 CRC-32 circuit when filling
3. a kind of according to claim 1 filling method of calibration of ten thousand mbit ethernet Frames based on FPGA is characterized in that: the active traffic that adopts 8 lane of ping pong scheme verification MAC layer transmit leg when data send.
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| CN102055555B true CN102055555B (en) | 2013-07-31 |
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| CN105356966B (en) * | 2014-08-22 | 2019-07-23 | 华为技术有限公司 | Cyclic redundancy check implementation method, device and the network equipment |
| CN107733568B (en) * | 2017-09-22 | 2020-05-12 | 烽火通信科技股份有限公司 | Method and device for realizing CRC parallel computation based on FPGA |
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|---|---|---|---|---|
| CN101764669A (en) * | 2008-12-21 | 2010-06-30 | 重庆川仪自动化股份有限公司 | CRC code check method in data receiving process |
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